JPH0991262A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the system architecture and VLSI chip architecture which realize a high communication performance and a low cost at the time of constituting a distributed memory type multiprocessor system by burying the communication function of a ring bus form in a VLSI chip constituting a processor element. SOLUTION: In the multiprocessor system which has a ring type communication network and performs communication in the master slave form, each of processor elements 13a, 17, and 12a is provided with a node ID register, which sets a node ID to each node, and an ID setting flag. When the ID setting flag is reset, the node ID added to a node ID setting instruction is set to the node ID register and the ID setting flag is set to perform such control processing that the node ID setting instruction is not transmitted to nodes below; and when the ID setting flag is set, the control processing is performed to transmit the node ID setting instruction to nodes on the downstream side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a distributed memory type multiprocessor system using a ring bus type communication network. In particular, the processor elements constituting the multiprocessor system are used for interprocessor communication, data transfer, The present invention relates to a multiprocessor system having a VLSI chip architecture configured with a VLSI (Large Scale Semiconductor Integrated Circuit) chip having a processing mechanism such as synchronization and parallel operation and realizing a high communication function and low cost.

[0002]

2. Description of the Related Art Conventionally, as one of the problems in constructing a multiprocessor system, there is a trade-off between performance and economical efficiency of communication between processors and data transfer. That is, in order to improve the performance of inter-processor communication and data transfer, the communication network becomes complicated and the cost increases. On the contrary, in order to suppress the cost, the performance of inter-processor communication and data transfer is deteriorated.

As an example of the former, in a fully coupled network in which all processors are coupled by a 1: 1 dedicated bus,
Data transfer is fast, but for N processors,
The communication network has a scale of O (N ^ 2), which causes an increase in cost. In the latter example, when a shared bus is used as the communication network, the cost is low, but the width of data transfer is small and the communication performance is poor.

For this reason, for example, as one approach to keep costs low while maintaining relatively high communication performance, VLSI manufacturing technology is used to implement all functions related to interprocessor communication in a single VLSI chip. There is an attempt to manufacture the same as that of the processor or to manufacture the communication function on the same VLSI chip as the processor.

However, in the past, MIMD (multiple instruction multiple data
tream type multiprocessor system, VLS
Considering the feasibility of the communication function by the I manufacturing technology, no proposal of an architecture having a high cost performance ratio has been made.

An example of the prior art which seems to be related to these techniques is, for example, Japanese Patent Laid-Open No. 62-18850.
There is a "broadcast communication control system for ring network" proposed in Japanese Patent Laid-Open Publication No. Hei 4-156655 and an "interprocessor communication system" proposed in Japanese Patent Laid-Open No. 4-156655. In these communication control methods or communication methods, a small capacity data buffer dedicated to data transfer via a communication network connected in a ring is used. Therefore, depending on the state of the node of the communication partner, data transfer cannot be started, and it is necessary to know the state of the node that is the communication partner in advance. However, there are problems that extra communication traffic increases and a dedicated signal line for monitoring the node status is required.

Another example is Japanese Patent Laid-Open No. 62-62.
The "identification number setting method" proposed in Japanese Patent No. 145348 can be mentioned. However, in this identification number setting method, it is inevitable to dedicate an arithmetic circuit and a signal line, and a multi-processor consisting of an extremely large number of processor elements is used. The economics of constructing a processor system are impaired.

[0008]

By the way, such a dedicated circuit can be replaced with a general-purpose arithmetic unit when the communication function and the processor are integrated. Therefore, an object of the present invention is to realize high communication performance and low cost when a distributed memory type multiprocessor system is constructed by embedding a ring bus type communication function in a VLSI chip that constitutes a processor element. System architecture and VLSI chip architecture.

[0009]

In order to achieve the above-mentioned object, the multiprocessor system of the present invention comprises a first
A multiprocessor system in which a plurality of nodes having processor elements are connected via a ring bus type communication network, data communication is performed between the nodes in a master / slave format, and the processor elements of each node perform data processing. In, each processor element stores a node ID register (44) for setting a node ID provided for each node, and an ID for storing an ID setting flag indicating whether or not the node ID provided for each node is set. A setting flag register (43), a reset means (27) for resetting the ID setting flag when the system is reset, a node type setting means (43) for setting a distinction between a master node and a slave node, and the node type setting Means set to masternode In the case, a different node ID to each
An instruction issuing means (27) for issuing a node ID setting instruction for setting a node ID setting instruction, and the node ID setting instruction when the ID setting flag is reset when the node type setting means is set to a slave node. The node ID added to the node ID is set in the node ID register, the ID setting flag is set, a control process for not transmitting the node ID setting command to a downstream node is performed, and the ID setting flag is set. In this case, a control means (27) for performing control processing for transmitting the node ID setting command to a downstream node is provided.

A second feature of the multiprocessor system of the present invention is that a plurality of nodes having processor elements are similarly connected via a ring bus type communication network, and data between the nodes are master / slave type. In a multiprocessor system that performs communication and performs data processing in the processor element of each node, each processor element inputs an instruction code assigned for interprocessor communication, decodes the content, and is required for interprocessor communication. A control circuit (27) for generating a control signal, and a header part generation circuit (38) for assembling a header part of one or a plurality of data transferred in packet format based on the control signal.
An output buffer (32) for temporarily storing the data inside the node, a data input from the ring bus, an output of the header part generation circuit, and data from the output buffer.
Multiplexer (2
9) and a latch circuit (30) for delaying the output of the multiplexer by one clock and outputting it to the next node.

As a third feature of the multiprocessor system of the present invention, similarly, a plurality of nodes having processor elements are connected via a ring bus type communication network, and data between the nodes is transmitted in a master / slave type. In a multiprocessor system that performs communication and performs data processing in the processor element of each node, a dedicated interrupt signal line propagated through the processor element of each node and the processor element of each node are And a communication control processing means (27) for transmitting an interrupt having a higher priority than data communication to another processor element.

As a fourth feature, in the multiprocessor system of the present invention, a plurality of nodes having processor elements are similarly connected via a ring bus type communication network, and data between the nodes are master / slave type. In a multiprocessor system that performs communication and performs data processing in the processor element of each node, a storage unit that stores a descriptor that describes control data related to data transfer between nodes, and a pointer register group that sets a pointer to the descriptor And an updating means for updating the pointer set in the pointer register every time data transfer is processed.

Further, in this case, in the multiprocessor system of the present invention, as a fifth feature, the descriptor is a pointer to a next descriptor, and a pointer to a memory block in which transmission / reception data is stored.
And a data length.

As a sixth characteristic, in the multiprocessor system of the present invention, each processor element is a processor of a master node or a slave node when an external input signal is given to the node type setting means. It is characterized in that it functions as an element. In that case, the seventh feature is that the processor element functioning as a slave node enters a standby mode after reset release and is restarted by an interrupt signal transmitted from the processor element of the master node. . An eighth characteristic is that the processor element functioning as a slave node stores the program or data transmitted via the ring bus in the local memory in the standby mode after reset release.

According to the multiprocessor system of the present invention having such various characteristics, it is possible to easily construct a multiprocessor system having a good cost performance ratio.
More specifically, in a multiprocessor system having a ring-shaped communication network and performing communication in a master / slave format, a node ID register for setting a node ID for each node in each processor element, and an ID setting By providing the flag, it becomes possible to efficiently set the node ID using the ID setting flag without requiring a dedicated arithmetic circuit or a signal line.

Further, the ID setting flag is reset when the system is reset, and the processor element of the master node uses the node ID setting command for setting the node ID to add different node IDs. Are issued as many node ID setting commands as the number of slave nodes. The processor element of the slave node receives the node ID setting instruction, and when the ID setting flag is reset,
The node ID added to the node ID setting command is set in the node ID register, the ID setting flag is set, and the command is not transmitted to the downstream node. Further, when the ID setting flag is set, the processor element of the slave node simply transmits the node ID setting command to the downstream node and does nothing. By the operation of the processor element of each node as described above, it becomes possible to efficiently set the node ID in the processor element of each node.

Further, the processor element of each node constituting the multiprocessor system includes a header section generating circuit for generating a header section of a packet-type bus data communication command, and an output for temporarily storing data inside the node. The buffer, the ring bus data input, the output of the header part generation circuit, and the data output buffer are input to select one multiplexer, and the output of the multiplexer is delayed by one clock and output to the next node. And a latch circuit for performing data transfer at each node connected by the ring bus, the data can be propagated per node in one clock cycle. Data can be transferred by the synchronous method, and data communication between nodes can be performed at high speed.

Further, the multiprocessor system here is provided with a dedicated interrupt signal line propagated through each processor element, and by using this interrupt signal line, the priority is given to the normal communication. As a high interrupt, it operates so as to sequentially notify the processor elements of other nodes. As a result, even when an abnormal situation occurs in the system, it is possible to efficiently deal with it.

Further, for data transfer between the nodes,
It is provided with a pointer register group that sets pointers to descriptors that describe control data for data transfer, and update means that updates the pointers set in these pointer registers each time data transfer is processed. The descriptor relating to the data transfer holds the pointer to the next descriptor, the pointer to the memory block in which the transmission / reception data is stored, the pointer to the memory block in which the transmission / reception data is stored, and the data length. For this reason, the updating means here can inform the state of the descriptor only by updating the pointer, so that efficient data transfer can be performed at high speed.

The circuit configuration of each processor element constituting the multiprocessor system here is as follows.
Instead of having a dedicated circuit configuration for each of the master node and the slave node, as a common circuit configuration,
It is configured by a VLSI (Large Scale Semiconductor Integrated Circuit) chip and operates as a master node or a slave node by software processing. For this reason, a node type setting means is provided, and it is possible to discriminate whether to function as a processor element for a master node or a processor element for a slave node according to the setting, that is, by an external input signal. . When functioning as a processor element for the master node, after releasing the initial system reset, the node ID
Issue a setting command. When functioning as a processor element for a slave node, after releasing the system reset in the initial state, it enters the standby mode, and after initializing the local memory by data such as a program transmitted from the processor element for the master node, It is restarted by an interrupt signal.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a multiprocessor system that implements the present invention in one aspect. In FIG. 1, 10 is a ring bus, 11 is a master node, 12 is a first slave node, 13 is an nth slave node, and 1
4 is a host interface bus, 15 is a bus exchanger,
Reference numeral 16 is a host computer, 17 is a processor element, 18 is a local memory, 19 is an interface circuit, and 20 is a peripheral circuit.

The ring bus 10 is a bus through which data information is transmitted only in one direction. Ring bus 10 here
To the master node 11 and the slave node (1
2, 13) (N + 1) nodes are connected in a ring shape. The node number of the master node 11 is set to “0”, and the node number of each node is one node ahead of the ring bus 10 in the bus data output direction and one node ahead of the ring bus in the bus data input direction. It is a value obtained by adding "1" to the node number of the node. That is, with the master node 11 as the starting node (node number “0”),
The node numbers of the N nodes are 1, 2, 3, ..., (N-
2), (N-1), N.

The master node 11 is a node that controls communication by the ring bus 10. In the basic operation mode, only the processor element 17 belonging to the master node 11 can issue a ring bus communication command. A local memory 18, an interface circuit 19, and a peripheral circuit 20 are connected to the local bus connected to the processor element 17 of the master node 11.

The individual slave nodes 12 to 13 interpret and execute the ring bus communication command. Each slave node (12, 13) includes a processor element (12a, 13a) and a local memory (12).
b, 13b), the processor element (12a, 13a) and the local memory (12b, 13b) are coupled by the local bus. Only the local memory is connected to the local bus of the slave node.
On the other hand, as described above, the local memory 18 is connected to the local bus of the master node 11, and the interface circuit 19 and the peripheral circuit 20 are also connected to the interface circuit 19. A host computer 16 is connected via 15. As a result, the host computer 16 reads and writes data from and to the local memory 18 of the master node 11 via the bus switch 15, the host interface bus 14, and the interface circuit 19.

The internal circuit configuration of each processor element (17, 12a, 13a) in the master node 11 and other slave nodes (12, 13) is as follows.
All have the same configuration, and are configured by VLSI (semiconductor integrated circuit device) chips without having dedicated circuit configurations for the master node and the slave node. Next, the internal circuit configuration of such a processor element will be described.

FIG. 2 is a block diagram showing the internal structure of the processor element. In FIG. 2, 17 is a processor element, 21 is a ring bus interface unit (RBIU), 22 is an internal data bus, 23 is an integer arithmetic unit (IAU), 24 is a floating point arithmetic unit (FAU), and 25 is an instruction cache unit ( IC
U) and 26 are memory interface units (MI
U).

Ring bus interface unit 21
Performs bus communication control processing by the ring bus, and issues, interprets, controls, and executes bus communication commands. As a signal line for the main external interface signals, a ring bus input,
Ring bus output, bus communication command input (bus command input, token input, parity input), bus communication command output (bus command output, token output, parity output),
Signal lines for interrupt input, interrupt output, bus wait input, and bus wait output are provided, and these input lines and output lines are connected in series with the corresponding signal lines of the ring bus interface unit of another adjacent processor element. Connected to. Further, as will be described later, the ring bus interface unit 21 includes a control circuit that inputs an instruction code assigned for inter-processor communication, decodes the content of the instruction code, and generates a control signal necessary for inter-processor communication. There is. The main internal interface of the ring bus interface unit 21 is the internal data bus 22. The internal data bus 22 has an integer arithmetic unit (IAU) 23, a floating point arithmetic unit (FAU) 24, and an instruction cache unit (ICU) 2.
5, the memory interface unit (MIU) 26 is connected, and data transmission between these and the ring bus interface unit 21 is performed.

The integer arithmetic unit 23 includes an arithmetic operation unit (ALU), a register file, etc., and controls the integer arithmetic operation. The integer arithmetic unit 23 includes an instruction processing mechanism that outputs an instruction address to the instruction cache unit 25 and interprets and executes an instruction input from the instruction cache unit 25.

The floating point arithmetic unit 24 includes a floating point adder / subtractor, a floating point multiplier, and a floating point register file, and controls processing of floating point arithmetic. This arithmetic processing is controlled by the floating point arithmetic unit 2
4 interprets the instruction input from the instruction cache unit 25, and executes the floating point arithmetic processing according to the content.

The instruction cache unit 25 inputs the instruction address from the integer arithmetic unit 23, and if there is an instruction corresponding to the internal cache memory (cache hit), outputs it. If there is no instruction corresponding to the internal cache memory (cache miss), the data block including the necessary instruction is input from the external memory (local memory) through the memory interface unit 26, and the integer of the data of the input data block is input. It outputs a command to the arithmetic unit 23.

The memory interface unit 26 includes
Control processing for reading and writing data from and to an external memory (local memory) connected to the outside of the processor element 17 is performed. The control processing of reading and writing data to the memory here executes the memory interface processing as the following four types of tasks. That is, task: a task that performs a process necessary for a load / store instruction to be decoded by the integer arithmetic unit 23. Task: A task of continuously storing data from an external memory inside the floating point arithmetic unit 24, and conversely, continuously storing data from the floating point arithmetic unit 24 to the external memory. Task: A task that performs a process required for a cache miss in the instruction cache unit 25 (a process of inputting a block including a necessary instruction from an external memory and outputting an instruction from the data of the input block). Task: Write the data input from the ring bus via the ring bus interface unit 21 to the external memory. Conversely, the task of reading the data output to the ring bus via the ring bus interface unit 21 from the external memory.

The memory interface unit 26 relating to these four types of tasks and the integer arithmetic unit 2
3, data transfer among the floating point arithmetic unit 24, the instruction cache unit 25, and the ring bus interface unit 21 is all performed via the internal data bus 22. Therefore, the data transfer via the ring bus network can be performed completely independently of the processing of the internal arithmetic unit (23, 24). Further, the data transfer between the networks occupies the internal data bus 22 and the memory interface unit 26, so that competition with other arithmetic units occurs. In that case, the priority is given to the process of data transfer between the networks, so that during this period, if another computing unit requests these resources, it is kept waiting.

FIG. 3 is a diagram showing the types of data held in the registers of each unit of the processor element. The internal registers of the ring bus interface unit 21, the integer arithmetic unit 23, the floating point arithmetic unit 24, the instruction cache unit 25, and the memory interface unit 26 correspond to the blocks of the respective units constituting the processor element shown in FIG. It is shown.

As shown in FIG. 3, the ring bus interface unit 21 includes an input buffer register (IB
R), output FIFO memory (OFR), node ID register (NIDR), group ID register (GID
R), Test & Set flag register (TSFR),
It includes a Test & Set command register (TSCR), interrupt vector register (INTVSR), and ring bus interface unit control / status register (RCSR).

Further, the integer arithmetic unit 23 includes a general-purpose register (R0 to R31), an integer arithmetic unit control / status register (ICSR), and a trap address register (TRAR). The floating point arithmetic unit 24 includes floating point registers (FR0-F).
R15), floating point vector status register (F
VSR), floating point FIFO memory (FFFIFO (3
2)), Floating point unit control / status register (FCSR) is included.

The instruction cache unit 25 also includes
A cache memory (CM) and a tag memory (TM) are included. And the memory interface unit 2
2 is a ring bus instruction pointer (CMDP), SEN
D command pointer (SENDRP), RTRV instruction pointer (RTRVRP), memory block pointer (MEM)
BP), a memory counter (MCNT), and a memory interface unit control / status register (MCSR). Data is temporarily stored using these registers, and data processing in this processor element proceeds.

FIG. 4 is a block diagram showing the internal circuit configuration of the ring bus interface unit, mainly showing the flow of data to the ring bus in the ring bus interface unit. In FIG. 4, reference numeral 22 denotes an internal data bus, which is connected to the internal data bus 22 shown in FIG. 27 is a ring bus interface unit control circuit (RBIU control circuit), 28 is a ring bus data input signal line, 29 is a multiplexer, 30 is a latch circuit, and 31 is a ring bus data output signal line. Further, 32 is an output FIFO memory, 33
Is an input FIFO memory, 35 is a comparator, 36 is an external input / output control signal group in the ring bus data input direction, 37 is an external input / output control signal group in the ring bus data output direction, and 38 is a header section generation circuit. . 39 is another unit (IAU,
FAU, ICU, MIU) input control signal group,
40 is a control signal group output to another unit, 41 is an internal control signal group of the ring bus interface unit (RBIU), 42 is a register file, 43 is a ring bus interface unit control / status register (RCSR), and 44 is a node. ID register (NIDR), 45 is a group ID register (GID
R).

Before explaining the operation of the ring bus interface unit here, first, the ring bus interface unit / status register (RCSR) 4
The control function of 3 will be described. FIG. 5 is a diagram showing a bit configuration of the ring bus interface unit control / status register (RCSR). The meaning of each bit of the ring bus interface unit control / status register (RCSR) is as follows:
The following is defined as the processor architecture that constitutes the processor element. 0th bit (MODE0): Currently, the operation mode of Mode0. First bit (MODE1): Currently, the operation mode of Mode1. Second bit (MODE2): Currently, the operation mode of Mode2. Third bit (MODEX): Currently, the operation mode of ModeX. 4th bit (IFE); Input FIFO memory is empty. Fifth bit (OFE); Output FIFO memory is empty. 6th bit (OFF); Output FIFO memory is full. 7th bit (AND): AND operation of the corresponding bit (state bit) of each processor element is performed. Eighth bit (OR): The corresponding bit (state bit) of each processor element is ORed. 9th bit (CFF); TEST / TESTR / RTR
The return of the command packet of each instruction of V / RTRVA is shown. 10th bit (STATF); indicates that the STAT command is being executed. 11th bit (NID): Indicates that the node ID is set. 12th bit (KPTK): Indicates a token request. 13th bit (AN): Indicates that it is an active node. 14th bit (MN): Indicates the master node. Fifteenth bit (INTC): It is an interrupt generation flag corresponding to the ring bus instruction pointer (CMDP). 16th bit (INTCM): An interrupt mask flag corresponding to the ring bus instruction pointer (CMDP). 17th bit (INTS); SEND instruction pointer (S
This is an interrupt generation flag corresponding to ENDRP). 18th bit (INTSM): This is an interrupt mask flag corresponding to the SEND instruction pointer (SENDRP). 19th bit (INTR): An interrupt generation flag corresponding to the data recovery instruction pointer (RTRVRP). 20th bit (INTRM): An interrupt mask flag corresponding to the data recovery instruction pointer (RTRVRP).

The ring bus interface unit control / status register (RCSR) is a register file (4) for the ring bus interface unit.
2: provided in FIG. 4), and the control operation of the ring bus interface unit is performed based on these bit contents. In this bit configuration, the 0th bit to the 3rd bit are the ring bus interface unit (RBIU).
Represents the respective operating mode in which it operates, and only one of these is always set. At reset, only the 0th bit is set to "1" and the 1st to 3rd bits are reset. Also, the 4th bit ~
The sixth bit is an input / output buffer (input FIFO memory,
This bit indicates the status of the output FIFO memory). Bits 7 to 8 are status bits relating to the STAT instruction, and bit 9 is TEST /
This is a status bit indicating that the processing of each instruction of the TESTR / RTRV / RTRVA instruction is completed. Also,
The 10th bit is a status bit indicating that the status of the 7th bit to the 8th bit obtained as the processing result of the STAT instruction (state check instruction) is valid.

The eleventh bit is a status bit indicating whether the contents of the node ID register are valid or invalid.
This bit is also reset when the processor element chip is reset. The 12th to 13th bits are status bits of a communication request used in the operation mode of Mode 1 described below, and the 12th bit represents a state in which a token is requested, that is, the issuance of a communication command. It represents the requested state. Also,
The thirteenth bit represents the state where the own node has the token.

The 14th bit is a status bit indicating whether the own node is the master node or the slave node, that is, the processor element of the own node operates as the master node, or , And whether it operates as a slave node. The 14th bit is set by the external input signal and is reflected as it is in the value of this bit. When connected to the power supply (when set to "1"), the master node operates. When connected to ground (when set to "0"), operates the slave node. To do.

The fifteenth to sixteenth bits enable an interrupt bit set in the instruction issue node and the interrupt when the processing of a ring bus instruction (CMD instruction, CMDA instruction) described below is completed. / Mask bit to be invalidated. Also, the 17th bit to the 1st
8 bits are used for transfer instructions (SEND instruction, S
The interrupt bit is set in the instruction issue node when the processing of the (ENDA instruction) is completed, and the mask bit for enabling / disabling the interrupt. The 19th to 20th bits are interrupt bits set in the instruction issuing node and enable / disable of the interrupt when the processing of the data recovery instruction (RTRV instruction, RTRVA instruction) described below is completed. This is the mask bit to be used.

Next, the ring bus interface function for performing data communication by interprocessor communication in the multiprocessor system of this embodiment will be described.
In this case, in a multiprocessor system, four operation modes (Mode0, Mode1, Mode2, ModeX)
In addition to performing data communication between processors, a status check function for other processor elements and an interrupt function for another processor are provided.

The transfer mode in data transfer is Mode
The operation is performed in any one of four operation modes of 0, Mode1, Mode2 and ModeX. The operation mode of Mode 0 is a data transfer mode in which the master node manages and controls all data transfers on the ring bus to a plurality of slave nodes. Therefore, in this case, data transfer is performed under the control of the master node. The operation mode of Mode 1 is that among nodes (processor elements) connected on the ring bus, one active node (processor element) having a token manages all data transfer on the ring bus with respect to other passive nodes. This is the data transfer mode to control. Therefore, in this case, the data transfer is controlled by one node having the token (the processor element of the active node).

The operation mode of Mode 2 is a mode in which a combination of two nodes connected to the front and rear by a ring bus independently transfers data. Therefore, in this case, data transfer is individually performed under the control of each node. In addition, the operation mode of ModeX is
It is a failure mode. This mode is set when a failure is found in the function of the node. Nodes that are set to ModeX operation mode (in ModeX state)
Always pass the data as it is so as not to impair the function of the entire ring bus. In other words, Mode in this case
A node set to the X operation mode is the same as not existing on the ring bus.

Next, the ring bus instruction used in such an operation mode will be specified. The following is a list of ring bus instructions. SEND: Data transfer command SENDA: Data transfer command with address RTRV: Data recovery command RTRVA: Data recovery command with address MODE0: Mode switching command to Mode0 MODE1: Mode switching command to MODE1 MODE2: Mode switching command to MODE2: MODEX: Mode switching command to ModeX SETNID: Node ID setting command SETGID: Group ID setting command STAT: Status recovery command RESNID: Node ID reset command TESTS: Test & Set command TESTR: Test & Reset command INTH: Hardware interrupt command INTS B: NOP command: Software interrupt command BUSNOP instruction (no operation instruction)

These ring bus instructions are assigned within the instruction set of the integer arithmetic unit (IAU) 23, and the integer arithmetic unit 23 accepts these ring bus instructions, reads, decodes and analyzes them. The calculation control signal of is transmitted. That is, when the integer arithmetic unit 23 inputs and decodes the ring bus instruction, it is transmitted to the ring bus interface unit control circuit 27 through the signal line of the control signal group 39. Performs the control operation corresponding to the instruction.

In the operation modes of Mode 0 and Mode 1, as described above, only the master node (or active node) can issue the ring bus instruction, and the slave node (or passive node).
Only receives, interprets and executes instructions. However, the INTH instruction (hardware interrupt) can be issued in the slave node (or passive node). The hardware interrupt due to this INTH instruction is transmitted to the processor element of each node by an interrupt signal line.

In the operation mode of Mode2, all nodes cannot issue any instruction other than the INTH instruction. An example of the data structure of the packet format of the ring bus instruction is shown in FIG. FIG. 6 is a diagram showing a packet format of the SEND instruction. In FIG. 6, 100
Is a packet format of the SEND command, 100a is a command field, 100b is a data length field, 100
c is a source field and 100d is a destination field. Further, reference numeral 100e indicates a dummy packet, and reference numeral 100f indicates a data packet.

As shown in FIG. 6, the packet format 100 of the ring bus instruction is 1 for 64-bit packets.
It is composed of one or more pieces, and the content thereof is composed of an instruction packet (header section) and a data packet (data section) following it. Each of these instruction packets and data packets, one packet per clock, propagates individually or continuously on the ring bus, and the packet format of the instruction packet and the data packet of the ring bus instruction to each node. The whole is told. In this case, for example, as shown in FIG. 4, since the signal passes through one node, when it propagates from the ring bus data input 28 to the ring bus data output 31, it is transmitted in synchronization via the latch circuit 70. Therefore, a delay of one clock cycle occurs. Therefore,
Instruction and data packets propagate through each node on the ring bus with a delay of one clock cycle per node. A data packet (ring bus instruction) in the packet format of the ring bus instruction as shown in FIG. 6 goes around the ring bus to the node that issued the instruction, and the propagation is stopped there.

The node address of each node on the ring bus is set by the node ID and the group ID. The node ID is set so that each node ID is unique within the range of "0" to "32767" (15-bit binary number), and the group ID is "0" to "14" (each of 15 bits). It is set to each node within the range of (position).

Therefore, the value of the node ID (15-bit binary number) of the node that issued the packet is stored as it is in the source ID field (hereinafter referred to as src field) 100c in the instruction packet of the ring bus instruction. To be done. In addition, the destination node ID field (hereinafter referred to as the "dest field") 100d that designates the destination of transmission includes single node designation (unicast), multiple node designation (multicast), and all node designation (broadcast). Yes, the value of the node ID or the group ID is set according to each designation.

When a single node is designated, the node ID of the designated node is directly set in the dest field 100d. In this case, the MS of the dest field
B (15th bit) is "0", and the value of the node ID of the designated partner node is stored as it is in the 0th bit to the 14th bit. In the case of designation of a plurality of nodes, the MSB (15th bit) of the dest field 100d is set to "1", and the bit position from the 0th bit to the 14th bit is set to the position corresponding to the group ID. The 1 "bit specifies the group ID. For example, the dest field 100
The address of the bit expression set in d is "1000000."
In the designation of "000000101", the MSB (15th bit) is "1", and the designation of multiple nodes (multicast) is made. From the 0th bit to the 14th bit, the group ID is "0"
Or it means selecting the node of "2".
In this way, each node is designated by the bit position set in the dest field 100d. Therefore, here, all nodes are designated (broadcast).
In this case, all the 0th to 15th bits are set to "1" to instruct designation of all nodes. Next, for each ring bus instruction, an operation example when the instruction is executed will be described.

SEND Command (Data Transfer Command) FIG. 6 described above shows the data structure of the packet format of the SEND command, which will be described with reference to FIG. In the processor element of the master node or the active node that executes the SEND instruction, the ring bus interface unit 21 sends the data to be transferred according to the packet format 100 of the SEND instruction.

In this case, in the packet format 100 of the SEND instruction, the instruction code stored in the instruction field 100a of the first instruction packet is received from the integer arithmetic unit 23 and stored. Also, as the value of the node ID of the src field 100c indicating the transmission source,
The value of the node ID register (NIDR) 44 is stored. The data length field (hereinafter referred to as the len field) 100b, the dest field 100d,
The values to be stored in the data packet 100f and the data packet 100f are read out from the local memory and stored by performing memory access according to the data structure described below. In addition, the instruction packet (1
00a to 100d) and the data packet 100f, a dummy packet 100e is inserted according to the timing adjustment of data reading. In the packet format 100 of this SEND command, two dummy packets are inserted.

FIG. 7 is a diagram for explaining the data structure for reading data used when executing the SEND instruction. As shown in FIG. 7, a ring bus instruction pointer (CM
In the DP) 47, a pointer to a data structure for reading data in this case is set in advance. The memory interface unit (MIU) 26 accesses the descriptor block (desc) 120 stored in the local memory by outputting the content of the ring bus instruction pointer (CMDP) 47 as a memory address. Descriptor block (desc) 1
7, the descriptor pointer field (desp) 120a, the memory block pointer field (mem) 120b, the data length field (len) 120d, and the destination address field (dest) 120f are provided in FIG. There is. Areas corresponding to two 64-bit packets are allocated to store data in each field, but unused areas are left as unused areas 120c and 120e.

Descriptor pointer field (de
sp) 120a is set to the start address of the next descriptor pointer when data continues. For the next SEND instruction, the ring bus instruction pointer (CM
The DP) 47 contains the descriptor pointer (des).
p) The value of 120a is entered. The start address of the data area 121 to be transferred is set in the memory block pointer field (mem) 120b. The value of the memory block pointer field (mem) 120b is written in the memory block pointer (MEMBP) of the register group of the memory interface unit (MIU) 26, and when reading the data, the data value of the memory block pointer (MEMBP). Is output as an address while being incremented.

In the data length field (len) 120d, le of the packet format 100 of the SEND instruction is set.
The data length stored in the n field 100b is set. Further, in this case, the data length is set in the memory counter (MCNT) of the register group of the memory interface unit (MIU) 26 and is used to count the number of data in the data area 121 to be transferred. Also,
In the destination address field (dest) 120f,
DEST of packet format 100 of SEND instruction
The destination address set in the field 100d is set.

The data read and transferred from the memory access having such a data structure is transferred from the local memory to the ring bus interface unit 21 through the local bus, the memory interface unit (MIU) 26 and the internal data bus 22. Sent and sent out on the ring bus. In the ring bus interface unit 21, as shown in FIG. 4, the data read through the internal data bus 22 is stored in the output FIFO memory 32, and the multiplexer 29 and the latch circuit 3 are stored.
It is output from the signal line of the ring bus data output 31 via 0. The data transfer timing in this case is shown in FIG.

FIG. 8 is an iming chart for explaining the data transfer timing of data transmission by the SEND instruction. That is, as shown in FIG. 8, when the SEND instruction is issued, at the first clock, the issue of the ring bus instruction is instructed by the command output signal, and at the timing of the clock, as the ring bus data output, Packets in the packet format are sequentially output to. A command packet (Header) is first transmitted to the ring bus data output, and then a data packet is transmitted. In that case, the reading of the data to be transferred is started, and the data is read from the local memory via the local bus and the internal data bus. However, at the second clock, the transfer data (first data packet) The transfer data (first data packet) is placed on the internal data bus at the third clock that follows. Then, the transfer data (first
The fourth data packet) is sent out as the ring bus data output only after the fourth clock.
Therefore, here, two dummy packets (Dummy)
Are transmitted subsequently to the command packet (Header), and the first data packet is transmitted after the fourth clock.

Next, the data receiving operation in the slave node or the passive node which receives the packet of the SEND command will be described. In the processor element of the slave node or the passive node, the ring bus interface unit 21 receives the SEND command packet from the ring bus data input 28, as shown in FIG.
The value of the node address in the dest field 100d of the packet format 100 and the node ID register (NIDR) 44 or the group ID register 45
The value of the node address set in is compared. In this case, the comparator 35 uses the MS of the dest field 100d.
If B (15th bit) is "0", the value of the node address in the dest field 100d is compared with the node ID register (NIDR) 44, and dest
MSB (15th bit) of field 100d is "1"
If so, the value of the node address of the dest field 100d is compared with the group ID register (GIDR) 45 at the bit position.

As a result of this comparison operation, if the address conditions of the node address match, the data packet following the command packet of the SEND command is input from the ring bus data input 28 and stored in the input FIFO memory 33. It When the address conditions of the node address do not match, the instruction packet and the data packet input from the ring bus data input 28 are the multiplexer 29, the latch circuit 30, and the ring bus data output 31.
It is output as it is via.

When the address conditions of the node address match, the instruction packet and the data packet input from the ring bus data input 28 are not output to the next node (this rule will be described below. Applies to all orders). The data packet stored in the input FIFO memory 33 is stored at a predetermined address in the local memory via the internal data bus 22 and the local bus according to the memory access method based on the data structure similar to that described above.

FIG. 9 is a diagram for explaining the data structure for storing data used when the SEND instruction is executed. As shown in FIG. 9, in the memory access by the data structure of the descriptor block in this case, SEND
A pointer to this data structure is preset in the instruction pointer (SENDRP) 48. The memory interface unit (MIU) 26 accesses the descriptor block (desc) 122 in the local memory by outputting the SEND instruction pointer (SENDRP) 48 as a memory address. In the descriptor block (desc) 122 in this case, as shown in FIG. 9, the descriptor pointer field (de
sp) 122a, memory block pointer field (mem) 122b, data length field (len)
122d and the source address field (sr
c) 122e is provided. Areas corresponding to two 64-bit packets are allocated so as to store data in each field, but unused areas are left as unused areas 122c and 122f.

Descriptor pointer field (de
sp) 122a is set with the start address of the next descriptor pointer. For the next SEND command,
The value of the descriptor pointer (desp) 122a is stored in the SEND instruction pointer (SENDRP) 48. Memory block pointer field (mem
p) 122b, the start address of the data area 123 for storing the transmitted data is set. The value of the memory block pointer field (mem) 122b is written in the memory block pointer (MEMBP) of the register group of the memory interface unit 26, and when the data is written, the value of the memory block pointer (MEMBP) is incremented, It is output as an address. Data length field (len) 1
The len field 100b of the packet format 100 of the sent SEND instruction is written in 22d. Further, this data length field (len) 122
The value of d is set in the memory counter (MCNT) of the register group of the memory interface unit 26 and used to count the number of data in the data area 123. In this case, the source address field (sr
c) 122e contains sr of packet format 100
The source address entered in the c field 100c is set.

The data written by the memory access according to this data structure is the input FIFO memory 33.
(FIG. 4), transferred to the local memory through the internal data bus 22 and the local bus. The data transfer timing in this case is shown in FIG. Figure 10 shows SEN
7 is a timing chart illustrating a data fetching timing of a data receiving process by a D command. As shown in FIG. 10, when the data transfer by the packet of the SEND command is accepted and the reception process is started, if the address conditions of the node address of the command packet match, the data packets are sequentially received and are input to the input FIFO memory 33. Store temporarily.

In this case, the reason why there is a delay of 9 clock cycles between the input of data from the ring bus and the transfer of the data from the input to the internal data bus is that the processor element of the receiving node uses the internal data bus. It is necessary to obtain the right to use 22 to read the descriptor block (desc) 122 and set the data for controlling the data writing in each register, which requires 9 clock cycles. is there. The delay time of 9 clock cycles is absorbed by the data packet stored in the input FIFO memory 33.

SENDA instruction (data transfer with address
Command) FIG. 11 is a diagram showing a packet format of a SENDA command. In FIG. 11, 101 is the packet format of the SENDA command, 101a is the command field,
101b is a data length field, 101c is a source field, 101d is a destination field,
101e is an address field. Also 101f
Indicates a dummy packet and 101g indicates a data packet. In the packet format 101 of the SENDA command here, in addition to the fields of the packet format 100 of the SEND command described above, an address field 101e is further added.

In the master node or the active node which executes such a SENDA instruction, the ring bus interface unit (RBIU) 21 of the processor element, in accordance with the packet format 101 of the SENDA instruction as shown in FIG. Along with the addition of the address by, the data to be transferred is transmitted by the data packet.

In this case, in the packet format 101 of the SENDA instruction, the instruction code stored in the instruction field 101a of the first instruction packet is received from the integer arithmetic unit 23 and stored, as in the case described above. In addition, a source field (hereinafter referred to as src field) 101c that stores a node ID indicating a transmission source.
The node ID value of the node ID register (NI
The value of (DR) 44 is stored. A data length field (hereinafter referred to as a len field) 10 for storing the data length
1b, a destination field (hereinafter referred to as a "dest field") 101d for storing a destination, and a value to be stored in a data packet 101f are memory-accessed by a data structure as described below, data read processing is performed, and a local memory is used. Read from and store. A dummy packet 101f is inserted between the instruction packet (100a to 100e) and the data packet 101g according to the timing adjustment of data reading. Here, one dummy packet is inserted.

The operation of data transfer by the SENDA instruction is basically the same as that of the SEND instruction.
The difference is that the address field 101e for storing the memory address of the data transmission destination is added to the instruction packet, and the processing related to the memory address is added. FIG. 12 is a diagram showing a data structure for memory access used when the SENDA instruction is executed. Memory access in this case will be described with reference to FIG.

Ring Bus Instruction Pointer (CMDP) 47
In, a pointer to this data structure is preset.
The memory interface unit (MIU) 26 outputs the ring bus instruction pointer (CMDP) 47 as a memory address, so as to output the disc pointer pointer block (des) stored in the local memory.
c) Access 124.

Discrete pointer block (des
The structure of c) 124 is the same as that of the above-mentioned discriter pointer block (desc) 120 of FIG. 7 except that an address field 124g for storing the memory address of the data destination is added. That is,
As shown in FIG. 12, the descriptor block (des
c) 124 has a descriptor pointer field (desp) 124a, a memory block pointer field (mem) 124b, and a data length field (le).
n) 124d, destination address field (dest)
124f, and address field (addr) 12
4g is provided. In this case, areas corresponding to three 64-bit packets are allocated so as to store data in each field. Also in this case, unused areas are left as unused areas 124c and 124e.

Descriptor pointer field (de
sp) 124a is set with the start address of the next descriptor pointer when data continues. For the next SENDA instruction, the ring bus instruction pointer (C
The MDP 47 contains the descriptor pointer (de
sp) The value of 124a is entered. The start address of the data area 125 to be transferred is set in the memory block pointer field (mem) 124b. The memory block pointer field (mem) 124b
Value of the memory interface unit (MIU) 26
Register block memory block pointer (MEMBP)
When the data is read, the data value of the memory block pointer (MEMBP) is output as an address while being incremented.

The data length field (len) 12
In 4d, the data length stored in the len field 101b of the packet format 101 is set. In this case, the data length is set in the memory counter (MCNT) of the register group of the memory interface unit (MIU) 26, and the data area 12 to be transferred is set.
Used to count the number of 5 data. In the transmission destination address field (dest) 124f, the transmission destination address set in the dest field 101d of the packet format 101 is set. The address field (addr) 124g stores the value of the address field 101e that stores the memory address of the data destination.

The data read and transferred from the memory access having such a data structure is the SEN described above.
As in the case of the D instruction, the local memory to the local bus, the memory interface unit (MIU) 26,
Then, it is sent to the ring bus interface unit 21 through the internal data bus 22 and sent out on the ring bus. In the ring bus interface unit 21, as shown in FIG. 4, the data read through the internal data bus 22 is stored in the output FIFO memory 32, and the ring bus data output 31 through the multiplexer 29 and the latch circuit 30. Is output from the signal line of. The data transfer timing in this case is shown in FIG.

FIG. 13 is a timing chart for explaining the data transfer timing of data transmission by the SENDA instruction. In this case, as shown in FIG.
When an instruction is issued, at the first clock, the command output signal instructs the issuance of a ring bus instruction, and at the timing of that clock, packets of the packet format are sequentially output as ring bus data output. It Here, since an address is added to the command packet of the ring bus command, two command packets (Header1, Header2) are sent. Therefore, first, the first command packet (Header 1) is sent to the ring bus data output, and then the second command packet (Header 3) is sent. Then, the data packet is transmitted. Also in this case, the reading of the data to be transferred is started, and the data is read from the local memory via the local bus and the internal data bus.
Since the transfer data (first packet) is loaded on the local bus at the second clock, the transfer data (first packet) is loaded on the internal data bus at the subsequent third clock. Therefore, the transfer data of the first packet is sent to the ring bus data output only after the fourth clock.
Therefore, here, one dummy packet (Dummy)
Are transmitted subsequently to the instruction packet (Header1, Header2), and the first data packet is transmitted after the fourth clock.

Next, the data receiving operation in the slave node or the passive node which receives the packet of the SENDA command will be described. In the processor element of the slave node or the passive node, the ring bus interface unit 21 receives the SENDA command packet from the ring bus data input 28 as shown in FIG.
By the comparator 35, the packet format 101 de
The value of the node address in the st field 101d is compared with the value of the node address set in the node ID register (NIDR) 44 or the group ID register 45. In this case, if the MSB (15th bit) of the dest field 101d is “0”, the comparator 35 compares the value of the node address of the dest field 101d with the node ID register (NIDR) 44. If the MSB (15th bit) of the dest field 101d is "1", the value of the node address of the dest field 101d and the group ID register (GID
R) 45 is compared at the bit position.

If the address condition of the node address matches as a result of the comparison operation, the data packet of the packet of the SENDA instruction is input from the ring bus data input 28 and stored in the input FIFO memory 33.
When the address conditions of the node addresses do not match, the packet input from the ring bus data input 28 is output as it is via the multiplexer 29, the latch circuit 30, and the ring bus data output 31.

In this case, the slave node or passive node receiving the SENDA command stores the data packet in the input FIFO memory 33 and writes the data packet in the local memory if the address meets the condition. The slave node or passive node that receives the instruction does not use the above-mentioned data structure for storing the data in the memory.

That is, in the SENDA command, since the address for storing the data is added, the address of the addr field 101e in the command packet is
Write directly to the memory block pointer (MEMBP) of the memory interface unit (MIU) 26, and put the data length of the len field 101b of the instruction packet into the memory counter (MCNT) to count the number of data to be written to the local memory. Used for. The data to be written is transferred to the local memory through the input FIFO memory 33 (FIG. 4), the internal data bus 22, and the local bus. The data transfer timing in this case is shown in FIG.

FIG. 14 is a timing chart showing the internal data transfer timing at the receiving node according to the SENDA instruction. As shown in FIG. 14, when the data transfer by the packet of the SENDA command is accepted and the reception process is started, if the address conditions of the node address of the command packet match, the data packets are sequentially received and are input to the input FIFO memory 33. Store temporarily.

In this case, the reason why there is a delay of 9 clock cycles between the input of the ring bus data and the transfer of the data from the input to the internal data bus is that the processor element of the receiving node uses the internal data bus. In order to obtain the right to use 22 to set the address and data length in the respective registers and finish the process for controlling the data write, as described above,
This is because that number of cycles is required. The delay time of this 9 clock cycle is as follows:
It is stored in the FO memory 33 and absorbed.

RTRV (Data Collection Command) FIG. 15 is a diagram showing a packet format of the RTRV command. In FIG. 15, 102 is the packet format of the RTRV command, 102a is the command field, 10
2b is a data length field (hereinafter referred to as len field), 102c is a source field (hereinafter referred to as src field), and 102d is a destination field (hereinafter referred to as dest field).
Further, 102e indicates a dummy packet, and 102f indicates a data packet.

The processor element of the master node or the active node which executes the RTRV instruction sends the packet of the RTRV instruction in its ring bus interface unit (RBIU) according to the packet format 102 shown in FIG. However, when executing this ring bus instruction, the node issuing the RTRV instruction is the packet format 1 of the RTRV instruction.
02 instruction field 102a, len field 10
2b, the src field 102c, and the first 64-bit instruction packet including the dest field 102d are transmitted. Also, the len field 102 in this case
The data length and the value of the node ID stored in the b and dest fields 102d are used for the memory access by the data structure similar to the data structure as shown in FIG. It is read from a similar data structure. RTRV
The instruction is valid only for single node specification (unicast).

On the ring bus, the slave node or passive node which has received the instruction packet of the RTRV instruction receives the RTRV instruction from the ring bus data input 28 in the processor-emulated ring bus interface unit 21 as shown in FIG. Is received, the value of the node address in the dest field 102d of the packet format 102 and the node ID register (NIDR) are received by the comparator 35.
44 or the value of the node address set in the group ID register 45 is compared. In this case, only the single node designation (unicast) is effective, and substantially only the node IDs are compared.

If the node address conditions are matched by comparing the node IDs, the node performs the process of transmitting the transfer data. Therefore, as shown in FIG. 9, similar to the operation of the SEND instruction described above. , SEND instruction pointer (SENDRP) 48 is used to perform memory access using the same data structure as the data structure linked to the SEND instruction pointer (SENDRP) 48, read data from the local memory, and send transfer data to the ring bus. However, in the operation by this RTRV instruction, when the register storing the start address of the data structure for memory access is the node that receives the RTRV instruction, the RTRV instruction pointer (RT
RVRP). That is, in FIG. 9, instead of the data of the SEND instruction pointer (SENDRP) 48, R
The data of the TRV instruction pointer (RTRVRP) is used, and the memory access is performed by the similar data structure.

In this case, the memory interface unit (MIU) 26 uses the RTRV instruction pointer (RTRVR).
By outputting the value of P) as a memory address,
Descriptor block (des) in local memory
c) Access 122. The descriptor block (desc) 122 is provided with a descriptor pointer field (desp) 122a, a memory block pointer field (mem) 122b, a data length field (len) 122d, and a transmission source address field (src) 122e.

At the node which has received the command packet of the RTRV command, the data reading is performed as follows. The data length of the len field 102b in the received instruction packet is the data length field (122) of the descriptor accessed by the RTRV instruction pointer in the memory interface unit 26.
It is written in d), and further, memory counter (MCNT)
Is used to count the number of data written to and read from. Also, the src field 1 in the instruction packet
02c is a descriptor block for the RTRV instruction (d
esc) 122 source address field (src)
It is written in 122e. Data is read starting from the address designated by the memory block pointer field (mem) 122b of the descriptor block block (desc) 122, and the internal data bus 22, the output FIFO memory 32, the multiplexer 29, the latch circuit 30, and the ring bus data are read. It is sent out on the ring bus via the route of the output 31.

FIG. 16 shows the data read timing in the slave node or the passive node which has received the RTRV instruction in this case. Figure 16 shows R
7 is a timing chart illustrating a data transfer timing of data transmission according to a TRV command. As shown in FIG. 16, when the instruction packet (Header) of the RTRV instruction is received together with the command input signal by the ring bus data input, the transfer data is sent from the node in the next clock cycle. The command packet (Header) is sent as ring bus data output together with the command output signal. Then, the dummy packets (Dummy) are continuously transmitted as ring bus data output until the timing at which the data packets can be transmitted. During this time, the processor element of the node obtains the right to use the internal data bus 22,
It takes 9 clock cycles to complete the process for the descriptor (desc) 122 for memory access of the local memory. After the elapse of this processing time, the read first data is loaded on the local bus, and subsequently, in the next clock cycle, the read first data is transferred from the memory interface unit 26 to the internal data. It is put on the bus and sent out as a link bus data output from the ring bus interface unit 21 in the next clock cycle. During this time, the ring bus interface unit 21
In, the dummy packet (Dummy) is continuously transmitted.

In this way, in response to the RTRV instruction, the transfer data is sent from the corresponding node onto the ring bus. On the other hand, in the master node or active node that issued the RTRV command, R
When the TRV command makes a round trip on the ring bus and returns,
As shown in FIG. 7, the transferred data packet is input according to the data structure used in the memory access by the ring bus instruction pointer (CMDP) 47, and the data is written in the local memory.

FIG. 17 is a timing chart showing the timing of data writing in the node which has received the transfer data according to the RTRV instruction. Referring to FIG.
Here, the timing of data writing in the master node or the active node that has received the transfer data according to the RTRV command will be described. As described above, the data written by the memory access according to the data structure shown in FIG. 7 is transferred to the local memory through the input FIFO memory 33 (FIG. 4), the internal data bus 22, and the local bus. The data transfer by the command packet is accepted and the reception process is started.
Also in this case, as described above, it takes 9 clock cycles to read the data in the corresponding node that sends the transfer data, and further, it takes 2 clocks before the read data is loaded on the ring bus. Since it takes a clock cycle time, the data packet is transferred after 11 clock cycles through the dummy packet.

Therefore, the dummy packet is received in response to the data transfer by the command packet (Header) of the RTRV command, and the first data packet is received after 11 clock cycles. The received data packet is
The data is sequentially stored temporarily in the input FIFO memory 33, and written in the local memory via the internal data bus, the memory interface unit and the local bus.

RTRVA instruction (data with address recovery instruction
Decree) Figure 18 is a diagram showing a packet format of RTRVA instructions. In FIG. 18, 103 is the packet format of the RTRVA command, 103a is the command field,
103b is a data length field, 103c is a source field, 103d is a destination field,
103e is an address field. Also, 103f
Indicates a dummy packet, and 103g indicates a data packet. The packet format 103 of the RTRVA command here has an address field 103e added to each field of the packet format 102 of the RTRV command described above.

The master node or the active node which executes the RTRVA instruction receives the data of the instruction packet of the RTRVA instruction from the ring bus interface (RBIU) 21 of the processor element according to the packet format 103 of the RTRVA instruction as shown in FIG. Is sent. Even in this case, RTRV
Similar to the operation of the instruction, the node issuing the RTRVA instruction has the instruction field 103a, the data length field (hereinafter referred to as the len field) 103b, and the source field (hereinafter referred to as the src field) 103 in the packet format 103 of the RTRVA instruction.
c, the destination field (hereinafter referred to as the "dest field") 103d, and the address field (hereinafter referred to as the "addr field") 103e. The len field 103b, dest in this case
Field 103d, and addr field 103
The data length, node ID, and address values stored in e are
Memory access is performed by a data structure similar to the data structure as shown in FIG. 12 described above, and data is read from the same data structure as the data structure for memory access of the SENDA instruction. The RTRVA instruction is valid only for single node designation (unicast).

The data transfer operation by this RTRVA instruction is basically the same as the above-mentioned RTRV operation, and the difference is that an address for memory access is added to the instruction packet in the instruction. Is that
That is, processing related to the memory address is added.

Next, the operation of the slave node or passive node that has received the RTRVA command will be described. On the ring bus, the slave node or the passive node that has received the instruction packet (Header 1) of the RTRVA instruction receives the RTRVA instruction from the ring bus data input 28 in the processor-emulated ring bus interface unit 21 as shown in FIG. Of the first instruction packet (Header1) of FIG.
As shown in, the comparator 35 compares the value of the node address in the dest field 103d of the packet format 103 with the value of the node address set in the node ID register (NIDR) 44 or the group ID register 45. In this case, since only the single node designation (unicast) is effective, only the node IDs are practically compared.

By comparing the node IDs, if the condition of the node address is met, the process for transmitting the transfer data is performed by the node, so that the second command packet (Header 2) is sent as in the operation of the SENDA command. The address is used to perform memory access, read data from the local memory, and transfer data to the ring bus. That is, if the address conditions are met, the data length of the len field 103b in the instruction packet and the address of the addr field 103e are used to read the data from the local memory and send it to the ring bus. The value of the data length of the len field 103b is written in the memory counter (MCNT) and is used to count the number of data to be read. a
The ddr field 103e is written in the memory block pointer (MEMBP).

The data read from the local memory is output through the path of the internal data bus 22, the output FIFO memory 32, the multiplexer 29, the latch circuit 30, and the ring bus data output 31. FIG. 19 shows the timing of data reading in the slave node or passive node that has received the RTRVA command.

FIG. 19 is a timing chart for explaining the data transfer timing of data transmission by the RTRVA instruction. As shown in FIG. 19, the first of the RTRVA instructions
When the second command packet (Header1) is received together with the command input signal by ring bus data input, the transfer data is sent from the node in the next clock cycle. The data output is sent together with the command output signal. In this case, the second command packet (Header2) including the address is
Since it is received by the ring bus data input, it is delayed by one clock cycle and the RTRV
The second command packet (Header 2) of the A command is sent as ring bus data output.

Then, until the timing at which the data packet can be transmitted subsequently, the ring bus data output,
Dummy packets are sent continuously. Meanwhile, in the processor element of the node, it takes 9 clock cycles to obtain the right to use the internal data bus 22 and finish the processing for the address setting for the memory access of the local memory. After the elapse of this processing time, the read first data is loaded on the local bus, and subsequently, in the next clock cycle, the read first data is transferred from the memory interface unit 26 to the internal data. It is put on the bus and sent out as a link bus data output from the ring bus interface unit 21 in the next clock cycle. During this time, in the ring bus interface unit 21, a dummy packet (Dummy)
Are continuously transmitted, in this case, nine dummy packets are transmitted.

Thus, in response to the RTRVA instruction, the transfer data is sent from the corresponding node onto the ring bus. On the other hand, in the master node or active node that issued the RTRVA command,
When the RTRVA instruction makes a round on the ring bus and returns, as shown in FIG. 12, the ring bus instruction pointer (CMDP) 47 makes a memory access according to the data structure using the descriptor block and is transferred. Input a data packet and write the data to local memory.

FIG. 20 is a timing chart showing the timing of data writing in the node that has received the transfer data according to the RTRVA instruction. With reference to FIG. 20, the timing of data writing in the master node or the active node that has received the transfer data according to the RTRVA instruction will be described. As previously mentioned,
The data written by the memory access according to the data structure shown in FIG. 12 is transferred to the local memory through the input FIFO memory 33 (FIG. 4), the internal data bus 22, and the local bus. In this case, the RTRVA is used.
The data transfer by the command packet of the command is accepted, and the receiving process is started. As described above, it takes 9 clock cycles to read the data at the corresponding node that sends the transfer data after receiving the RTRVA instruction, and before the read data is loaded on the ring bus. Since it takes 2 clock cycles,
A data packet is sent after 11 clock cycles from the instruction packet through 9 dummy packets.

Therefore, in response to the data transfer by the command packet (Header1, Header2) of the RTRVA command,
After receiving 9 dummy packets, that is, 11 clock cycles after the start of receiving the instruction packet, the first
Receive the th data packet. The received data packet is sequentially temporarily stored in the input FIFO memory 33, and is written in the local memory via the internal data bus, the memory interface unit and the local bus.

MODE0 instruction, MODE1 instruction, MOD
E2 instruction, MODEX instruction (Mode 0, Mode 1, Mode
2, mode switching instruction to ModeX) Next, other ring bus instructions such as a mode switching instruction will be described. FIG. 21 shows the MODE0 instruction and M
It is a figure which shows the packet format of an ODE1 command.
22 is a diagram showing the packet format of the MODE2 instruction, and FIG. 23 is a diagram showing the packet format of the MODE3 instruction. When these mode switching instructions are executed, all the nodes connected to the ring bus or the designated nodes are switched to the designated mode.

In the packet formats (104, 105, 106) of these mode switching commands, as shown in FIGS. 21, 22, and 23, the command fields (104a, 105a, 1) in the command packet are used.
06a) designates the type of operation mode to be switched, and the destination field (104d, 10
5d, 106d) designates the node for switching the operation mode. Also, the source field (104c,
105c, 106c), the node I that issued the instruction
Specify D.

When these mode switching command packets are sent out on the ring bus, the current mode at the designated corresponding node is the ring bus interface unit control / status register (RCS).
R) Mode 0 of the 0th bit to the 3rd bit in R, 43,
Since the flag bits of Mode1, Mode2, and ModeX are reflected, these flag bits are switched according to the contents of the mode switching instruction packet. When switching from the operation mode of Mode 2 to another operation mode, since the operation mode cannot be switched by these mode switching instructions, the INTH instruction (hardware interrupt instruction) is used. That is, Mode 2 does not accept any link bus instruction other than the INTH instruction.

SETNID Command (Node ID Setting Command) FIG. 24 is a diagram showing a packet format of the SETNID command. In FIG. 24, 107 is SETNID
Command packet format, 107a is command field, 107b is set node ID field (nid),
107c is a source field (src), 107d is a destination field (BROADCAST)
It is.

In the multiprocessor system having the link bus structure, immediately after reset, the node ID is not given to the processor element of each slave node, and the ring bus interface unit control / status register (RCSR) 43 is used.
The NID flag bit of the eleventh bit is "0". In this case, the master node executes the SETNID command to set the node ID of one slave node per command. The integer arithmetic unit (IAU) 23 of the master node executes the SETNID command,
Setting node I as an operand, setting node I
Set in the D field (nid) 107b and set the SE
Execute the TNID instruction.

The node ID set in the slave node is
Since the SETNID command is transmitted after being put in the set node field (nid) 107b of the packet format 107, the slave node receiving the SETNID command receives the ring bus interface unit control / status register (RCSR) 4 of the node.
Check the NID flag bit of the 11th bit of No. 3, NID
If the flag bit is "0", the value of the setting node field (nid) 107b of the SETNID instruction is written in the node ID register (NIDR) 44, and then the NID flag bit is set to "1" to set the SETN.
The ID command is not output to the subsequent nodes. Also, already NI
If the D flag bit is "1", nothing is done to the SETNID instruction and the SETNID instruction is sent to the next node as it is.

RESNID command (node ID reset command
Decree) Figure 25 is a diagram showing a packet format of RESNID instructions. In FIG. 25, 108 is SETNID
Command packet format, 108a is command field, 108c is source field (src), 108d
Is a destination field (dest). The RESNID instruction is used to reset the node ID of the corresponding node in the multiprocessor system having the ring bus. The node which has received the ring bus instruction and has the matched address condition is the Nth bit of the 11th bit of the ring bus interface unit control / status register (RCSR) 43 of the node.
Reset the ID flag bit. That is, the NID flag bit is set to "0". As a result, in this slave node, a new node ID can be set by the above-mentioned SETNID command.

SETGID command (group ID setting command
Decree) Figure 26 is a diagram showing a packet format of SETGID instructions. In FIG. 26, 109 is SETGID
Command packet format, 109a is command field, 109b is setting group node ID field (g
id), 109c is the source field (src), 10c
9d is a destination field (dest).

In the multiprocessor system having the link bus structure, since a plurality of slave nodes (processor elements) to be processed are designated at the same time, the system architecture that can set the group ID in addition to the node ID is adopted. are doing. The group ID for this purpose is set using the SETGID command. In the slave node, when the SETGID command as shown in FIG. 26 is received, the node whose node address condition matches according to the node ID specified by the destination field (dest) 109d is the set group node ID field of the SETGID command 109. The content of (gid) 109b is set in the group ID register (GIDR) 45.

STAT Command (Status Command) FIG. 27 is a diagram showing a packet format of the STAT command. In FIG. 27, 110 is the packet format of the STAT command, 110 a is the command field, and 11
0b is a status bit field (st), 110c is a source field (src), and 110d is a destination field (dest). This STAT instruction is the status bit at the designated node and the ST
This is a ring bus instruction that performs an AND logical operation or an OR logical operation with the status bit of the status bit field (st) 110b of the AT instruction to check the status bit in each node.

When issuing a STAT command, the master node or the active node issues a status bit field (s) of the packet format 110 of this STAT command.
t) As an initial value of 110b, the AND bit for AND logical operation is set to "1", and OR for OR logical operation is set.
The STAT command is sent with the bit set to "0". In the slave node or the passive node that receives this STAT command from the ring bus, the node whose address condition matches the node ID of the destination field (dest) 110d is the AND bit of the status bit field (st) 110b and the node concerned. The logical AND operation with the AND flag bit of the 7th bit of the ring bus interface unit control / status register (RCSR) 43 of FIG. Also, the logical OR operation of the OR bit of the status bit field (st) 110b and the OR flag bit of the 8th bit of the ring bus interface unit control / status register (RCSR) 43 of the node is executed.
Then, the calculation result is put into the status bit field (st) 110b again, and the STAT instruction is sent to the next node. Even if the STAT command is received, the node whose address condition does not match does nothing and sends the STAT command as it is to the next node.

The master node or the active node which issued the STAT command sets the status bit field (st) 110b of the returned STAT command to the ring bus interface unit control / control of the node.
A of 7th bit of status register (RCSR) 43
The state of the corresponding node is obtained by reflecting it in the ND flag bit and the 8th OR flag bit. In this case, the STAT instruction for inspecting the state of each node is sent to the ring bus by executing the STAT instruction once from the integer arithmetic unit (IAU) 23 and then ending the STAT instruction. The STAT instruction is issued every cycle until the BNOP instruction is executed.

TESTS instruction / TESTR instruction (Test
& Set / Test & Reset command) FIG. 28 is a diagram showing a packet format of a TESTS command. In FIG. 28, 111 is a TESTS command packet format, 111a is a command field,
111b is a mask bit field (mask), 11
Reference numeral 1c indicates a source field (src), and 111d indicates a destination field (dest). 29 is a diagram showing a packet format of the TESTR instruction, and in FIG. 29, 112 shows a packet format of the TESTR instruction, and 112
a is an instruction field, 112b is a mask bit field (mask), 112c is a source field (sr
c) and 112d are destination fields (d
est) are each shown.

When the master node or the active node issues the TESTS command or the TESTR command, the initial value of the mask bit field 111b of the packet format 111 of the TESTS command or the mask bit field 112b of the packet format 112 of the TESTS command is an integer operation. Unit (IAU) 23
Is given as an operand when executing an instruction, and TES
The value of the node ID of the target node is set in the destination field 111d of the TS instruction or the destination field 112d of the TESTR instruction. These values are stored in the internal data bus 22, output FIFO.
It is output through the memory 32 or the like, and the TESTS instruction or TE is output from the ring bus interface unit 21.
It is output as a STR command.

These TESTS instructions or TESTRs
Upon receiving the instruction packet of the instruction, the slave node (or the passive node) having the address condition of the node ID matched performs the following operation. That is, in the case of the TESTS instruction, only for the bit for which the input mask bit field 111b is "1", the corresponding bit of the Test & Set flag register (TSFR) 46 is put in the corresponding bit of the mask bit field 111b, and at the same time. , The bit of the Test & Set flag register (TSFR) 46 is set to "1". Further, in the case of the TESTR instruction, only for the bit for which the input mask bit field 112b is "1", the corresponding bit of the Test & Set flag register (TSFR) 46 is put into the corresponding bit of the mask bit field 111b, and at the same time. , And the bit of the Test & Set flag register (TSFR) 46 is set to “0”. As a result, the state of the corresponding bit of the Test & Set flag register (TSFR) 46 can be inspected, and the flag can be set / reset according to its contents.

INTH instruction (hardware interrupt command
Decree) Figure 30 is a diagram showing a packet format of INTH instructions. In FIG. 30, 113 is the packet format of the INTH instruction, 113a is the instruction field, 11
3b is a vector field (vector), 113c
Indicates a source field (src), and 113d indicates a destination field (BROADCAST). The INTH instruction can be issued by all nodes. This INTH instruction is used for the following two purposes.

One of the purposes is the mode switching from the Mode 2 operation mode to the Mode 0 operation mode.
In the operation mode of Mode2, ring bus instructions other than the INTH instruction are invalidated, and all ring bus data input 2
Input from 8 is considered data. Therefore, by using the ring bus interrupt input in the external input / output control signal group 36 in the ring bus data input direction which is a special signal,
Transfers the input timing of the INTH command and
This is distinguished from the normal data transfer in the operation mode of No. 2, whereby the mode switching from the operation mode of Mode2 to the operation mode of Mode0 is performed.

Another purpose of the INTH instruction is to inform the master node and other slave nodes of the state of occurrence of an exception such as an operation exception that has occurred in the slave node. The interrupt generation factor is I as vector data.
It is set and transmitted in the vector field (vector) 113b of the packet format 113 of the NTH command. In this case, the INTH instruction has priority over other ring bus instructions and is not synchronized with the packet of other transfer data being executed. The interrupt generation factor is I
Vector field (vector) of NTH command 11
Since it is transmitted by being put in 3b, the node that accepts the interrupt performs processing according to the interrupt generation factor.

INTS instruction (software interrupt command
Decree) Figure 31 is a diagram showing a packet format of INTS instructions. In FIG. 31, 114 is a packet format of the INTS command, 114a is a command field, and 11a.
4b is a vector field (vector), 114c
Indicates a source field (src), and 114d indicates a destination field (dest).

The INTS instruction is used as an interrupt process for the master node or the active node to notify the slave node or the hash node of the occurrence of an event by a software-like procedure (processing program). The type of this event is transmitted as vector data indicating an interrupt generation factor by being put in the vector field (vector) 114b of the INTS instruction.

BNOP instruction (bus no operation command
Decree) Figure 32 is a diagram showing a packet format of BNOP instructions. In FIG. 32, 115 is the packet format of the BNOP command, 115a is the command field, and 11
Reference numeral 5c indicates a source field (src), and 115d indicates a destination field (dest). The BNOP instruction is used by the master node or the active node to release the token and terminate the STAT instruction in the operation mode of Mode 1.

Next, regarding the initial operation of the system, FIG.
This will be described with reference to FIG. The host computer 16 downloads the program and data to the local memory 18 in the master node 11 via the bus switch 15 and the interface circuit 19. During this period, the processor element 17 of the master node 11 and the processor elements 12a to 13a of the slave nodes 12 to 13
Are reset by a common reset signal.

When the program and initial data have been downloaded from the host computer 16 to the local memory 18 of the master node 11, the reset signal for the processor elements (17, 12a, 13a) is released. At this time, at the same time when the reset is released, the processor element 17 of the master node 11 fetches an instruction from the local memory 18 and starts executing the program. The processor elements 12a and 13a of the slave nodes 12 and 13 do not fetch an instruction and execute a program even if the reset signal is released. This is because the local memories 12b and 13b of the slave nodes 12 and 13 have not been initialized.

The processor elements 12a and 13a of the slave nodes 12 and 13 enter a standby state in which they do not fetch, decode or execute instructions. In this state, as shown in FIG. 2, the integer arithmetic unit (IAU) 23, the floating point arithmetic unit (FAU) 24, and the instruction cache unit (ICU) 25, which are the constituent elements of the processor element, do nothing but the ring bus interface. The unit (RBIU) 21 and the memory interface unit (MIU) 26 are operable. That is, the instruction given via the ring bus can be executed, and only the ring bus instruction is executed.

Therefore, in this state, the processor element 17 of the master node 11 has the processor elements 12a and 13a of the slave nodes 12 and 13, respectively.
In order to activate, the following three procedures are processed. 1) First, the SETNID command is used to set the node IDs of all slave nodes. 2) Next, the slave node is specified by the set node ID, and the group IDs of all the slave nodes are set by using the SETGID command. 3) Next, use the SENDA instruction to download the program and initial data to the local memory of all slave nodes. If the program and the initial data are the same for all slave nodes, the SENDA command is sent by all node designation (broadcast). In other cases, the previously set node I
The slave node is specified using D or the group ID, and the SENDA command is transmitted by unicast designation or multicast designation.

As described above, the processor elements of the master node and the processor elements of the slave nodes have almost the same processing function, but they are almost the same, and the two processor elements are designed and designed as the same VLSI. It can be manufactured. As a result, the cost can be reduced when constructing a multiprocessor system including a plurality of nodes.

Therefore, one processor element is
The processor element of the master node and the processor element of the slave node have two processing functions. Which element each processor element operates as is determined by the set value of the MN flag bit, and therefore is determined by the MN signal of the external input signal. That is, if the MN signal is at the power supply level, it functions as a processor element of the master node, and if it is at the ground level, it functions as a processor element of the slave node.

[0132]

As described above, according to the multiprocessor system of the present invention, when a multiprocessor system having a ring bus type communication network and performing data communication in a master / slave system is configured,
A node ID setting register for each node and a node I
By providing a D setting bit and a series of processing units for a node ID setting instruction, setting a node ID for each node of a multiprocessor system efficiently without requiring a dedicated arithmetic circuit or signal line. Method becomes possible.

Further, the processor element of the node, which is an element constituting the multiprocessor system, temporarily stores data in the node and a header section generating circuit which generates a header section of a bus communication command (ring bus command) of a packet format. An output buffer for storing, a multiplexer for inputting the three inputs of the ring bus data input, the output of the header section generation circuit, and the output of the data output buffer, and selecting one, and delaying the output of the multiplexer by one clock to the next node By providing a latch circuit for output,
When transferring ring bus instructions or data on the ring bus, data can be propagated per node synchronously in one clock cycle, and a faster data transfer without bottleneck in data transfer. Communication is now possible.

Further, the multiprocessor system of the present invention is provided with a dedicated interrupt signal line propagated through each processor, so that an interrupt having a higher priority than a normal communication is sent to the processor of another node. I try to tell you. As a result, it is possible to efficiently deal with an abnormal situation in the system.

Further, in the processor element of the node,
Pointer groups for setting pointers to descriptor blocks related to data transfer, and means for updating the pointers set in these pointer registers each time data transfer is processed are provided, and descriptor blocks related to data transfer are By providing the pointer to the next descriptor block, the pointer to the memory block in which the transmission / reception data is stored, and the field for storing the data length, it is possible to transfer data at high speed and efficiently.

Further, the elements (processor elements) constituting the multiprocessor system of the present invention are constituted by the semiconductor integrated circuit device, and the semiconductor integrated circuit device is operated by discriminating between the master processor and the slave processor by an external input signal. Configure to allow. in this case,
After the slave processor enters the standby mode after the reset is released and the local memory is initialized by the data such as the program sent from the master processor, it is configured to be restarted by the interrupt. It becomes possible to commonly perform the design using the VLSI manufacturing technology of the processors, which in turn improves the economic efficiency in the design of the multiprocessor system.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a multiprocessor system that implements the present invention in one aspect;

FIG. 2 is a block diagram showing an internal configuration of a processor element,

FIG. 3 is a diagram showing types of data held in a register of each unit of a processor element;

FIG. 4 is a block diagram showing an internal circuit configuration of a ring bus interface unit,

FIG. 5 is a diagram showing a bit configuration of a ring bus interface unit control / status register (RCSR);

FIG. 6 is a diagram showing a packet format of a SEND instruction,

FIG. 7 is a diagram for explaining a data structure for reading data used when executing a SEND instruction;

FIG. 8 is an iming chart for explaining a data transfer timing of data transmission by a SEND instruction,

FIG. 9 is a diagram illustrating a data structure for storing data used when a SEND instruction is executed;

FIG. 10 is a timing chart for explaining the data acquisition timing of the data reception processing by the SEND command,

FIG. 11 is a diagram showing a packet format of a SENDA instruction,

FIG. 12 is a diagram showing a data structure for memory access used when executing a SENDA instruction;

FIG. 13 is a timing chart explaining data transfer timing of data transmission by a SENDA instruction,

FIG. 14 is a timing chart showing internal data transfer timing in a receiving node according to a SENDA instruction,

FIG. 15 is a diagram showing a packet format of an RTRV command,

FIG. 16 is a timing chart for explaining the data transfer timing of data transmission by the RTRV instruction,

FIG. 17 is a timing chart showing the timing of data writing in the node that has received the transfer data according to the RTRV instruction.

FIG. 18 is a diagram showing a packet format of an RTRVA command,

FIG. 19 is a timing chart for explaining the data transfer timing of the data transmission by the RTRVA instruction,

FIG. 20 is a timing chart showing the timing of data writing in the node that has received the transfer data according to the RTRVA instruction.

FIG. 21 shows a MODE0 instruction and a MODE1 instruction.
Diagram showing packet format of instruction,

FIG. 22 is a diagram showing a packet format of a MODE2 instruction,

FIG. 23 is a diagram showing a packet format of a MODE3 instruction,

FIG. 24 is a diagram showing a packet format of a SETNID command,

FIG. 25 is a diagram showing a packet format of a RESNID command;

FIG. 26 is a diagram showing a packet format of a SETGID command,

FIG. 27 is a diagram showing a packet format of a STAT command,

FIG. 28 is a diagram showing a packet format of a TESTS command,

FIG. 29 is a diagram showing a packet format of a TESTR instruction,

FIG. 30 is a diagram showing a packet format of an INTH command,

FIG. 31 is a diagram showing a packet format of an INTS command,

FIG. 32 is a diagram showing a packet format of a BNOP instruction.

[Explanation of symbols]

10 ... Ring bus, 11 ... Master node, 12 ... First
Th slave node, 13 ... Nth slave node, 14 ... Host interface bus, 15 ... Bus exchanger, 16 ... Host computer, 17 ... Processor element, 18 ... Local memory, 19 ... Interface circuit, 20 ... Peripheral circuit , 21 ... Ring bus interface unit (RBIU), 22 ... Internal data bus, 23 ... Integer arithmetic unit (IAU), 24 ... Floating point arithmetic unit (FAU), 25 ... Instruction cache unit (ICU), 26 ... Memory interface unit (MIU), 27 ... Ring bus interface unit control circuit, 28 ... Ring bus data input signal line, 29 ... Multiplexer, 30 ... Latch circuit, 31 ...
Ring bus data output signal line, 32 ... Output FIFO memory, 33 ... Input FIFO memory, 35 ... Comparator, 36
... External input / output control signal group for ring bus data input direction,
37 ... External input / output control signal group in ring bus data output direction, 38 ... Header section generating circuit, 39 ... Control signal group input from other unit, 40 ... Control signal group output to other unit, 41 ... Internal control signal group, 42 ... Register file, 43 ... Ring bus interface unit control / status register (RCSR), 44 ... Node ID register (NIDR), 45 ... Group ID register (GIDR), 47 ... Ring bus instruction pointer (CMDP) ), 48 ... SEND instruction pointer (SEND
RP), 100 ... Packet format of SEND instruction, 100a ... Instruction field, 100b ... Data length field, 100c ... Source field, 100d ... Destination field, 100e ... Dummy packet, 100f ... Data packet, 101 ... SENDA
Command packet format, 101a ... Command field, 101b ... Data length field, 101c ... Source field, 101d ... Destination field, 101e ... Address field, 101f ... Dummy packet, 101g ... Data packet, 102 ... RTR
V command packet format, 102a ... Command field, 102b ... Data length field, 102c ... Source field, 102d ... Destination field, 102e ... Dummy packet, 102f ... Data packet, 103 ... RTRVA command packet format, 103a ... Command field , 103b ... Data length field, 103c ... Source field, 103d ... Destination field, 103e ... Address field, 103f ... Dummy packet, 103g ... Data packet, 107 ... SETNID command packet format, 107a ... Command field, 107b ... Setting node ID field, 107c ... Source field,
107d ... Destination field, 108 ...
Packet format of SETNID command, 108a ...
Command field, 108c ... Source field, 108
d ... Destination field, 109 ... SET
GID command packet format, 109a ... Command field, 109b ... Setting group node ID field, 109c ... Source field, 109d ... Destination field, 110 ... STAT command packet format, 110a ... Command field, 110
b ... Status bit field, 110c ... Source field, 110d ... Destination field, 11
1 ... TESTS command packet format, 111a
Command field, 111b ... mask bit field, 111c ... source field, 111d ... destination field, 112 ... packet format of TESTR command, 112a ... command field, 11
2b ... mask bit field, 112c ... source field, 112d ... destination field,
113 ... packet format of INTH command, 113
a ... instruction field, 113b ... vector field,
113c ... Source field, 113d ... Destination field, 114 ... INTS command packet format, 114a ... Command field, 114b ...
Vector field, 114c ... Source field, 1
14d ... Destination field, 115 ... B
Packet format of NOP command, 115a ... Command field, 115c ... Source field, 115d ... Destination field, 120 ... Descriptor block, 120a ... Descriptor pointer field, 120b ... Memory block pointer field,
120c ... Unused area, 120d ... Data length field, 120e ... Unused area, 120f ... Destination address field, 121 ... Data area, 122 ... Descriptor block, 122a ... Descriptor pointer field, 122b ... Memory block pointer field, 122c ... Unused area, 122d ... Data length field, 122e ... Source address field, 122f
... unused area, 123 ... data area, 124 ... descriptor block, 124a ... descriptor pointer field, 124b ... memory block pointer field, 124c ... unused area, 124d ... data length field, 124e ... unused area, 124f ... destination Address field, 124g ... Address field, 125
… Data area.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Nobuaki Miyagawa 2274 Hongo, Ebina City, Kanagawa Prefecture Fuji Xerox Co., Ltd. (72) Reiji Aihara 1-2-2, Kagamiyama, Higashihiroshima City, Hiroshima Prefecture Hiroshima University (72 ) Inventor Mitsumasa Koyanagi, Aoba-ku, Sendai-shi, Miyagi New winding letter Aoba, Tohoku University

Claims (8)

[Claims] 1. A multiprocessor in which a plurality of nodes having processor elements are connected via a ring bus type communication network, data communication between nodes is performed in a master / slave type, and data processing is performed in the processor elements of each node. In the system, each processor element sets a node ID for setting a node ID provided for each node.
A D register, an ID setting flag register for each node, which stores an ID setting flag indicating whether or not a node ID has been set, a reset means for resetting the ID setting flag when the system is reset, and a master node. Node type setting means for setting a distinction from a slave node; command issuing means for issuing a node ID setting instruction for setting a different node ID when the node type setting means is set as a master node; When the node type setting means is set to the slave node and the ID setting flag is reset, the node I added to the node ID setting command
D is set in the node ID register, the ID setting flag is set, control processing is performed to prevent the node ID setting command from being transmitted to a downstream node, and if the ID setting flag is set, the node A multiprocessor system comprising: a control unit that performs a control process of transmitting an ID setting command to a downstream node. 2. A multiprocessor in which a plurality of nodes having processor elements are connected via a ring bus type communication network, data communication is performed between the nodes in a master / slave type, and data processing is performed in the processor element of each node. In the system, each processor element inputs a command code assigned for interprocessor communication, decodes the content of the control code, and generates a control signal necessary for interprocessor communication, and a packet based on the control signal. Header part generation circuit that assembles the header part of one or more data transferred in a format, output buffer that temporarily stores the data inside the node, data input from the ring bus and output of the header part generation circuit And the data from the output buffer Multiprocessor system characterized in that it comprises a multiplexer for selecting one of them by force, and a latch circuit for outputting to the next node by one clock delay the output of the multiplexer. 3. A multiprocessor in which a plurality of nodes having processor elements are connected via a ring bus type communication network, data communication is performed between the nodes in a master / slave type, and data processing is performed in the processor elements of each node. In the system, a dedicated interrupt signal line propagated through the processor element of each node, and communication by which the processor element of each node transmits an interrupt having a higher priority than normal data communication to another processor element by the interrupt signal line A multiprocessor system comprising: control processing means. 4. A multiprocessor in which a plurality of nodes having processor elements are connected via a ring bus type communication network, data communication is performed between the nodes in a master / slave type, and data processing is performed in the processor element of each node. In the system, a storage unit that stores a descriptor that describes control data related to data transfer between nodes, a pointer register group that sets a pointer to the descriptor, and a pointer register that is set in the pointer register every time data transfer is processed. A multiprocessor system comprising: an updating unit for updating a pointer. 5. The multiprocessor system according to claim 4, wherein the descriptor includes a pointer to a next descriptor, a pointer to a memory block in which transmission / reception data is stored, and a data length. Multiprocessor system. 6. A multiprocessor in which a plurality of nodes having processor elements are connected via a ring bus type communication network, data communication is performed between the nodes in a master / slave type, and data processing is performed in the processor element of each node. In the system, each processor element functions as a processor element of a master node or a slave node when an external input signal is given to the node type setting means. 7. The multiprocessor system according to claim 6, wherein the processor element functioning as a slave node enters a standby mode after reset release, and is restarted by an interrupt signal transmitted from the processor element of the master node. A multiprocessor system characterized by the following. 8. The multiprocessor system according to claim 7, wherein the processor element functioning as a slave node stores a program or data transmitted via the ring bus in a local memory in a standby mode after reset release. A multiprocessor system characterized by: