JPH0990396A - Liquid crystal display device and control ic therefor - Google Patents
Liquid crystal display device and control ic thereforInfo
- Publication number
- JPH0990396A JPH0990396A JP7249319A JP24931995A JPH0990396A JP H0990396 A JPH0990396 A JP H0990396A JP 7249319 A JP7249319 A JP 7249319A JP 24931995 A JP24931995 A JP 24931995A JP H0990396 A JPH0990396 A JP H0990396A
- Authority
- JP
- Japan
- Prior art keywords
- control
- signal
- signal line
- drive circuit
- line drive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/361—Assembling flexible printed circuits with other printed circuits
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、液晶表示装置およ
びこれに使用されるコントロールＩＣに関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a control IC used therein.
【０００２】[0002]
【従来の技術】アクティブマトリクス型液晶表示装置１
００は、図６に示すように表示パネル１１０を駆動させ
るために、信号線駆動回路１１２と走査線駆動回路１２
２とが設けられ、この信号線駆動回路１１２と走査線駆
動回路１２２を制御するためのコントロールＩＣ（タイ
ミングコントローラ）１１６が設けられている。2. Description of the Related Art Active matrix type liquid crystal display device 1
00 is a signal line driving circuit 112 and a scanning line driving circuit 12 for driving the display panel 110 as shown in FIG.
2 is provided, and a control IC (timing controller) 116 for controlling the signal line driving circuit 112 and the scanning line driving circuit 122 is provided.
【０００３】そして、パソコン等の本体からこのコント
ロールＩＣ１１６へ外部入力信号が入力し、コントロー
ルＩＣ１１６から信号線駆動回路１１２及び走査線駆動
回路１２２に映像信号及び制御信号が送られ表示パネル
１１０を駆動する。An external input signal is input to the control IC 116 from the body of a personal computer or the like, and a video signal and a control signal are sent from the control IC 116 to the signal line driving circuit 112 and the scanning line driving circuit 122 to drive the display panel 110. .
【０００４】また、コントロールＩＣ１１６，走査線駆
動回路１２２，信号線駆動回路１１２には、電源回路１
１４から電源が供給されている。The control IC 116, the scanning line drive circuit 122, and the signal line drive circuit 112 include the power supply circuit 1
Power is supplied from 14.
【０００５】図７及び図８は、表示パネル１１０の上側
及び下側にそれぞれ信号線駆動回路１１８，１２０を取
付けた、いわゆる両側駆動法における配置例を示したも
のである。FIGS. 7 and 8 show an arrangement example in a so-called double-sided drive method in which signal line drive circuits 118 and 120 are attached to the upper side and the lower side of the display panel 110, respectively.
【０００６】外部より入力された映像信号及び制御信号
は、コントロールＩＣ１１６内で、上側の信号線駆動回
路１１８と、下側の信号線駆動回路１２０への信号及び
走査線駆動回路１２２への信号に変換されて各回路に転
送される。Video signals and control signals input from the outside are converted into signals for the upper signal line drive circuit 118, the lower signal line drive circuit 120, and the scanning line drive circuit 122 in the control IC 116. It is converted and transferred to each circuit.
【０００７】表示パネル１１０と、上下の信号線駆動回
路基板１２４，１２６とは、信号線駆動ＩＣを有するＴ
ＣＰ（TAPE CARRIER PACKAGE）１２８を介して接続され
ている。なお、信号線駆動回路とは、信号線駆動回路基
板上の配線、ＴＣＰ上の配線及びＴＣＰ上にある信号線
駆動ＩＣによって構成された回路の総称である。同様
に、走査線駆動回路とは、走査線駆動回路基板上の配
線、ＴＣＰ上の配線及びＴＣＰ上にある走査線駆動ＩＣ
によって構成された回路の総称である。The display panel 110 and the upper and lower signal line drive circuit boards 124 and 126 have a T having a signal line drive IC.
It is connected through a CP (TAPE CARRIER PACKAGE) 128. Note that the signal line driver circuit is a generic term for a circuit including a wiring over the signal line driver circuit board, a wiring over TCP, and a signal line driver IC over TCP. Similarly, the scanning line driving circuit means the wiring on the scanning line driving circuit board, the wiring on the TCP, and the scanning line driving IC on the TCP.
Is a general term for circuits configured by.
【０００８】この両側駆動法では、図７に示すように、
表示パネル１１０における奇数番号の信号線１，３，
５，……は、上側のＴＣＰ１２８で駆動され、偶数番号
の信号線２，４，６，……は下側のＴＣＰ１２８で駆動
される。In this double-sided driving method, as shown in FIG.
Odd-numbered signal lines 1, 3, on the display panel 110
.. are driven by the upper TCP 128, and the even-numbered signal lines 2, 4, 6, ... Are driven by the lower TCP 128.
【０００９】この場合に、図８（ａ）に示すように、コ
ントロールＩＣ１１６は、コントロール回路基板１３０
の長手方向の中心に配置されている。In this case, as shown in FIG. 8A, the control IC 116 is connected to the control circuit board 130.
Is arranged at the center in the longitudinal direction.
【００１０】そして、コントロールＩＣ１１６から上下
の信号線駆動回路１１８，１２０への信号を出力するた
めの複数の出力ピンは、図８（ｂ）に示すように、平面
矩形のコントロールＩＣ１１６の上下の対向する２辺に
配列されている。すなわち、コントロールＩＣ１１６の
上辺には、上側の信号線駆動回路１１８へ出力するため
の出力ピン１１６ａが配列され、その下辺には、下側の
信号線駆動回路１２０へ出力するための出力ピン１１６
ｂが配列されている。また、その右辺には、走査線駆動
回路１２２への出力ピン１１６ｃが配列されている。A plurality of output pins for outputting signals from the control IC 116 to the upper and lower signal line drive circuits 118 and 120 are provided on the upper and lower sides of the planar rectangular control IC 116 as shown in FIG. 8B. It is arranged on two sides. That is, the output pins 116 a for outputting to the upper signal line drive circuit 118 are arranged on the upper side of the control IC 116, and the output pins 116 for outputting to the lower signal line drive circuit 120 are arranged on the lower side thereof.
b are arranged. Further, an output pin 116c to the scanning line drive circuit 122 is arranged on the right side thereof.
【００１１】このような出力ピン１１６ａ，ｂ，ｃの配
列により、信号線駆動回路１１８，１２０及び走査線駆
動回路１２２へ最短で配線を行うことができる。With the arrangement of the output pins 116a, 116b, 116c as described above, wiring can be performed to the signal line driving circuits 118, 120 and the scanning line driving circuit 122 in the shortest time.
【００１２】[0012]
【発明が解決しようとする課題】ところで、最近では、
表示パネル１１０の周辺の駆動回路やバックライトを小
型化する要求が強く、従来のように信号線駆動回路を表
示パネル１１０の上下両側に設けることが困難となり、
図５に示すように、信号線駆動回路１３０を表示パネル
１１０の上下どちらか片側に配置させる片側駆動法が採
られるようになった。By the way, recently,
There is a strong demand for miniaturizing the drive circuit and the backlight around the display panel 110, and it becomes difficult to provide the signal line drive circuits on the upper and lower sides of the display panel 110 as in the conventional case.
As shown in FIG. 5, the one-side driving method has been adopted in which the signal line driving circuit 130 is arranged on one side of the display panel 110 either above or below.
【００１３】一方、表示パネル１１０は、大型，高精細
化しているために、駆動周波数が高くなってきており、
従来のように信号線を表示パネル１１０の上下両側から
駆動する方法では、表示パネル１１０の大型化に従って
コントロールＩＣ１１６と信号線駆動回路の配線が長く
なって配線容量が増え、信号波形の劣化及び消費電力の
増大を導くという問題があった。On the other hand, since the display panel 110 has a large size and high definition, the driving frequency is increasing,
In the conventional method of driving the signal lines from both the upper and lower sides of the display panel 110, the wiring of the control IC 116 and the signal line driving circuit becomes longer as the display panel 110 becomes larger, and the wiring capacity increases, which deteriorates and consumes the signal waveform. There was a problem of leading to an increase in electric power.
【００１４】そこで、本発明は上記問題点に鑑み、片側
駆動法でも、比較的周波数の高い信号を扱う信号線駆動
回路基板への信号を優先させて短く配線できるコントロ
ールＩＣ及び液晶表示装置を提供するものである。Therefore, in view of the above problems, the present invention provides a control IC and a liquid crystal display device in which a signal to a signal line drive circuit board that handles a signal having a relatively high frequency can be prioritized and shortened even in the one-sided drive method. To do.
【００１５】[0015]
【課題を解決するための手段】第１の発明の液晶表示装
置のコントロールＩＣは、矩形の表示パネルの一側部に
のみ信号線駆動回路の基板を配し、前記一側部に隣接す
る隣接側部に走査線駆動回路の基板を配した液晶表示装
置に用いられ、外部から入力する信号のための複数の入
力ピンと、前記信号線駆動回路及び前記走査線駆動回路
に信号を出力する複数の出力ピンを有する平面矩形のコ
ントロールＩＣであって、前記ＩＣの隣接する二辺に、
前記信号線駆動回路への出力ピン群がそれぞれ設けられ
たものである。In a control IC of a liquid crystal display device according to a first aspect of the present invention, a substrate of a signal line drive circuit is arranged only on one side of a rectangular display panel, and adjacent to the one side. It is used in a liquid crystal display device in which a substrate of a scanning line driving circuit is arranged on a side part, and a plurality of input pins for a signal input from the outside, and a plurality of outputting a signal to the signal line driving circuit and the scanning line driving circuit. A planar rectangular control IC having an output pin, the two adjacent sides of the IC being
Output pin groups to the signal line drive circuit are provided respectively.
【００１６】第２の発明の液晶表示装置は、矩形の表示
パネルの一側部にのみ信号線駆動回路基板を配し、前記
一側部に隣接する隣接側部に走査線駆動回路基板を配し
た液晶表示装置において、前記信号線駆動回路基板、ま
たは、前記走査線駆動回路基板における前記信号線駆動
回路基板と前記走査線駆動回路基板との交差部近傍にコ
ントロールＩＣを設けたものである。In the liquid crystal display device of the second invention, the signal line drive circuit board is arranged only on one side of the rectangular display panel, and the scanning line drive circuit board is arranged on the adjacent side adjacent to the one side. In the above liquid crystal display device, a control IC is provided near the signal line drive circuit board or an intersection of the scanning line drive circuit board and the signal line drive circuit board.
【００１７】以上により、コントロールＩＣと信号線駆
動回路の間の配線を短くすることができ、配線容量の低
減が可能であり消費電力もそれに伴って低くなる。配線
が短くなって配線領域が狭くなると、回路基板の実装領
域を有効に活用でき、基板サイズをも小型化することが
できる。As described above, the wiring between the control IC and the signal line driving circuit can be shortened, the wiring capacitance can be reduced, and the power consumption can be reduced accordingly. When the wiring becomes shorter and the wiring area becomes narrower, the mounting area of the circuit board can be effectively utilized and the board size can be reduced.
【００１８】さらに、各基板へ転送する信号をそれぞれ
まとめて配置したコントロールＩＣの入出力ピンの構成
を行うことにより、不要なＢＶＨ、スルーホールを減ら
しＥＭＩを低減させることができる。Further, by configuring the input / output pins of the control IC in which the signals to be transferred to each substrate are collectively arranged, unnecessary BVH and through holes can be reduced and EMI can be reduced.
【００１９】[0019]
【発明の実施の形態】以下、本発明の実施形態である第
１の実施例を図１，３，４に基づいて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment, which is an embodiment of the present invention, will be described below with reference to FIGS.
【００２０】本実施例は、図５で説明した片側駆動法を
用いた液晶表示装置１０である。The present embodiment is a liquid crystal display device 10 using the one-sided driving method described with reference to FIG.
【００２１】液晶表示装置１０は、図１（ａ）に示すよ
うに表示パネル１２の上辺には、信号線駆動回路１４の
配線部分を有する信号線駆動回路基板１６が配置され、
信号線回路駆動基板１６と表示パネル１２とは、信号線
駆動ＩＣを有する８個のＴＣＰ１８で接続されている。In the liquid crystal display device 10, as shown in FIG. 1A, a signal line driving circuit board 16 having a wiring portion of the signal line driving circuit 14 is arranged on the upper side of the display panel 12.
The signal line circuit drive substrate 16 and the display panel 12 are connected by eight TCPs 18 each having a signal line drive IC.
【００２２】また、表示パネル１２の左辺には、走査線
駆動回路２０の配線部分を有する走査線駆動回路基板２
２が配置され、走査線駆動回路基板２２と表示パネル１
２とは、走査線駆動ＩＣを有する４個のＴＣＰ２４で接
続されている。On the left side of the display panel 12, the scanning line driving circuit board 2 having the wiring portion of the scanning line driving circuit 20 is provided.
2 are arranged, the scanning line drive circuit board 22 and the display panel 1
2 are connected by four TCPs 24 having a scanning line driving IC.
【００２３】そして、信号線駆動回路基板１６の左部、
すなわち、走査線駆動回路基板２２との交差部近傍にコ
ントロールＩＣ２６が配置されている。Then, the left part of the signal line drive circuit board 16,
That is, the control IC 26 is arranged near the intersection with the scanning line drive circuit board 22.
【００２４】このコントロールＩＣ２６は、図１（ｂ）
に示すように、信号線駆動回路１４へ出力する信号を送
る出力ピン群２６ａが、コントロールＩＣ２６の下辺と
左右両辺の下部に配列されている。この出力ピン群２６
ａからは、クロック信号、水平スタート信号、映像信号
（８ビット×３（Ｒ，Ｇ，Ｂ））、ＴＣＰ制御信号及び
電源信号が信号線駆動回路１４へ出力される。This control IC 26 is shown in FIG.
As shown in, the output pin group 26a for sending a signal to be output to the signal line drive circuit 14 is arranged on the lower side of the control IC 26 and the lower side of both left and right sides. This output pin group 26
From a, a clock signal, a horizontal start signal, a video signal (8 bits × 3 (R, G, B)), a TCP control signal and a power supply signal are output to the signal line drive circuit 14.
【００２５】パソコン本体からの入力信号を受ける入力
ピン群２６ｂは、コントロールＩＣ１６の上辺の右側及
び右辺の上側に配列されている。この入力ピン群２６ｂ
には、パソコン本体から水平同期信号、垂直同期信号、
クロック信号及び映像信号（８ビット×３（Ｒ，Ｇ，
Ｂ））が入力される。The input pin group 26b for receiving an input signal from the personal computer body is arranged on the right side of the upper side of the control IC 16 and the upper side of the right side. This input pin group 26b
The horizontal sync signal, vertical sync signal,
Clock signal and video signal (8 bits x 3 (R, G,
B)) is input.
【００２６】走査線駆動回路２２へ出力する信号のため
の出力ピン群２６ｃがコントロールＩＣ２６の上辺の左
側及び左辺の上側に配列されている。この出力ピン群２
６ｃからは、クロック信号、垂直スタート信号、出力制
御信号及び電源信号が走査線駆動回路２０へ出力され
る。Output pin groups 26c for signals output to the scanning line drive circuit 22 are arranged on the left side of the upper side of the control IC 26 and the upper side of the left side thereof. This output pin group 2
A clock signal, a vertical start signal, an output control signal, and a power supply signal are output from 6c to the scanning line drive circuit 20.
【００２７】このように出力ピン群２６ａ，ｂ，ｃを配
列して、そのコントロールＩＣ２６を信号線駆動回路基
板１４の左部に配置することにより、信号線駆動回路１
４への配線を最も短くすることができる。すなわち、信
号線駆動回路１４への出力信号が比較的周波数の高い信
号を取扱っているため、この配線を最も考慮する必要が
あるからである。そして、その点をさらに考慮するため
に、出力ピン群２６ａの配列は、図３に示すように、映
像信号の出力ピン群の中央にクロック信号を出力する出
力ピンが配置されている。すなわち、映像信号は、ＲＧ
Ｂの８ビットのデータであるため、全部で２４本の出力
ピンが設けられている。そのため、クロック信号の出力
ピンをこの映像信号の２４本の出力ピン群の中央、すな
わち、１２本と１２本の間に設けている。By thus arranging the output pin groups 26a, 26b, 26c and arranging the control IC 26 thereof on the left portion of the signal line driving circuit board 14, the signal line driving circuit 1 is formed.
The wiring to 4 can be the shortest. That is, since the output signal to the signal line drive circuit 14 handles a signal having a relatively high frequency, it is necessary to consider this wiring most. In order to further consider this point, the output pin group 26a is arranged such that an output pin for outputting a clock signal is arranged at the center of the output pin group for the video signal, as shown in FIG. That is, the video signal is RG
Since it is B 8-bit data, a total of 24 output pins are provided. Therefore, the output pin of the clock signal is provided at the center of the group of 24 output pins of this video signal, that is, between 12 and 12.
【００２８】図４は、コントロールＩＣあるいは信号線
駆動回路１４が映像信号を取込み、保持するときのタイ
ミングを、映像信号を基準にした波形で示したものであ
る。そして、図４（ｂ）（ｃ）は、セットアップ時間及
びホールド時間が短くなる場合を示しており、回路基板
の配線を行う上で各配線間の長さにばらつきが生じて信
号の立上がり及び立下がりのタイミングにずれが生じて
いる場合を示している。すなわち、クロック信号と映像
信号との間にずれが生じている。FIG. 4 shows the timing when the control IC or the signal line drive circuit 14 takes in and holds the video signal, with a waveform based on the video signal. 4B and 4C show the case where the setup time and the hold time are shortened, and when the wiring of the circuit board is performed, the lengths of the respective wirings are varied and the signal rises and rises. It shows a case in which there is a deviation in the falling timing. That is, there is a deviation between the clock signal and the video signal.
【００２９】そこで、図３のようにクロック信号を各映
像信号の中心に配列させることにより、クロック信号と
映像信号のタイミングのずれを平均化し、クロック信号
の配線長さが、２４本の映像信号線の配線長さの平均的
な長さと等しくなるようにしている。そのようにするこ
とで、図４（ａ）に示すように、そのずれが最小限に抑
えられている。Therefore, by arranging the clock signal at the center of each video signal as shown in FIG. 3, the timing deviation between the clock signal and the video signal is averaged, and the wiring length of the clock signal is 24 video signals. The length of the wire is set to be equal to the average length. By doing so, as shown in FIG. 4A, the shift is minimized.
【００３０】図２は、本発明の第２の実施例の液晶表示
装置１０の平面図であり、第１の実施例と異なる点は、
コントロールＩＣ２８を走査線駆動回路基板２２の上
側、すなわち、信号線駆動回路基板１６との交差部近傍
に設けている点にある。FIG. 2 is a plan view of a liquid crystal display device 10 according to the second embodiment of the present invention. The difference from the first embodiment is that
The control IC 28 is provided on the upper side of the scanning line drive circuit board 22, that is, near the intersection with the signal line drive circuit board 16.
【００３１】また、コントロールＩＣ２８は、信号線駆
動回路１４への出力信号のための出力ピン群２８ａが、
図２（ｂ）に示すように、平面矩形のコントロールＩＣ
２８の上辺及び左右両側辺の上部に配列されている点に
ある。In the control IC 28, the output pin group 28a for the output signal to the signal line drive circuit 14 is
As shown in FIG. 2B, a planar rectangular control IC
28 on the upper side and on the left and right sides.
【００３２】このように出力ピン群２８ａを配列するこ
とにより、信号線駆動回路１４までの配線長さを最小に
抑えることができる。By arranging the output pin group 28a in this way, the wiring length up to the signal line drive circuit 14 can be minimized.
【００３３】[0033]
【発明の効果】以上により、本発明のコントロールＩＣ
及び液晶表示装置であると、信号線駆動回路に近い位置
にコントロールＩＣを配置するとともに、その信号線駆
動回路に出力するための出力ピン群の配列を考慮するこ
とにより配線容量の増大による波形の劣化を最小限に抑
え、消費電力を減らすことができる。As described above, the control IC of the present invention
In the case of the liquid crystal display device, the control IC is arranged at a position close to the signal line drive circuit, and the arrangement of the output pin group for outputting to the signal line drive circuit is taken into consideration to improve the waveform due to the increase of the wiring capacitance. It is possible to minimize deterioration and reduce power consumption.
【００３４】また、配線長さを短くすることによって液
晶表示モジュールの外部に放射する電波の周波数成分を
高周波側にシフトさせ、ＥＭＩ問題を改善することがで
きる。Further, by shortening the wiring length, the frequency component of the radio wave radiated to the outside of the liquid crystal display module can be shifted to the high frequency side, and the EMI problem can be improved.
【００３５】さらに、コントロールＩＣのピン配列にお
いては、入力ピン群と出力ピン群をそれぞれ連続配列さ
せ、また、映像信号の入出力ピン群の中央にクロック信
号等の制御信号の入出力ピンを配列させることによって
信号の取込み、保持のタイミングのずれを平均化するこ
とができる。Further, in the pin arrangement of the control IC, the input pin group and the output pin group are arranged continuously, and the input / output pin of the control signal such as the clock signal is arranged in the center of the input / output pin group of the video signal. By doing so, it is possible to average deviations in the timing of signal acquisition and signal retention.
【図１】本発明の第１の一実施例の図面であり、（ａ）
は液晶表示装置の平面図であり、（ｂ）はコントロール
ＩＣの平面図である。FIG. 1 is a drawing of a first embodiment of the present invention, (a)
Is a plan view of the liquid crystal display device, and (b) is a plan view of the control IC.
【図２】本発明の第２の実施例の図面であり、（ａ）は
液晶表示装置の平面図であり、（ｂ）はコントロールＩ
Ｃの平面図である。2A and 2B are drawings of a second embodiment of the present invention, FIG. 2A is a plan view of a liquid crystal display device, and FIG.
It is a top view of C.
【図３】コントロールＩＣと信号線駆動回路１４との間
の接続を示す説明図である。FIG. 3 is an explanatory diagram showing a connection between a control IC and a signal line drive circuit 14.
【図４】映像信号を基準とした取込み、保持のタイミン
グチャートである。FIG. 4 is a timing chart of capturing and holding based on a video signal.
【図５】片側駆動法の信号線接続の説明図である。FIG. 5 is an explanatory diagram of signal line connection of a one-side driving method.
【図６】液晶表示装置の駆動回路のブロック図である。FIG. 6 is a block diagram of a drive circuit of a liquid crystal display device.
【図７】両側駆動法の信号線接続を示した説明図であ
る。FIG. 7 is an explanatory diagram showing a signal line connection of a double-side drive method.
【図８】両側駆動法の図面であり、（ａ）は液晶表示装
置の平面図であり、（ｂ）はコントロールＩＣの平面図
である。8A and 8B are diagrams of a double-sided driving method, FIG. 8A is a plan view of a liquid crystal display device, and FIG. 8B is a plan view of a control IC.
１０ 液晶表示装置 １２ 表示パネル １４ 信号線駆動回路 １６ 信号線駆動回路基板 １８ ＴＣＰ ２０ 走査線駆動回路 ２２ 走査線駆動回路基板 ２４ ＴＣＰ ２６ コントロールＩＣ ２８ コントロールＩＣ 10 liquid crystal display device 12 display panel 14 signal line drive circuit 16 signal line drive circuit board 18 TCP 20 scanning line drive circuit 22 scanning line drive circuit board 24 TCP 26 control IC 28 control IC
Claims (7)
動回路の基板を配し、前記一側部に隣接する隣接側部に
走査線駆動回路の基板を配した液晶表示装置に用いら
れ、外部から入力する信号のための複数の入力ピンと、
前記信号線駆動回路及び前記走査線駆動回路に信号を出
力する複数の出力ピンを有する平面矩形のコントロール
ＩＣであって、 前記ＩＣの隣接する二辺に、前記信号線駆動回路への出
力ピン群がそれぞれ設けられたことを特徴とする液晶表
示装置のコントロールＩＣ。1. A liquid crystal display device in which a substrate of a signal line driving circuit is arranged only on one side of a rectangular display panel and a substrate of a scanning line driving circuit is arranged on an adjacent side adjacent to the one side. And multiple input pins for externally input signals,
A planar rectangular control IC having a plurality of output pins for outputting a signal to the signal line drive circuit and the scanning line drive circuit, wherein output pin groups to the signal line drive circuit are provided on two adjacent sides of the IC. A control IC for a liquid crystal display device, wherein:
記コントロールＩＣの一辺に連続して配列されたことを
特徴とする請求項１記載の液晶表示装置のコントロール
ＩＣ。2. The control IC of a liquid crystal display device according to claim 1, wherein the input pin group and the output pin group are continuously arranged on one side of the control IC.
に映像信号の入力ピン群を設けたことを特徴とする請求
項１記載の液晶表示装置のコントロールＩＣ。3. The control IC of the liquid crystal display device according to claim 1, wherein the control IC is provided with a group of input pins for a video signal on both sides of an input pin for a control signal such as a clock signal from the outside. .
ック信号等の制御信号の出力ピンの両側に映像信号の出
力ピン群を設けたことを特徴とする請求項１記載の液晶
表示装置のコントロールＩＣ。4. The control IC, wherein output signal pin groups are provided on both sides of an output pin for a control signal such as a clock signal to the signal line drive circuit or the scanning line drive circuit. Item 2. A control IC for a liquid crystal display device according to item 1.
動回路基板を配し、前記一側部に隣接する隣接側部に走
査線駆動回路基板を配した液晶表示装置において、 前記信号線駆動回路基板、または、前記走査線駆動回路
基板における前記信号線駆動回路基板と前記走査線駆動
回路基板との交差部近傍にコントロールＩＣを設けたこ
とを特徴とする液晶表示装置。5. A liquid crystal display device in which a signal line drive circuit board is arranged only on one side of a rectangular display panel, and a scanning line drive circuit board is arranged on an adjacent side adjacent to the one side. A liquid crystal display device, wherein a line driving circuit board or a control IC is provided near an intersection of the signal line driving circuit board and the scanning line driving circuit board in the scanning line driving circuit board.
ルＩＣを設けた場合に、 前記ＩＣの信号線駆動回路への複数の出力ピン群を、前
記ＩＣの前記表示パネルに対抗する辺と、この辺に隣接
する隣接辺に配列したことを特徴とする請求項５記載の
液晶表示装置。6. When the control IC is provided on the signal line drive circuit board, a plurality of output pin groups to the signal line drive circuit of the IC and a side of the IC that opposes the display panel and this side are provided. 6. The liquid crystal display device according to claim 5, wherein the liquid crystal display device is arranged on the adjacent side adjacent to.
ルＩＣを設けた場合に、 前記ＩＣの信号線駆動回路への複数の出力ピン群を、前
記信号線駆動回路基板と前記走査線駆動回路基板との交
差部に面する前記ＩＣの一辺と、この一辺に隣接する隣
接辺に配列したことを特徴とする請求項５記載の液晶表
示装置。7. When the control IC is provided on the scanning line drive circuit board, a plurality of output pin groups to the signal line drive circuit of the IC are provided on the signal line drive circuit board and the scanning line drive circuit board. 6. The liquid crystal display device according to claim 5, wherein the liquid crystal display device is arranged on one side of the IC facing an intersection with and on an adjacent side adjacent to the one side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24931995A JP3593392B2 (en) | 1995-09-27 | 1995-09-27 | Liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24931995A JP3593392B2 (en) | 1995-09-27 | 1995-09-27 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0990396A true JPH0990396A (en) | 1997-04-04 |
| JP3593392B2 JP3593392B2 (en) | 2004-11-24 |
Family
ID=17191236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24931995A Expired - Fee Related JP3593392B2 (en) | 1995-09-27 | 1995-09-27 | Liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3593392B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008072084A (en) * | 2006-09-13 | 2008-03-27 | Samsung Electronics Co Ltd | Signal transmitting member and display device having the same |
| JP2008116982A (en) * | 2008-01-04 | 2008-05-22 | Hitachi Displays Ltd | Display device |
| USRE40706E1 (en) | 1998-12-02 | 2009-05-05 | Hitachi, Ltd. | Liquid crystal display device |
| JP2016029775A (en) * | 2014-07-25 | 2016-03-03 | ローム株式会社 | Parallel interface and integrated circuit |
| WO2019050020A1 (en) * | 2017-09-08 | 2019-03-14 | ローム株式会社 | Liquid crystal display device, image display system and vehicle |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5508662B2 (en) | 2007-01-12 | 2014-06-04 | 株式会社半導体エネルギー研究所 | Display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63179395A (en) * | 1987-01-20 | 1988-07-23 | 松下電器産業株式会社 | Integrated circuit apparatus for driving liquid crystal display panel |
| JPS63184781A (en) * | 1986-09-11 | 1988-07-30 | 株式会社東芝 | Liquid crystal display device |
| JPH03276129A (en) * | 1990-03-27 | 1991-12-06 | Toshiba Corp | Liquid crystal display device |
| JPH04362924A (en) * | 1990-09-05 | 1992-12-15 | Seiko Instr Inc | Semiconductor integrated circuit device for flat plate type light valve substrate |
| JPH05313178A (en) * | 1992-05-12 | 1993-11-26 | Sharp Corp | Packaging method and packaging structure for panel |
-
1995
- 1995-09-27 JP JP24931995A patent/JP3593392B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63184781A (en) * | 1986-09-11 | 1988-07-30 | 株式会社東芝 | Liquid crystal display device |
| JPS63179395A (en) * | 1987-01-20 | 1988-07-23 | 松下電器産業株式会社 | Integrated circuit apparatus for driving liquid crystal display panel |
| JPH03276129A (en) * | 1990-03-27 | 1991-12-06 | Toshiba Corp | Liquid crystal display device |
| JPH04362924A (en) * | 1990-09-05 | 1992-12-15 | Seiko Instr Inc | Semiconductor integrated circuit device for flat plate type light valve substrate |
| JPH05313178A (en) * | 1992-05-12 | 1993-11-26 | Sharp Corp | Packaging method and packaging structure for panel |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE40706E1 (en) | 1998-12-02 | 2009-05-05 | Hitachi, Ltd. | Liquid crystal display device |
| JP2008072084A (en) * | 2006-09-13 | 2008-03-27 | Samsung Electronics Co Ltd | Signal transmitting member and display device having the same |
| JP2008116982A (en) * | 2008-01-04 | 2008-05-22 | Hitachi Displays Ltd | Display device |
| JP2016029775A (en) * | 2014-07-25 | 2016-03-03 | ローム株式会社 | Parallel interface and integrated circuit |
| WO2019050020A1 (en) * | 2017-09-08 | 2019-03-14 | ローム株式会社 | Liquid crystal display device, image display system and vehicle |
| CN111095390A (en) * | 2017-09-08 | 2020-05-01 | 罗姆股份有限公司 | Liquid crystal display device, image display system, and vehicle |
| JPWO2019050020A1 (en) * | 2017-09-08 | 2020-10-01 | ローム株式会社 | Liquid crystal display, video display system and vehicle |
| US11475808B2 (en) | 2017-09-08 | 2022-10-18 | Rohm Co., Ltd. | Liquid crystal display device, image display system and vehicle |
| US11922840B2 (en) | 2017-09-08 | 2024-03-05 | Rohm Co., Ltd. | Liquid crystal display device, image display system and vehicle |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3593392B2 (en) | 2004-11-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7113180B2 (en) | Plurality of column electrode driving circuits and display device including the same | |
| US6771258B2 (en) | Semiconductor device | |
| JP2001306040A (en) | Liquid crystal display device | |
| JP3638123B2 (en) | Display module | |
| KR20010007308A (en) | Liquid crystal display device | |
| US20030030604A1 (en) | Liquid crystal display | |
| KR20070057301A (en) | Connector for flexible printed circuit, flexible printed circuit inserting the same, and display device having the same | |
| US6707440B2 (en) | Semiconductor device | |
| CN110556078A (en) | display device | |
| JPH0313989A (en) | Integrated circuit for liquid crystal display and liquid crystal display device | |
| JPH0990396A (en) | Liquid crystal display device and control ic therefor | |
| JP2006018154A (en) | Liquid crystal display | |
| KR100392603B1 (en) | Driver Intergrated Circuit unit for Liquid Crystal Display Device | |
| JP3671237B2 (en) | Display device | |
| US7158128B2 (en) | Drive unit and display module including same | |
| KR100462379B1 (en) | LCD | |
| JP3272296B2 (en) | Liquid crystal display | |
| JP2001177040A (en) | Semiconductor integrated circuit, printed circuit board mounting the same thereon and liquid crystal display device using this printed circuit board | |
| JPH10207434A (en) | Liquid crystal display device | |
| JPH04333095A (en) | Semiconductor device | |
| JP2001033762A (en) | Planar display device | |
| JP2004310132A (en) | Driving circuit for a plurality of column electrodes, and display device | |
| KR102607898B1 (en) | Display device | |
| KR100233004B1 (en) | Lcd module | |
| JP2004302490A (en) | A plurality of column electrode driving circuits and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040415 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040601 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040721 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20040824 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20040830 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070903 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080903 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080903 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090903 Year of fee payment: 5 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090903 Year of fee payment: 5 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090903 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100903 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100903 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110903 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120903 Year of fee payment: 8 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120903 Year of fee payment: 8 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120903 Year of fee payment: 8 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120903 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130903 Year of fee payment: 9 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |