JPH098664A - Digital sigma modulator - Google Patents

Abstract

PURPOSE: To make a digital sigma modulator immune to process fluctuation and to remove integration error by delaying a differential signal between a signal, for which a quantized output signal is integrated and D/A converted, and an input signal for one clock, quantizing that signal for one bit and outputting it as a signal Y. CONSTITUTION: An integrator 7 integrates a digital output signal Y and generates an integrated signal CD of (n) bits, and a DAC 8 of (n) bits D/A converts the signal CD and outputs an analog signal AA to an adder 1. The adder 1 performs the subtraction of the input signal X and the signal AA, generates the differential signal and sends it to a delayer 6 and in response to the supply of a clock, the delayer 1 delays that differential signal for one clock. A quantizer 3 quantizes that delayed differential signal with one bit and outputs the result as the digital output signal Y. Thus, since an analog circuit or the like such as an amplifier weak for capacitor or process fluctuation to cause the generation of integration error can be removed, this device can be easily made into an integrated circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delta sigma modulator, and more particularly to a delta sigma modulator used in an A / D conversion circuit or a D / A conversion circuit.

[0002]

2. Description of the Related Art A delta-sigma modulator converts an analog signal into a corresponding pulse density modulated signal, and its basic principle is, for example, edited by Institute of Electronics, Information and Communication Engineers, Digital Signal Processing Handbook, No. 235-236. page,
As described in Ohmsha (1993) (Reference 1), for noise shaping in a feedback loop that quantizes the difference between the input signal and the D / A converted signal and returns it to the D / A converter. Is a modulator of the type in which this filter is provided immediately before the quantizer, and it is also called a noise shaping type because the spectrum of the quantization noise is distributed more in high frequencies. If the quantizer is set to 1 bit, the resolution of the D / A converter is also 1 bit, so it is suitable for integrated circuits.
By adding a thinning filter to the code output to form a high precision A / D converter, or by passing a digital signal sequence through an interpolation filter to a high sampling rate and then passing it through a digital delta sigma modulator, a high precision Configure a D / A converter.

A conventional delta-sigma converter of this type is, for example, an analog arithmetic circuit described in Japanese Patent Laid-Open No. 138609/1990 (Reference 2) or an A / D converter described in Japanese Patent Laid-Open No. 125355/1993 (Reference 3). It is used as the main component of each vessel.

Referring to FIG. 4 which shows a block diagram of a conventional delta sigma modulator described in Documents 1 and 2, this conventional delta sigma modulator is a delay device 4 for delaying an output signal Y and outputting a delay signal D. , A 1-bit D / A converter (DAC) 5 for converting the delay signal D into a 1-bit analog signal A
An adder 1 that subtracts the analog signal A and the input signal X to generate a difference signal B; an analog integrator 2 that integrates the difference signal B to generate an integrated signal C; And a quantizer 3 which is a comparator for generating an output signal Y.

Next, referring to FIG. 4, the operation of the conventional delta-sigma modulator will be described. First, the adder 1 outputs the difference signal B between the input signal X and the analog signal A output from the 1-bit DAC. Then, the integrator 2 integrates the difference signal B to generate an integrated signal C, which is supplied to the quantizer 3. The quantizer 3 quantizes the integrated signal C, but since the quantization noise Q is added thereto, the output signal Y is expressed by the following equation. Y = (X−YZ ⁻¹ ) / (1−Z ⁻¹ ) + Q …………………………………… (1) Transforming this, Y = X + Q (1−Z ⁻¹ ). ……………………………………………………… (2) However, Z is a delay operator. Furthermore, if this expression is expressed in the frequency domain for the sake of clarity, the following expression is obtained.

[0006]

Therefore, | Y | = | X | + | Q || sin (πf / fs) | ... (4) where fs is the sampling frequency.

From these results, it can be seen that the conventional delta-sigma modulator with this configuration has a characteristic of blocking low frequencies with respect to the quantization noise Q, that is, performs a modulation operation.

[0009]

Since the above-mentioned conventional delta-sigma modulator requires an analog integrator as an integrator, it has a high gain amplifier such as an operational amplifier which is an analog circuit and a capacitor for integration. Although used as an essential component, analog circuits are vulnerable to process variations, and
There is a drawback in that the leakage of the electric charge of the capacitor causes an integration error.

[0010]

A delta-sigma modulator according to the present invention comprises a digital integrating circuit for integrating a digital output signal and outputting an integrated signal of n (integer) bits, and n for converting the integrated signal into an analog signal. A bit D / A conversion circuit, an adder circuit for subtracting the analog signal and the input signal to generate a difference signal, and a delay difference signal for delaying the difference signal by one clock in response to a clock supply to generate a delayed difference signal. And a quantization circuit that quantizes the delay difference signal with 1 bit and outputs the digital output signal.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Next, referring to FIG. 1, which is a block diagram in which components common to those of FIG. 4 are designated by common reference characters / numerals, the embodiment of the present invention shown in FIG. In addition to the conventional adder 1 and quantizer 3, the delta sigma modulator of (1), a digital integrator 7 that integrates a digital output signal Y to generate an n-bit integrated signal CD, The signal CD is DA converted to generate an analog signal AA.
A bit DAC 8 and a delay unit 6 that transfers the difference signal B to the quantizer 3 when the clock CK is at the H level are provided.

Next, the operation of this embodiment will be described with reference to FIG. 1 and FIG. 2 showing the time charts of the respective parts. First, the delayer 6 operates when the clock CK is at the H level. The difference signal B is transferred to the quantizer 3. In FIG. 2, the output signal Y of the quantizer 3 at this time is “+1”.
And is accumulated in the integrator 7, and the integrated signal CD becomes 11 at this time. The next DA converter 8 outputs an analog signal AA corresponding to the integrated signal CD, and the adder 1 again takes the difference from the input signal X and outputs a difference signal B. In this way, the output signal Y is output one after another.

For convenience of explanation, the number of bits n of the DAC 8 is n.
5, the specific operation will be described.

First, assuming that the input signal X is "0.3" and the integration result is "10", the output signal AA of the DAC 8 is
Will be '10 / 32 '. When the difference signal B between the input signal X and the analog signal AA calculated by the adder 1 is Δ (n), the following equation is obtained. Δ (n) = 0.3−10 / 32 = −0.0125 <0 ……………… (5) This difference signal B passes through the delay device 2 and becomes the delay signal DB as the quantizer 3 , And the quantizer 3 outputs the output signal Y (n)
'-1' is output as. Then, this output signal Y
In response to the supply of (n), the integrator 7 decrements the inside and outputs an integrated signal CD'9 '. Since the input signal X is the same as before, the value Δ (n of the difference signal B output from the adder 1
+1) is as follows. Δ (n + 1) = 0.3-9 / 32 = 0.01875> 0 (6) As the output signal Y (n + 1) of the quantizer 3 in this case, '
+1 'is output. The output signal Y is output by repeatedly executing the above.

Next, the operation of this modulator will be described with reference to FIG. 3 showing simulation results when the input signal X is changed. First, the input signal of the delay device 6 and the quantizer 3 will be described. Since the difference between X and the analog signal AA after the D / A conversion of the digital integrated signal CD is delayed and compared by the delay device 6 and the quantizer 3, the quantization noise Q is added here, and therefore the output signal Y is It is expressed by the following equation. Y = {X−Y / (1−Z ⁻¹ )} Z ⁻¹ + Q ……………………………… (7) By modifying this, Y = (XZ ⁻¹ + Q) ( 1-Z ^-1 ) ………………………………………… (8) However, Z is a delay operator. Furthermore, if this expression is expressed in the frequency domain for the sake of clarity, the following expression is obtained.

[0016]

Therefore, | Y | = (| X | + | Q |) | sin (πf / fs) | ... (10) From these results, the delta-sigma modulator of the present embodiment can quantize noise. It can be seen that Q has a characteristic of blocking low frequencies, that is, the same modulation operation as in the past is performed.

As described above, the delta-sigma modulator according to the present embodiment can eliminate the analog circuit such as a high-gain operational amplifier which is weak in the process variation and has a large variation and the integrating capacitor which is a cause of the error, and can be integrated into an integrated circuit. Will be easier.

[0019]

As described above, the delta-sigma modulator of the present invention includes a digital integrating circuit that integrates a digital output signal and outputs an n-bit integrated signal, and an n-bit D / A conversion circuit. As a result, it is possible to remove an analog circuit such as an amplifier or the like, which is a factor that causes an integration error and is weak against process fluctuations.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a delta-sigma modulator of the present invention.

FIG. 2 is a time chart showing an example of the operation of the delta sigma modulator of the present embodiment.

FIG. 3 is a waveform diagram showing an example of a simulation result of signal waveforms at various parts in the delta-sigma modulator of the present embodiment.

FIG. 4 is a block diagram showing an example of a conventional delta-sigma modulator.

[Explanation of symbols]

 1 adder 2,7 integrator 3 quantizer 4,6 delay device 5,8 DAC

Claims (2)

[Claims] 1. A digital output signal is integrated to obtain n (integer).
A digital integrator circuit that outputs a bit integration signal, and an n-bit D / that converts the integration signal into an analog signal
An A conversion circuit; an adder circuit that subtracts the analog signal and an input signal to generate a difference signal; and a delay circuit that delays the difference signal by one clock in response to the supply of a clock to generate a delayed difference signal. A quantized circuit that quantizes the delay difference signal with 1 bit and outputs the digital output signal. 2. The delta-sigma modulator according to claim 1, wherein the quantization circuit includes a comparison circuit that determines whether the delay difference signal is positive or negative and generates the digital output signal.