JPH098662A - Encoder circuit and a/d converter provided with the same - Google Patents

Abstract

PURPOSE: To reduce the number of parts and to enable a high-speed operation with high resolution by synthesizing the output signals of respective bit lines of encoder circuits by dividing capacitance to appear on the lines, and providing a buffer for outputting a binary code. CONSTITUTION: Precharge and encode operations are controlled by a control signal 14, a code select signal is divided into (m) groups pieces of signal groups 23-25, and the groups 23-25 are inputted to encoding blocks 26-28 with the respective input numbers of j-l. At the time of encode operation, corresponding to the selection of the groups 23-25, the respective blocks 26-28 output encoded signals 29-31 of respective (n) bits and the signals 29-31 are inputted to a bit line dividing buffer 32. The buffer 32 logically synthesizes the respective bits of signals 29-31, shapes the waveform and outputs a binary code output 22. Thus, the number of transistors to be connected on the lines 29-31 can be reduced to be 1/m, therefore, the total sum of parasitic capacitances becomes 1/m as well, and time for precharge and encode operations can be shortened to be 1/m.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an encoding circuit and an A / D.
It concerns a converter.

[0002]

2. Description of the Related Art In many industrial fields, digitization of signal processing has advanced, and an A / D having a function of converting an analog value into a digital value, which is a key device for digital signal processing.
The converter is also required to have high speed and high accuracy. In particular, a parallel A / D converter is mentioned as a basic configuration method of an image A / D converter mounted on a VTR or the like for converting an analog video signal into a digital value. Therefore, the configuration and operation of the parallel A / D converter will be shown.

FIG. 2 shows the configuration of a 3-bit parallel A / D converter. Between the reference voltage 1 and the reference voltage 2, the reference resistor string 3
Is connected. The reference resistor string 3 divides the potential difference between the reference voltages 1 and 2 into equal potentials by the reference resistor 4, and the potential points VR1 to VR7 divided by the reference resistor 4 are the respective voltage comparators 6 in the voltage comparator column 5. Connected to one of the input terminals. The other input terminal of each voltage comparator 6 in the voltage comparator array 5 is connected to the analog input signal 7. The output terminal of the voltage comparator array 5 is a code selection circuit 8
, And the output terminal of the code selection circuit 8 is connected to the input terminal of the encoding circuit 9. The output terminal of the encoding circuit 9 is connected to the input terminal of the code conversion circuit 10, and the code conversion circuit 10 outputs a 3-bit A / D conversion output 11. The above is the configuration of the parallel A / D converter.

In order to realize a high resolution A / D converter, it is necessary to divide the two reference voltages 1 and 2 by many reference resistors 4. That is, as the resolution of the A / D converter increases, the potential difference between adjacent comparison reference voltages also decreases. At this time, however, in the A / D converter composed of CMOS transistors in particular, the constituent elements of each circuit are A / D conversion output 11 due to variations in
There is a problem in that a miscode occurs. As a means for solving this problem, a structure for outputting the gray code shown in (Table 1) is generally used in the encoding circuit 9 in FIG. 2, and the A / D converter once converts the voltage comparison result into the gray code. After the conversion, the code conversion circuit 10 converts the binary code shown in Table 2 and outputs the A / D conversion result (Japanese Patent Laid-Open No. 58-71726). The mechanism for preventing the occurrence of miss codes by the gray code shown in (Table 1) will be described below.

[0005]

[Table 1]

[0006]

[Table 2]

For example, in FIG. 2, assuming that the potential difference between VR4 and VR5 is very small under the condition of VR0 <VR8, VR4
The voltage comparator connected to VR4 judges that the analog input signal voltage value is smaller than the comparison reference voltage value due to variations in the constituent elements of the voltage comparator connected to the voltage comparator and the voltage comparator connected to VR5. The voltage comparator connected to VR5, which outputs 0 level, judges that the analog input signal voltage value is larger than the comparison reference voltage value, and outputs 1 level. Result C1 ~ C7 (1
110100) is output. The code selection circuit 8 sets the three output signals P3, P4, and P5 to one level due to the erroneous output of the voltage comparator array 5, and erroneous code selection signals P0 to P7.
(00011100) is output. The encoding circuit 9 outputs a composite code of three binary codes corresponding to one level of the incorrect output of the code selection circuit 8. Here, consider a case where the encoding circuit 9 has a structure for outputting the binary code shown in (Table 2). Now the code selection signal is P3,
If three binary codes corresponding to P4 and P5 are selected, three codes 011, 100 and 101 are simultaneously selected. The encoding circuit 9 outputs 0 (000) in decimal when a 0-level priority is output (AND output), and a 1-level priority output (OR output), as a composite code of three codes. It outputs 7 (111) in decimal. When the structure for outputting the binary code to the encoding circuit 9 is used in this way, the A / D conversion output 11 becomes a miscode for the incorrect comparison result of the voltage comparator array 5.

On the other hand, when the encoding circuit 9 has a structure for outputting a 3-bit Gray code as shown in (Table 1), the three codes 010, 110 and 111 are simultaneously generated under the above conditions. The selected encoding circuit 9 is 3 (010) in decimal for AND output, and 1 for OR output.
Outputs 5 (111) as a 0-digit number. When the structure for outputting the Gray code shown in (Table 1) is used for the encoding circuit 9 as described above, A /
It is possible to prevent the occurrence of a miscode in the D conversion output.

In the structure of FIG. 2, however, considering the case where an analog signal having a voltage value equal to the reference voltage value VR4 is input, the comparison result C of the voltage comparator connected to VR4 is given.
4 is an intermediate level between 0 level and 1 level. If there are variations in the constituent elements of the two exclusive OR circuits that output P4 and P5 to the input C4 in the code selection circuit 8, both outputs P4 and P5 may output 0 level. In such a case, the code selection signal input to the encoding circuit 9 is in the non-selection state (0000000), and the A / D conversion output 11 has the minimum value (000) or the maximum value (111) depending on the structure of the encoding circuit 9. Will generate the miscode of.

In order to avoid this phenomenon, in FIG. 4, outputs CK-1 and CK + 1 (K = 1, 2, 3, 4,
The structure is such that the exclusive OR of (5, 6, 7) is used as the code selection signal PK (JP-A-63-269829). According to this structure, for example, when an analog signal having a voltage value equal to VR4 is input, even if the comparison result C4 of the voltage comparator connected to VR4 becomes an intermediate level between 0 level and 1 level, code selection is performed. The output P4 for the input C5 (0 level) and C3 (1 level) in the circuit 12 is 1
The level is output, and the code output by the code selection circuit 12 is not at least in the non-selected state. Therefore, the A / D
The conversion output 11 has a minimum value (000) or a maximum value (11
There is no mistake in 1).

By the way, the circuit shown in FIG. 3 is conventionally used as the encoding circuit 9 in the A / D converter shown in FIG. The configuration and operation of the conventional encoding circuit shown in FIG. 3 will be described below.

Bit lines 19 to 21 which are capacitive signal lines
The drain terminal of the precharge transistor 15, which is a PMOS transistor, is connected to each of the above. NMO is provided to each of the bit lines 19 to 21 so that the binary code output 22 is output according to the selection of the code selection signal 18.
The drain terminal of the selection transistor 17, which is an S transistor, is connected. Each gate terminal of the selection transistor 17 is connected to each signal line of the code selection signal 18. The source terminal of the selection transistor 17 is N
Encode transistor 16 which is a MOS transistor
Connected to the drain terminal of. The gate terminals of the precharge transistor 15 and the encode transistor 16 are connected to the control signal 14.

When the control signal 14 is at a logic low level, the precharge transistor 15 is on, the encode transistor 16 is off, and each bit line 1
9 to 21 are charged with electric charges and fixed at a high logic level. Next, when the control signal 14 changes to the high level, the precharge transistor 15 is turned off and the encode transistor 16 is turned on. This time,
For example, if P4 of the code selection signal 18 indicates a high level of a logic level, and P0 to P3 and P5 to P7 indicate a low level of a logic level (that is, P4 is selected).
Select transistor 1 whose gate terminal is connected to P4
Since 7 is turned on and the encode transistor 16 is turned on, the electric charge stored in the bit line 21 is discharged, and the bit line 21 changes to the logic low level. At this time, the bit lines 19 and 20 are in a state of holding the high level of the logic level. As a result, the binary code output 22 is the gray code (110) corresponding to 4 in decimal.
Is output (hereinafter, this is referred to as an encoding operation). Next, when the control signal 14 changes to a logic low level,
The precharge transistor 15 is turned on, the encode transistor is turned off, and the bit line 21, which has been at the low level of the logic level, is charged again (hereinafter referred to as precharge operation).

FIG. 5 shows a conventional encoding circuit 13 used in the A / D converter shown in FIG. The precharge operation is similar to that of the encoding circuit shown in FIG. In the encoding operation, when the control signal 14 changes to the logic high level, the precharge transistor 15 is turned off,
The encode transistor 16 changes to the on state. At this time, for example, if P3 and P4 of the code selection signal 46 indicate a high level of a logical level and P0 to P2 and P5 to P8 indicate a low level of a logical level (that is, P3 and P4 are selected), The selection transistor 17 whose gates are connected to P3 and P4 is turned on, and the bit lines 19 and 2 are connected.
The electric charge stored in 1 is discharged, and the bit lines 19 and 21 change to low level. At this time, the bit line 20 is in the state of holding the high level. As a result, binary code output 2
2 outputs a gray code (010) corresponding to 3 in decimal. As described above, the encoding circuit 13 shown in FIG. 5 is configured to output (AND output) the logical product of two selection results selected by the code selection signal 46 as the binary code output 22.

By the way, the encoding circuit 9 shown in FIGS.
The operation speeds of the precharge operation and the encode operation of 13 depend on the total sum of the parasitic capacitances on the bit lines 19 to 21. That is, the operating speed of the encoding circuits 9 and 13 is the selection transistor 17 connected to each of the bit lines 19 to 21.
Will depend on the total number of

The delay time tp from the change of the control signal 14 to the logic high level until the encoding circuits 9 and 13 complete the precharge operation is the bit line 19 of each bit line 19.
If the sum of the drain capacitances of the selection transistors 17 connected to ˜21 is Cn, it is expressed by (Equation 1). In (Equation 1), Vtp is the threshold voltage of the precharge transistor 15. Similarly, the delay time te from the change of the control signal 14 to the logic low level until the encoding circuits 9 and 13 finish the encoding operation is the selection transistor connected to all the bit lines 19 to 21. 1
When the total sum Ct of the drain capacitances of 7 is used, it is expressed by (Equation 2). In (Equation 2), Vtn is the threshold voltage of the encode transistor 16.

[0017]

[Equation 1]

[0018]

[Equation 2]

As shown in (Equation 1) and (Equation 2), the operation time of the precharge operation and the encoding operation of the encoding circuits 9 and 13 depends on the drain capacitance of the selection transistor 17 connected to each bit line. Proportional to the sum of. When the resolution of the A / D converter increases by 1 bit, the encoding circuits 9 and 1
The total number of select transistors 17 in 3 is doubled. That is, when the resolution of the A / D converter increases by 1 bit, the operating speed of the encoding circuit decreases to 1/2. This has been a cause of impeding the high-speed operation of the A / D converter when realizing the high-resolution A / D converter.

[0020]

SUMMARY OF THE INVENTION As described above,
The operation time of the precharge operation and the encode operation of the encoding circuit in the conventional A / D converter is proportional to the total number of select transistors connected to the bit line. When the bit number of the A / D converter increases by 1 bit, the number of select transistors connected to the bit line doubles. Therefore, the operation time of the precharge operation and the encode operation of the encoding circuit is doubled, which hinders the high-speed operation when realizing the high resolution A / D converter.

In view of the above problems, the present invention divides the bit lines of the encoding circuit to reduce the total number of select transistors connected to one bit line, thereby performing the precharge operation and the encode operation. Realizes a high-speed encoding circuit with a short time. The purpose is to: By using the encoding circuit of the present invention in an A / D converter, high-speed operation is possible even in a high resolution A / D converter.

[0022]

In order to achieve the above-mentioned object, according to the present invention, a capacitive signal line is a bit line for holding a first voltage of a logic level by charging, and an instruction signal. The bit line having a plurality of switches for discharging the charged charge and changing it to the second voltage of the logic level, each bit line discharging the charged charge according to each instruction signal. The first encoding circuit and the first encoding circuit have the same configuration as that of the first encoding circuit, but have different bit lines discharged by the instruction signal. A bit line output signal is connected to a first input terminal, each bit line output signal of the second encoding circuit is connected to a second input terminal, and a bit line appears at the first input terminal. Capacity and the second input end A bit line dividing buffer for dividing the capacitance of the bit line appearing in the above and outputting the binary code by synthesizing the respective input signals, and the encoding circuit is an A / D converter. By using it, an A / D converter with high resolution and operating at high speed is realized.

[0023]

Since the encoding circuit of the present invention has a small number of selection transistors connected to each bit line, and therefore the operation time of the precharge operation and the encoding operation is short, the encoding circuit of the present invention operates at high speed. A / D converter enables high-speed operation even with high resolution.
A D converter can be realized.

[0024]

【Example】

(Embodiment 1) FIG. 1 is an embodiment relating to claim 1 of the present invention and shows an n-bit (n = 1, 2, 3, ...) Encoding circuit. The precharge operation and the encode operation are controlled by the control signal 14. In the present embodiment, the code selection signal is divided into m (m = 1, 2, 3, ...) Code selection signal groups 23 to 25. Each of the code selection signal groups 23, 24, 25 is j (j = 1, 2,
3, ...), k (k = 1, 2, 3, ...) And l (l = 1, 2, 3, ...) The number of inputs is divided into m. Are input to the encoded blocks 26, 27 and 28. Each coding block 26, 27, 28 has
During the encoding operation, the code selection signal groups 23, 24, 25
Of the n-bit encoded signals 29 and 3 respectively.
0 and 31 are output. Each coding block 26, 2
Encoded signals 29, 30, 31 output from 7 and 28
Is input to the bit line division buffer 32. The bit line input buffer 32 logically synthesizes each bit of the input coded signals 29 to 31 and simultaneously performs waveform shaping,
The binary code output 22 is output.

In this embodiment, since the encoding circuit is divided into m encoding blocks 26 to 28, the number of select transistors connected to each bit line 29 to 31 is 1 / m of the conventional one. Reduced to. Therefore, the total sum of the parasitic capacitances on each bit line is 1 / m of the conventional one, and as a result, the operation time of the precharge operation and the encoding operation is shortened to 1 / m of the conventional one.

(Embodiment 2) FIG. 6 shows an embodiment according to claim 2 of the present invention, which is a configuration example of the encoding circuit 9 used in the 3-bit A / D converter shown in FIG. In this embodiment, a 3-bit gray code is output according to the selection of the code selection signal 18. The code selection signal 18 is divided into two code selection signal groups (P1, P3, P5, P7) and (P0, P2, P4, P6) and input to the coding blocks 33 and 34, respectively. The encoding blocks 33 and 34 include three bit lines 19 to
21, a precharge transistor 15 which is a PMOS transistor, an encode transistor 16 which is an NMOS transistor, and a selection transistor 17 which is an NMOS transistor. The drain terminal of the precharge transistor 15 is connected to each bit line 19
Connected to ~ 21. The gate terminal of the selection transistor 17 is connected to the code selection signal 18, and the drain terminal of the selection transistor 17 outputs the coded signals 35 and 36 in accordance with the selection of the code selection signal 18.
It is connected to each bit line 19-21. The source terminal of the selection transistor 17 is the encode transistor 1.
6 is connected to the drain terminal. The gate terminals of the precharge transistor 15 and the encode transistor 16 are connected to the control signal 14. The encoded signals 35 and 36 output from the encoding blocks 33 and 34 are input to the bit line division buffer 37. The bit line division buffer 37 is composed of a logical product circuit 38, and D10 and D20, D11 and D21, D12 in the encoded signals 35 and 36.
And D22 are logically synthesized and waveform shaped,
It outputs a binary code output 22 which is a 3-bit Gray code.

In the encoding operation of the encoding circuit of the present invention shown in FIG. 6, for example, P4 of the code selection signal 18 indicates a logical high level, and P0 to P3 and P5 to P7 indicate a logical low level ( That is, P4 is selected), the selection transistor 17 whose gate terminal in the encoding block 34 is connected to P4 is turned on, and the electric charge stored in the bit line 21 during the precharge operation is discharged, The bit line 21 changes to a logic level low level. At this time, all the bit lines in the encoding block 33 and the bit lines 19 and 20 in the encoding block 34 are in a state of holding the charges accumulated during the precharge operation, and show a high logic level. As a result, the encoded signal 35 output by the encoding block 33 outputs (111), and the encoded signal 36 output by the encoding block 34 outputs (110). The bits of the encoded signals 35 and 36 are logically combined by the bit line division buffer 37, and the logical product (110) of the bits of the encoded signals 35 and 36 is output as the binary code output 22.

The encoding circuit of this embodiment shown in FIG. 6 has the configuration shown in FIG.
The number of select transistors 17 connected to one bit line is reduced from four to two as compared with the conventional encoding circuit shown in FIG. Therefore, the total sum of the drain capacitances of the selection transistors 17 parasitic on each bit line is reduced to 1/2 of the conventional one, so that the operation speed is twice as high as that of the conventional encoding circuit.

In this embodiment, the code selection signal 18 is 2 (P1, P3, P5, P7) and (P0, P2, P4, P6).
An example in which the code selection signal 18 is divided into one code selection signal group is shown, but the method of dividing the code selection signal 18 is arbitrary.

In the present embodiment, the coding circuit which outputs the gray code as the binary code output 22 by selecting the code selection signal 18 has been described. However, when the selection transistor 17 is connected, the coding circuit outputs the gray code. The binary code 22 can output an arbitrary code.

Although the coding circuit of this embodiment is divided into two coding blocks 33 and 34, the coding block can be divided into a number equal to the number of inputs of the code selection signal 18. is there.

In this embodiment, each coded signal 35, 3
The case where the logical product of 6 is output (AND output) as the binary code output 22 has been described.
A configuration in which the logical sum of 6 is output (OR output) is also feasible.

(Embodiment 3) FIG. 7 is an embodiment according to claim 3 of the present invention, which is a structural example of the encoding circuit 13 used in the 3-bit A / D converter shown in FIG. This embodiment outputs a 3-bit Gray code according to the selection of the code selection signal 46. The code selection signal 46 includes three code selection signal groups (P0, P3, P6), (P1, P4, P7), (P2, P).
5 and P8), which are coded blocks 39 and 4 respectively.
0 and 41 are input.

In the encoding operation of the encoding circuit of the present invention shown in FIG. 7, for example, P3 and P4 of the code selection signal 46 indicate a logic level high level, and P0 to P2 and P5 to P8 indicate a logic level low level. (That is, P3 and P4 are selected), the selection transistor 1 whose gate terminal is connected to P3 in the encoding block 39.
7 and the select transistor of which the gate terminal is connected to P4 in the encoding block 40 is turned on, and as a result, the encoded signal 4 of the encoding blocks 39, 40 and 41 is
2, 43 and 44 are (011), (110),
(111) is output. Each bit in the encoded signals 42 to 44 is logically combined by the bit line division buffer 37, and the logical product (010) of the encoded signals 42 to 44 is 2
It is output as a binary code output 22.

The coding circuit of the present embodiment shown in FIG. 7 divides the coding block into three, so that the transistor 17 parasitic on each bit line is compared with the conventional coding circuit shown in FIG. Since the sum of the drain capacitances of 1 to 3 is reduced to 1/3, it is possible to operate three times faster than the conventional encoding circuit.

In this embodiment, the code selection signals 46 are (P0, P3, P6), (P1, P4, P7), (P
Although an example in which the code selection signal 46 is divided into three code selection signal groups (2, P5, P8) is shown, the method of dividing the code selection signal 46 is arbitrary.

In the present embodiment, the coding circuit which outputs the gray code as the binary code output 22 by selecting the code selection signal 46 is shown, but the binary code output from the coding circuit is an arbitrary code. Can be output.

Although the coding circuit of this embodiment is divided into three coding blocks 39 to 41, the number of divisions of the coding block is arbitrary as long as it is equal to or less than the number of inputs of the code selection signal 46. is there.

In this embodiment, the encoded signals 42, 4 are
The logical product of 3, 44 is output as a binary code output 22 (A
ND output), the encoded signal 3
A configuration that outputs the logical sum of 5 and 36 (OR output) is also possible.

[0040]

Since the encoding circuit of the present invention has a small number of selection transistors connected to each bit line, and the operation time of the precharge operation and the encoding operation is short, the encoding circuit of the present invention operates at high speed. Is used in the A / D converter, it is possible to operate the A / D converter with high resolution and high speed.
A D converter can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an encoding circuit according to claim 1 of the present invention.

FIG. 2 is a block diagram of a conventional parallel type A / D converter.

3 is a block diagram of a conventional encoding circuit used in the parallel A / D converter shown in FIG.

FIG. 4 is a block diagram of a conventional parallel type A / D converter.

5 is a configuration diagram of a conventional encoding circuit used in the parallel A / D converter shown in FIG.

FIG. 6 is a configuration diagram of an encoding circuit according to claim 2 of the present invention used in the parallel A / D converter shown in FIG.

7 is a configuration diagram of an encoding circuit according to claim 3 of the present invention used in the parallel A / D converter shown in FIG.

[Explanation of symbols]

 8,12 Code selection circuit 9,13 Coding circuit 10 Code conversion circuit 11 A / D conversion output 14 Control signal 15 Precharge transistor 16 Encoding transistor 17 Selection transistor 18, 46 Code selection signal 19-21 Bit line 22 Binary code Output 23 to 25 Code selection signal group 26 to 28, 33, 34, 39 to 41 Coded block 29 to 31, 35, 36, 42 to 44 Coded signal 32, 37 Bit line division buffer 38, 45 AND circuit

Claims (3)

[Claims] 1. A bit line for charging a capacitive signal line with a charge to hold a first voltage of a logic level, and discharging a charged charge according to an instruction signal to generate a second voltage of a logic level. The same configuration of the first encoding circuit, which has the bit line provided with a plurality of switches so that the bit line can be changed, and each bit line discharges the electric charge charged in accordance with each instruction signal. The second encoding means having different bit lines discharged according to the instruction signal and the output signals of the respective bit lines of the first encoding circuit are connected to the first input terminal, and the second encoding means is connected to the second input means. The output signal of each bit line of the encoding circuit is connected to the second input terminal, and the capacitance of the bit line appearing at the first input terminal and the capacitance of the bit line appearing at the second input terminal are divided, Combining each input signal Encoding circuit that includes a bit line division buffers for outputting a binary code. 2. A means for generating a plurality of comparison reference voltages for sampling an analog voltage value that arbitrarily changes with the passage of time and converting it into a digital value, and the analog voltage value and the comparison reference voltage value. And a comparison result of the i-th voltage comparator when the order of the voltage comparators in the voltage comparator string is i and the comparison result is output.
A code selection circuit which outputs an i-th code selection signal using the comparison result of the th voltage comparator as an input, and a code which outputs a digital binary code selected by the i-th code selection signal of the code selection circuit An A / D converter including an encoding circuit and an encoding circuit that converts the binary code into a binary code and outputs the binary code as the digital value, wherein the encoding circuit includes the encoding circuit according to claim 1. An A / D converter characterized in that 3. A means for generating a comparison reference voltage according to claim 2, a voltage comparator array according to claim 2, and (i-1) where i is the order of the voltage comparators in the comparison reference voltage. ) Th code comparator and a (i + 1) th voltage comparator comparison result as an input and outputs an i-th code selection signal, and a code selection circuit's i-th code selection circuit. A composed of an encoding circuit for outputting a binary code by selection by a signal and selection by an (i + 1) th code selection signal, and a code conversion circuit for converting the binary code into a binary code and outputting it as the digital value An A / D converter, wherein the encoding circuit comprises the encoding circuit according to claim 1.