JPH098614A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To turn the power consumption of a storage circuit on standby to zero by comparing the output logic value and input logic value of the storage circuit at a comparator circuit and disconnecting the storage circuit from a power source when the input logic value is not changed in respect to the output logic value of the storage circuit. CONSTITUTION: A latch circuit 12 is composed of inverters INV1-INV4 and connected to hold output data even when the power source of an FF circuit 11 is turned off. The INV 1 and 2 hold the output values of data Q from the circuit 11 and the INV 3 and 4 hold the output values of data QX from the circuit 11. An MOSFET 14 inputs the output signal of an EXNOR circuit 13 and controls power supply to the circuit 11. Namely, the source of the FET 14 is connected to a power supply line VDD and its drain is connected to the internal power supply line of the circuit 11. When the input logic value of the circuit 11 is equal with the output logic value, the FET 14 is turned off and the power supply to the circuit 11 is cut off. Oppositely, when the input and output logic values of the circuit 11 are different, the FET 14 supplies power to the circuit 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a flip-flop circuit composed of CMOS type field effect transistors.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have become faster and more highly integrated due to the expansion of applications of semiconductor devices and the progress of technology. Further, since the circuit composed of the CMOS type FET is driven by voltage, it is also characterized in that it consumes less power than a bipolar transistor driven by current. Furthermore, in portable electronic devices, circuit power consumption is being reduced in order to prolong battery drive time. Above all, there is a demand for reducing the power consumption of a flip-flop circuit that operates based on a clock signal during standby.

FIG. 8A is a symbol diagram showing a D-type flip-flop circuit. In FIG. 8A, 10 is data D based on a clock signal (hereinafter referred to as CK signal).
Is a flip-flop circuit that temporarily holds the
It is composed of an inverter and a transfer gate formed by an S-type FET. In addition, FIG. 8B shows an internal configuration diagram of the D-type flip-flop circuit. FIG. 8 (B)
In FIG. 1, 1 is a master latch circuit that inverts and holds the data DIN based on the non-inverted CK0 signal and the inverted CKx signal, and 2 inverts the output data of the master latch circuit 1 based on the non-inverted CK0 signal and the inverted CKx signal. It is a slave latch circuit for holding the same. A clock distribution circuit 3 outputs the non-inverted CK0 signal and the inverted CKx signal to the master latch circuit 1 and the slave latch circuit 2. The clock distribution circuit 3 inputs an CK signal and outputs an inverted CKx signal, and an inverter INV1 and this inverter INV1.
It is composed of an inverter INV2 which inputs the output signal of the above and outputs a non-inverted CK0 signal. The inverters INV1 and INV2 are connected between the power supply line VDD and the ground line GND.

Next, the operation of the flip-flop circuit will be described. First, when the CK signal is supplied to the clock distribution circuit 3, the non-inverted CK signal and the inverted CK signal are output from the inverters INV1 and INV2 to the master latch circuit 1 and the slave latch circuit 2. In this state, for example, when the input data DIN = “L” (low) level is confirmed, CKx
The data DIN is taken into the master latch circuit 1 in synchronization with the signal and the CK0 signal, and the master latch circuit 1 holds the "H" level data. Then, the slave latch circuit 2 inverts the output data of the master latch circuit 1 based on the non-inverted CK signal and the inverted CK signal, and holds the “L” level data. As long as the input data DIN does not change, the flip-flop circuit 10 outputs "L" level data Q.

[0005]

However, according to the conventional flip-flop circuit 10, the output data Q
However, even if the input data DIN has not changed, the CK signal supplied to the clock distribution circuit 3 is "H" →
Since the “L” → “H” level is repeated, the inverters INV1 and INV2 operate, and the power supply line VDD and the ground line GND are
A through current i will flow between and.

Therefore, power is consumed in the clock distribution circuit 3 even while waiting for the input of the data DIN, which causes a problem of accelerating battery consumption of a portable electronic device or the like having a built-in flip-flop circuit.
The present invention was created in view of the problems of the conventional example, and an object of the present invention is to provide a semiconductor integrated circuit capable of suppressing power consumption during standby of a memory circuit operated by a clock signal.

[0007]

As shown in FIG. 1, a first semiconductor integrated circuit according to the present invention has a memory circuit for storing data based on a clock signal and an output logic of the memory circuit. An output circuit that holds a value, a comparison circuit that compares the output logic value of the storage circuit held by the output circuit with the input logic value of the storage circuit, and the storage circuit that inputs the output signal of the comparison circuit When the input logical value and the output logical value are the same, the power supply to the storage circuit is cut off, and when the input logical value and the output logic value of the storage circuit are different, a power supply control circuit for supplying power to the storage circuit is provided. It is characterized by having.

As shown in FIG. 3, the second semiconductor integrated circuit of the present invention has a memory circuit for storing data based on a clock signal, an output logical value of the memory circuit and the memory circuit. A comparator circuit for comparing an input logical value and an output signal of the comparator circuit are input, and when the input logical value and the output logical value of the memory circuit are the same, the clock signal to the memory circuit is cut off and the clock of the memory circuit is cut off. It is characterized by further comprising a clock control circuit which fixes an input to a constant potential and inputs a clock signal to the memory circuit when the input logical value and the output logical value of the memory circuit are different.

As shown in FIG. 4, a third semiconductor integrated circuit according to the present invention has a memory array for storing a plurality of data based on a clock signal and a plurality of output logical values of the memory array. An output circuit for holding, a comparison circuit for comparing a plurality of output logical values of the memory array held by the output circuit with a plurality of input logical values of the memory array, and an output signal of the comparison circuit for inputting the output signal A power supply control circuit that supplies power to the memory array when the input logical value and the output logical value of the memory array are the same, and supplies power to the memory array when the input logical value and the output logical value of the memory array are different. It is characterized by having and.

As shown in FIG. 5, the fourth semiconductor integrated circuit of the present invention has a memory array for storing a plurality of data based on a clock signal, and a plurality of output logical values of the memory array. A comparator circuit for comparing a plurality of input logic values of the memory array, and an output signal of the comparator circuit, and a clock signal to the memory array when the input logic value and the output logic value of the memory array are the same. In other words, a clock control circuit for inputting a clock signal to the memory array when the input logical value and the output logical value of the memory array are different is provided.

In the first to fourth semiconductor integrated circuits of the present invention, preferably, an amplifier circuit for amplifying output data of the memory circuit or the memory array is provided, and the above object is achieved.

[0012]

[Operation] The operation of the first semiconductor integrated circuit of the present invention will be described. First, when input data is determined to be “H” (high) or “L” (low) level while the clock signal is being supplied to the memory circuit, the data is written to the memory circuit in synchronization with the clock signal. The output logical value of this storage circuit is held by the output circuit. The output logic value of the storage circuit held by the output circuit is compared with the input logic value of the storage circuit by the comparison circuit. Then, the power supply control circuit to which the output signal of the comparison circuit is input turns off the power supply to the memory circuit when the input logical value and the output logical value of the memory circuit are the same. When the input logical value and the output logical value of the memory circuit are different, the power supply control circuit supplies power to the memory circuit.

As described above, according to the present invention, since the input logic value and the output logic value of the storage circuit are compared by the comparison circuit, when the input logic value does not change with respect to the output logic value of the storage circuit, the power supply Since the control circuit disconnects the memory circuit from the power source, power consumption of the memory circuit in standby can be zero. The operation of the second semiconductor integrated circuit of the present invention will be described.
First, similarly to the first semiconductor integrated circuit, when the input data is determined while the clock signal is being supplied to the memory circuit, the data is written to the memory circuit in synchronization with the clock signal. Then, the comparison circuit compares the input logical value and the output logical value of the memory circuit. The clock control circuit to which the output signal of the comparison circuit is input cuts off the clock signal to the storage circuit when the input logic value and the output logic value of the storage circuit are the same, and fixes the clock input of the storage circuit to a constant potential. To do. When the input logical value and the output logical value of the memory circuit are different, the clock control circuit inputs the clock signal to the memory circuit.

As described above, according to the present invention, since the input logical value and the output logical value of the memory circuit are compared by the comparator circuit, when the input logical value does not change with respect to the output logical value of the memory circuit, the clock Since the control circuit cuts off the clock signal to the memory circuit and fixes the clock input of the memory circuit to a constant potential, power consumption of the memory circuit in standby can be reduced unlike the first semiconductor integrated circuit. Since the output logic value of the memory circuit is more stable than that of the first semiconductor integrated circuit, the output circuit for holding the output logic value of the memory circuit can be omitted.

According to the third semiconductor integrated circuit of the present invention,
Since the plurality of input logical values of the memory array are compared with the plurality of output logical values by the comparison circuit, when the plurality of input logical values do not change with respect to the plurality of output logical values of the memory array, the power supply control circuit is Since the array is disconnected from the power supply, the power consumption of the standby memory array can be reduced to zero.

According to the fourth semiconductor integrated circuit of the present invention,
Since the comparator circuit compares the plurality of input logical values of the memory array with the plurality of output logical values, when the plurality of input logical values does not change with respect to the plurality of output logical values of the memory array, the clock control circuit Since the clock signal to the memory array is cut off and the clock input of the memory array is fixed to a constant potential, unlike the third semiconductor integrated circuit, the power consumption of the waiting memory array can be reduced. In addition,
Since the output logical value of the memory array is more stable than that of the third semiconductor integrated circuit, the output circuit for holding the output logical value of the memory array can be omitted.

When these semiconductor integrated circuits are combined, the power consumption can be reduced for each circuit block by suspending the storage circuit or the memory array for each circuit block.

[0018]

Embodiments of the present invention will now be described with reference to the drawings. 1 to 7 are explanatory views of a semiconductor integrated circuit according to an embodiment of the present invention. (1) Description of First Embodiment FIG. 1 is a block diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. In FIG. 1, 11 is a flip-flop circuit that holds data DIN based on a clock signal (hereinafter referred to as CK signal), and is an example of a memory circuit. Regarding the inside of the flip-flop circuit 11,
This will be described with reference to FIG.

A latch circuit 12 holds the output logical value of the flip-flop circuit 11, and is an example of an output circuit. The latch circuit 12 is composed of inverters INV1 to INV4 and is connected so that the output data can be held even when the power of the flip-flop circuit 11 is turned off.
The inverters INV1 and INV2 hold the output value of the data Q of the circuit 11, and the inverters INV3 and INV4 hold the output value of the data Qx of the circuit 11, respectively.

Reference numeral 13 is a 2-input exclusive-NOR circuit (hereinafter referred to as EXNOR) for comparing the output logical value of the data of the flip-flop circuit 11 held by the latch circuit 12 with the input logical value of the data to the flip-flop circuit 11. Circuit) and is an example of a comparison circuit. For example, when the input data DIN does not change with respect to the data Q of the circuit 11, that is, when the input logical value is the “L” level and the output logical value is the “L” level, the output signal of the EXNOR circuit 13 is “H”. Become a level. When the input logical value is “H” level and the output logical value is “H” level,
The output signal of the EXNOR circuit 13 becomes "H" level.

When the input data DIN changes with respect to the data Q of the circuit 11, that is, when the input logical value is "L" level and the output logical value is "H" level,
The output of the EXNOR circuit 13 becomes "L" level. When the input logical value is "H" level and the output logical value is "L" level, the output signal of EXNOR circuit 13 is "L" level.

Reference numeral 14 designates p which inputs the output signal of the EXNOR circuit 13 and controls the power supply to the flip-flop circuit 11.
It is a channel MOSFET and is an example of a power supply control circuit. The source of the MOSFET 14 is connected to the power supply line VDD, and the drain thereof is connected to the internal power supply line of the flip-flop circuit 11. MOSFET 14 is circuit 11
When the input logical value and the output logical value are the same, they are turned off and the power supply to the flip-flop circuit 11 is cut off. On the contrary, the MOSFET 14 is turned on when the input logical value and the output logical value of the circuit 11 are different from each other to supply power to the flip-flop circuit 11. Reference numeral 15 is an output buffer that amplifies the output data of the flip-flop circuit 11, and is an example of an amplifier circuit. The output buffer 15 is connected to enhance the driving capability of the circuit 11.

In FIG. 2, reference numeral 101 is a master latch circuit composed of transfer gates TG11, TG12 and inverters INV11 and INV12, which inverts and holds data DIN based on CK and CKx signals. The inverters INV11 and INV12 are connected between the internal power supply line and the ground line GND, and the internal power supply line is connected to the drain of the above MOSFET 14. 102 is a transfer gate TG
A slave latch circuit composed of 21, TG22 and inverters INV21 and INV22, which inverts and holds the output data of the latch circuit 101 based on the CK signal and the CKx signal.

Reference numeral 103 designates a non-inverted CK0 signal and an inverted CKx signal for the master latch circuit 101 and the slave latch circuit 10.
It is a clock distribution circuit that outputs to 2. The clock distribution circuit 103 includes an inverter INV31 that inputs a CK signal and outputs an inverted CKx signal, and an inverter INV32 that inputs an inverted CKx signal and outputs a non-inverted CK0 signal. Unlike the conventional example, the inverters INV31 and INV32 are connected between the internal power supply line and the ground line GND.

Next, the operation of the semiconductor integrated circuit of this embodiment will be described. First, when the CK signal is supplied to the flip-flop circuit 11 while the MOSFET 14 is on, the clock distribution circuit 103 outputs the non-inverted CK0 signal and the inverted CKx signal to the master latch circuit 101 and the slave latch circuit 102. To do. In this state, input data DIN
However, for example, when it becomes the "L" level, the data DIN is held in the flip-flop circuit 11 in synchronization with the CK signal.

At this time, when the transfer gates TG11 and TG12 of the master latch circuit 101 are turned on in synchronization with the non-inverted CK0 signal and the inverted CKx signal, the inverter I
The data DIN is inverted and held by NV11 and INV12. Further, the transfer gates TG21 and TG22 of the slave latch circuit 102 have the non-inverted CK0 signal and the inverted CKx signal.
When it is turned on in synchronization with the signal, the inverters INV21 and INV2
2 inverts and holds the output data (“H” level) of the master latch circuit 101. As a result, the output data Q of the slave latch circuit 102 becomes "L" level.

The output logical value of the slave latch circuit 102 = “L” level is held by the latch circuit 12.
The output logical value of this latch circuit = “L” level is E
Flip-flop circuit 11 by XNOR circuit 13
Input logical value = “L” level. At this time, since the input logical value and the output logical value of the flip-flop circuit 11 become the same, the EXNOR circuit 13 outputs the MO signal.
An “H” level signal is output to the gate of the SFET 14.

Then, when the signal = “H” level is input, M
The OSFET 14 is turned off, and the flip-flop circuit 1
Turn off power to 1. As a result, the power supply line VDD is disconnected from the internal power supply line, and the power consumption in the flip-flop circuit 11 becomes zero. Also, when the input to the flip-flop circuit 11 changes from “L” to “H” level after the data waiting period or the like, the output logical value “L” level of the latch circuit 12 is flipped by the EXNOR circuit 13. The input logical value of the flop circuit 11 is compared with the “H” level. At this time, since the input logical value and the output logical value of the flip-flop circuit 11 are different, EXN
An “L” level signal is output from the OR circuit 13 to the gate of the MOSFET 14.

Then, when the signal = “L” level is input, M
The OSFET 14 is turned on, and the flip-flop circuit 1
Supply power to 1. As a result, since the power supply line VDD and the internal power supply line are connected, the clock distribution circuit 103 which receives the CK signal outputs the non-inverted CK0 signal and the inverted CKx signal to the master latch circuit 101 and the slave latch circuit 102. In this state, the flip-flop circuit 1 synchronizes the input data DIN fixed to the “H” level with the CK signal.
Hold at 1.

At this time, the non-inverted CK0 signal and the inverted CK
The data DIN = “H” level is inverted and held by the master latch circuit 101 in synchronization with the x signal, and the master latch circuit 10 is held by the slave latch circuit 102.
The output data of 1 is inverted and held. The output logical value of the slave latch circuit 102 = “H” level is held by the latch circuit 12. The output logical value = “H” level of the latch circuit 12 is compared with the input logical value = “H” level of the flip-flop circuit 11 by the EXNOR circuit 13. At this time, since the input logical value and the output logical value of the flip-flop circuit 11 become the same, E
An "L" level signal is output from the XNOR circuit 13 to the gate of the MOSFET 14.

Then, the signal = M to which the "L" level is input
The OSFET 14 is turned off, and the flip-flop circuit 1
Turn off power to 1. As a result, the power supply line VDD is disconnected from the internal power supply line, and the power consumption in the flip-flop circuit 11 becomes zero. Thus, the first aspect of the present invention
According to the semiconductor integrated circuit of the embodiment, as shown in FIG. 1, since the EXNOR circuit 13 compares the input logical value and the output logical value of the flip-flop circuit 11, the output of the flip-flop circuit 11 When the input data DIN does not change with respect to the data Q, the MOSFET
14 will turn off.

Therefore, when the data DIN does not change, the MOSFET 14 disconnects the internal power supply line of the flip-flop circuit 11 from the power supply line VDD, so that the master latch circuit 101 and the slave latch circuit 102 are waiting for data.
And the power consumption in the clock distribution circuit 103 can be reduced to zero.
In particular, even if the CK signal is input to the clock distribution circuit 103, the power supply to the circuit 103 is stopped, so that the through currents in the inverters INV31 and INV32 as in the conventional example are eliminated and the power consumption becomes zero.

When the input data DIN changes with respect to the output data Q of the flip-flop circuit 11,
Since the MOSFET 14 inputting the "L" level is turned on to connect the internal power supply line of the flip-flop circuit 11 and the power supply line VDD, the data is rewritten in the master latch circuit 101 and the slave latch circuit 102. As described above, since no electric power is consumed in the flip-flop circuit while waiting for data input, it is possible to prolong the battery drive time of a portable electronic device or the like incorporating this circuit 11.

(2) Description of Second Embodiment FIG. 3 is a block diagram of a semiconductor integrated circuit according to a second embodiment of the present invention. In the second embodiment, unlike the first embodiment, the output data DOU of the flip-flop circuit 11 is
The supply of the CK signal is controlled according to the change of the input data DIN with respect to T (Q).

In FIG. 3, reference numeral 21 is a flip-flop circuit, which comprises a master latch circuit 201, a slave latch circuit 202 and a clock distribution circuit 203. Each circuit 20
1, 202 and 203 are different from the first embodiment in that the power supply line VDD
And ground line GND. Reference numeral 22 is a two-input exclusive OR circuit (hereinafter referred to as an EXOR circuit) for comparing the output logical value of the slave latch circuit 202 and the input logical value to the flip-flop circuit 21, which is another example of the comparison circuit.

For example, when the input data DIN for the data Q of the circuit 21 does not change, that is, when the input logical value is "L" level and the output logical value is "L" level,
The output signal of the EXOR circuit 22 becomes "L" level. Further, when the input logical value is "H" level and the output logical value is "H" level, the output signal of EXNOR circuit 13 becomes "" L "level.

When the input data DIN for the data Q is changing and the input logical value is "L" level and the output logical value is "H" level, the output of the EXNOR circuit 13 becomes "H" level. . The input logical value is "H".
EXN when the output logical value is "L" level
The output signal of the OR circuit 13 becomes "H" level. A clock distribution circuit 23 receives the output signal of the EXOR circuit 22
A clock control circuit for controlling input of a CK signal to 203. The control circuit 23 is an n-type field effect transistor TN1.
And TN2 and an inverter INV. The gate of the transistor TN1 is connected to the output of the EXOR circuit 22, its drain is connected to the supply point of the CK signal, and its source is connected to the input part of the clock distribution circuit 203. The gate of the transistor TN2 is connected to the output of the EXOR circuit 22 via the inverter INV, the drain thereof is connected to the source of the transistor TN2, and the source thereof is connected to the ground line GND. The inverter INV of the control circuit 23 is connected between the power supply line VDD and the ground line GND.

The control circuit 23 is the flip-flop circuit 2
When the input logical value and the output logical value of 1 are the same, the circuit is turned off, the CK signal to the clock distribution circuit 203 is cut off, and the circuit 20
Connect the input part of 3 to the ground line GND and fix it to "L" level. On the contrary, the control circuit 23 is the flip-flop circuit 2
When the input logical value and the output logical value of 1 are different from each other, it is turned on to connect the input portion of the circuit 203 to the ground line GND. Other configurations and those having the same names as those in the first embodiment have the same functions, and therefore their explanations are omitted.

Next, the operation of the semiconductor integrated circuit of this embodiment will be described. First, the transistor TN1 turns on and TN2
When the CK signal is supplied to the flip-flop circuit 21 in the state where the switch is off, the clock distribution circuit 203 outputs the non-inverted CK0 signal and the inverted CKx signal to the master latch circuit.
Output to 201 and slave latch circuit 202. In this state, when the input data DIN becomes, for example, “H” level (determined), the data DIN is held in the flip-flop circuit 21 in synchronization with the CK signal.

At this time, the master latch circuit 201 synchronizes the data DIN with the non-inverted CK0 signal and the inverted CKx signal.
Invert and hold. Further, the slave latch circuit 202 inverts and holds the output data of the master latch circuit 201 in synchronization with the non-inverted CK0 signal and the inverted CKx signal. As a result, the output data Q of the slave latch circuit 202 becomes "H" level.

The output logical value of the slave latch circuit 202 = “H” level is flipped by the EXOR circuit 22.
The input logical value of the flop circuit 21 is compared with "H" level. At this time, since the input logical value and the output logical value of the flip-flop circuit 21 become the same, the EXOR circuit 22 outputs an "L" level signal to the gate of the transistor TN1.

Then, the transistor TN1 to which the signal = “L” level is input is turned off, the supply of the CK signal to the clock distribution circuit 203 is cut off, and the clock input is fixed to the “L” level. As a result, the inverted C of the clock distribution circuit 203
Since the Kx signal is fixed to the “H” level and the non-inverted CK signal is fixed to the “L” level, the master latch circuit 20
1 retains the "L" level data, and the slave latch circuit 202 retains the "H" level data.

When the input to the flip-flop circuit 21 changes from "H" to "L" level after the data waiting period, etc., the EXOR circuit 22 outputs the output logical value of the flip-flop circuit 21 = The “H” level and the input logical value = “L” level are compared. At this time,
Since the input logical value and the output logical value of the flip-flop circuit 21 are different, the EXOR circuit 22 causes the transistor T
An "H" level signal is output to the gate of N1.

Then, the transistor TN1 to which the signal = “H” level is input is turned on to supply the CK signal to the clock distribution circuit 203. As a result, the clock distribution circuit 203 that receives the CK signal receives the non-inverted CK0 signal and the inverted CKx signal.
Signal to master latch circuit 201 and slave latch circuit
Output to 202. As a result, the flip-flop circuit 21 rewrites the data DIN from "H" to "L" level.

As described above, according to the semiconductor integrated circuit of the second embodiment of the present invention, the EXOR circuit 22 compares the input logical value and the output logical value of the flip-flop circuit 21, and thus the flip-flop circuit 21 flips. When the input data does not change with respect to the output data of the flop circuit 21,
The transistor TN1 of the clock control circuit 22 is turned off.

Therefore, when the data DIN does not change, the transistor TN1 outputs the CK to the clock distribution circuit 203.
Since the supply of the signal is cut off and the input of the clock distribution circuit 203 is fixed to the "L" level, unlike the first embodiment, the clock distribution circuit 203 in the data standby state transfers to the master latch circuit 201 and the slave latch circuit 202. Since the inverted CK signal fixed to the “H” level and the non-inverted CK signal fixed to the “L” level are output, the master latch circuit 20
1 retains the "L" level data, and the slave latch circuit 202 retains the "H" level data.

As a result, the power consumption of the flip-flop circuit 21 cannot be reduced to zero as in the first embodiment, but since the CK signal is not input to the clock distribution circuit 103, it is different from the conventional example. Through current in the inverter is eliminated, and the power consumption of the circuit 21 can be reduced. When the input data DIN changes with respect to the output data Q of the flip-flop circuit 21, the transistor TN1 to which the “H” level is input is turned on and the clock distribution circuit 203.
Since the CK signal is input to the master latch circuit 101 and the slave latch circuit 102, the data is rewritten.

Further, as compared with the first embodiment, the flip
Since the output logical value is fixed to the “H” or “L” level by the slave latch circuit 202 of the flop circuit 21,
The latch circuit 12 for stabilizing the output logical value of the flip-flop circuit 11 as in the first embodiment can be omitted. (3) Description of Third Embodiment FIG. 4 is a configuration diagram of a semiconductor integrated circuit according to a third embodiment of the present invention. Unlike the first embodiment, the third embodiment is provided with a memory array for holding data,
For example, the power supply to the memory array is controlled by comparing three input data and three output data.

In FIG. 4, reference numeral 31 is a memory array for storing three input data D1 to D3 based on the CK signal. For example, nine flip-flop circuits FF11 to FF11.
It is composed of FF31, FF12 to FF32, and FF13 to FF33. These circuits FF11-FF31, FF12-FF32, FF13-F
F33 is connected to the internal power supply line dedicated to the flip-flop circuit.

32 is the three data Q of the memory array 31.
The output unit holds the output logical values of 1 to Q3, and includes the latch circuit 12 and the output buffer 15 as in the first embodiment. Reference numeral 33 compares 6 output logical values of the memory array 31 held by the latch circuit 12 with input logical values of 3 data D1 to D3 to the memory array 31.
The input EXNOR circuit is an example of a comparison circuit. 6
The input EXNOR circuit may be composed of three 2-input AND circuits and one 2-input EXNOR circuit. For example, 6
The input EXNOR circuit 33 outputs an "H" level signal when the input data D1 to D3 corresponding to the data Q1 to Q3 of the memory array 31 does not change. Also, EX
The NOR circuit 33 outputs an "L" level signal when the input data D1 to D3 corresponding to the data Q1 to Q3 changes.

Reference numeral 34 is an input of the output signal of the EXNOR circuit 33. When the input logical value and the output logical value of the memory array 31 are the same, the power supply to the memory array 31 is cut off, and the input logical value and the output logical value of the memory array 31 are turned off. , And a MO for power supply control that supplies power to the memory array 31
It is an SFET. The source of the MOSFET is connected to the power supply line VDD and its drain is connected to the internal power supply line. Other configurations and those having the same names as those in the first embodiment have the same functions, and therefore their explanations are omitted.

Next, the operation of the semiconductor integrated circuit of this embodiment will be described. First, when the three input data D1 to D3 are determined while the CK signal is being supplied to the memory array 31, the three data D1 to D3 are stored in the memory array 31 in synchronization with the CK signal. 31 of 3
The output logical values of the data Q1 to Q3 are held by the output unit 32. The output logical values of the three data Q1 to Q3 of the memory array 31 held by the output unit 32 are set to 3 by the EXNOR circuit 33.
It is compared with the input logical value of one data D1 to D3. Then, the MO to which the output signal of the EXNOR circuit 33 is input.
The SFET 34 is the three data Q1 of the memory array 31.
When the input logical value of Q3 to the output logical value of the three data D1 to D3 are the same, the power supply to the memory array 31 is cut off. In addition, the three data Q1 to Q3 of the memory array 31 are
When the input logical value of 3 is different from the output logical value of the three data D1 to D3, the MOSFET 34 operates in the memory array 3
Supply power to 1.

In this way, according to the semiconductor integrated circuit of the third embodiment of the present invention, the EXNOR circuit 33 causes the input logical values of the three data D1 to D3 of the memory array 31 and the three data Q1 to Q3. Of the memory array 31, the three output data of the memory array 31 are not changed.
Since the MOSFET 34 disconnects the memory array 31 from the power supply, nine flip
Flop circuit FF11 to FF31, FF12 to FF32, FF13
The power consumption of FF33 can be reduced to zero.

Output data Q1 of the memory array 31
When any one of the input data D1 to D3 changes with respect to Q3, the MOSFE inputting the "L" level
Since T34 is turned on to connect the memory array 31 to the power supply line VDD, the flip-flop circuits FF11 to FF31,
Data is rewritten in FF12 to FF32 and FF13 to FF33.

As described above, the nine flip-flop circuits FF11 to FF31 and FF12 to F are on standby for data input.
Since no power is consumed in F32 and FF13 to FF33, it is possible to extend the battery drive time of a portable electronic device or the like having the memory array 31 built therein. (4) Description of Fourth Embodiment FIG. 5 shows a configuration diagram of a semiconductor integrated circuit according to a fourth embodiment of the present invention. In the fourth embodiment, unlike the first to third embodiments, a memory array for holding data is provided, and, for example, three input data and three output data are compared, and the data is stored in the memory array. It controls the supply of the clock signal.

In FIG. 5, reference numeral 41 is a memory array for storing three data D1 to D3 based on the CK signal, and for example, nine flip-flop circuits FF11 to F.
It is composed of F31, FF12 to FF32, and FF13 to FF33. These circuits FF11-FF31, FF12-FF32, FF13-FF
33 is connected between the power supply line VDD and the ground line GND.
An output unit 42 amplifies the output data Q1 to Q3 of the memory array 41, and the latch circuit 1 as in the first embodiment.
2 is not provided.

43 is the three data Q of the memory array 41.
6-input EXO for comparing output logical values of 1 to Q3 with input logical values of three data D1 to D3 to the memory array 41
The R circuit is another example of the comparison circuit. For example, 6
The input EXOR circuit 43 may be composed of three 2-input AND circuits and one 2-input EXOR circuit. The 6-input EXOR circuit 43 includes the data Q1 to Q1 of the memory array 41.
When the input data D1 to D3 for Q3 does not change, an "L" level signal is output. Further, the EXOR circuit 43 inputs the input data D1 to the data Q1 to Q3.
When D3 changes, a "H" level signal is output.

Reference numeral 44 denotes the CK to the memory array 41 when the output signal of the EXNOR circuit 43 is input and the input logical values of the three data Q1 to Q3 of the memory array 41 and the output logical values of the three data D1 to D3 are the same. Cut off the signal and flip-flop circuits FF11-FF31, FF12-FF3
2, a clock control circuit for fixing the clock inputs of FF13 to FF33 to the "L" level. On the contrary, the clock control circuit 44 controls the three data Q1 to Q3 of the memory array 41.
When the input logical value of 3 is different from the output logical value of the three data D1 to D3, the CK signal is input to the memory array 41. Other configurations and those having the same names as those in the first embodiment have the same functions, and therefore their explanations are omitted.

Next, the operation of the semiconductor integrated circuit of this embodiment will be described. First, similarly to the third embodiment, while the CK signal is being supplied to the memory array 41, the input data D
When 1 to D3 are determined, three data are stored in the memory array 41 in synchronization with the CK signal. And EXOR
The circuit 43 compares the three input logic values of the memory array 41 with the three output logic values. The clock control circuit 44, to which the output signal of the EXOR circuit 43 is input, cuts off the CK signal to the memory array 41 when the three input logical values of the memory array 41 and the three output logical values are the same, and The clock input is fixed at "L" level. When the three input logical values and the three output logical values of the memory array 41 are different, the clock control circuit 4
4 inputs the CK signal to the memory array 41.

In this way, according to the semiconductor integrated circuit of the fourth embodiment of the present invention, the EXOR circuit 43 compares the three input logical values of the memory array 41 with the three output logical values. , Three input data D1 to D3 for three output data Q1 to Q3 of the memory array 41
When 3 does not change, the clock control circuit 44 cuts off the CK signal to the memory array 41 and fixes the clock input of the memory array 41 to the “L” level, so that the first, second and third embodiments are performed. Unlike the above, it is possible to reduce the power consumption of the memory array 41 during the data standby. Since the output logic value of the memory array 41 is stable as compared with the third embodiment, the latch circuit 12 for holding the output logic value of the memory array 41 can be omitted.

(5) Description of Fifth Embodiment FIG. 6 is a block diagram of a semiconductor integrated circuit according to a fifth embodiment of the present invention. In the fifth embodiment, four semiconductor integrated circuits of the third embodiment are combined and the power supply to the memory array 41 is controlled for each circuit block. FIG.
In the figure, B1 to B3 are circuit blocks, which are composed of the semiconductor integrated circuit according to the third embodiment. Circuit block B1
Holds the three data D11 to D13 based on the CK signal, the circuit block B2 holds the output data of the circuit block B1 based on the CK signal, and the three data Q11 to Q13.
Is output. The circuit block B3 holds three data D21 to D23 based on the CK signal, and the circuit block B3
Reference numeral 4 holds the output data of the circuit block B3 based on the CK signal, and outputs three data Q21 to Q23. Other configurations and those having the same names as those in the third embodiment have the same functions, and therefore their explanations are omitted.

Next, the operation of the semiconductor integrated circuit of this embodiment will be described. On the other hand, on the other hand, similarly to the third embodiment, when the input data D11 to D13 are determined while the CK signal is supplied to the memory array 31 of the circuit block B1, C
Memory array 3 in which three pieces of data are B1 in synchronization with the K signal
1 is stored. Then, the EXNOR circuit 33 of B1 compares the three input logical values of the memory array 31 of B1 with the three output logical values. The MOSFET 34 to which the output signal of the EXNOR circuit 33 is input turns off the power supply to the B1 memory array 31 when the three input logical values of the B1 memory array 31 and the three output logical values are the same. When the three input logical values and the three output logical values of the memory array 31 of B1 are different, the MOSFET 34
Supplies power to the memory array 31.

Further, when the output data of the circuit block B2 is determined in the state where the CK signal is supplied to the memory array 31 of the circuit block B2, 3 is synchronized with the CK signal.
One data is stored in the memory array 31 of B2. Then, the EXNOR circuit 33 of B2 compares the three input logical values and the three output logical values of the memory array 31 of B2. MO to which the output signal of the EXNOR circuit 33 is input
The SFET 34 turns off the power supply to the memory array 31 of B2 when the three input logical values and the three output logical values of the memory array 31 of B2 are the same. Further, when the three input logical values and the three output logical values of the memory array 31 of B2 are different, the MOSFET 34 operates as the memory array 31.
Supply power to

On the other hand, similarly to the third embodiment, when the input data D21 to D23 are determined with the CK signal being supplied to the memory array 31 of the circuit block B3, the CK
Memory array 31 in which three pieces of data are B3 in synchronization with signals
Is stored. Then, the EXNOR circuit 33 of B3 is
The three input logic values and the three output logic values of the three memory arrays 31 are compared. The MOSFET 34 to which the output signal of the EXNOR circuit 33 is input turns off the power supply to the B3 memory array 31 when the three input logical values of the B3 memory array 31 and the three output logical values are the same. When the three input logical values and the three output logical values of the memory array 31 of B3 are different, the MOSFET 34
Supplies power to the memory array 31.

Further, when the output data of the circuit block B3 is determined in the state where the CK signal is supplied to the memory array 31 of the circuit block B4, 3 is output in synchronization with the CK signal.
One data is stored in the memory array 31 of B4. Then, the EXNOR circuit 33 of B4 compares the three input logical values of the memory array 31 of B4 with the three output logical values. MO to which the output signal of the EXNOR circuit 33 is input
The SFET 34 turns off the power supply to the memory array 31 of B4 when the three input logical values and the three output logical values of the memory array 31 of B4 are the same. Further, when the three input logical values and the three output logical values of the memory array 31 of B4 are different, the MOSFET 34 supplies power to the memory array 31.

In this way, according to the semiconductor integrated circuit of the fifth embodiment of the present invention, each of the circuit blocks B1 to B
The EXNOR circuit 33 of 4 allows 3 of the memory array 31.
Since one input logical value and three output logical values are compared for each block, the three output data Q of the memory array 31 are compared.
When the three input data D1 to D3 do not change for 1 to Q3, the MOSFET 34 of each circuit block is
Since the power supply to the memory array 31 is cut off for each block, unlike the first, second, third and fourth embodiments,
The power consumption of the memory array 31 during data standby can be reduced to zero for each circuit block.

(6) Description of Sixth Embodiment FIG. 7 is a block diagram of a semiconductor integrated circuit according to the sixth embodiment of the present invention. In the sixth embodiment, four semiconductor integrated circuits of the fourth embodiment are combined and the supply of the clock signal to the memory array 41 is controlled for each circuit block. In FIG. 7, B1 to B3 are circuit blocks, which are composed of the semiconductor integrated circuit according to the fourth embodiment. The circuit block B1 receives three data D11 based on the CK signal.
To D13 are held, and the circuit block B2 is the circuit block B1.
The output data of the above is held based on the CK signal, and three data Q11 to Q13 are output. The circuit block B3 is C
Based on the K signal, the three data D21 to D23 are held, and the circuit block B4 outputs the output data of the circuit block B3 to CK.
It holds based on the signal and outputs three data Q21 to Q23. The other configurations and those having the same names as those in the fourth embodiment have the same functions, and thus the description thereof will be omitted.

Next, the operation of the semiconductor integrated circuit of this embodiment will be described. On the other hand, on the other hand, similarly to the fourth embodiment, when the input data D11 to D13 are determined in the state where the CK signal is supplied to the memory array 41 of the circuit block B1, C
Memory array 4 in which three pieces of data are B1 in synchronization with the K signal
1 is stored. Then, the EXOR circuit 43 of B1 is B
The three input logical values and the three output logical values of one memory array 41 are compared. The clock control circuit 44, to which the output signal of the EXOR circuit 43 is input, cuts off the CK signal to the memory array 41 of B1 when the three input logical values and the three output logical values of the memory array 41 of B1 are the same, The clock input of the memory array is fixed at "L" level. When the three input logical values and the three output logical values of the memory array 41 of B1 are different, the clock control circuit 44 inputs the CK signal to the memory array 41.

Further, when the output data of the circuit block B2 is determined in the state where the CK signal is supplied to the memory array 41 of the circuit block B2, the 3 data is synchronized with the CK signal.
One data is stored in the memory array 41 of B2. Then, the EXOR circuit 43 of B2 is connected to the memory array 4 of B2.
The three input logic values of 1 and the three output logic values are compared. The clock control circuit 44, to which the output signal of the EXOR circuit 43 is input, cuts off the CK signal to the memory array 41 of B2 when the three input logical values of the memory array 41 of B2 and the three output logical values are the same, The clock input of the memory array is fixed at "L" level. Also, B
When the three input logical values and the three output logical values of the second memory array 41 are different, the clock control circuit 44 inputs the CK signal to the memory array 41.

On the other hand, similarly to the fourth embodiment, when the input data D21 to D23 are determined with the CK signal being supplied to the memory array 41 of the circuit block B3,
Three pieces of data are stored in the memory array 41 of B3 in synchronization with the CK signal. Then, the EXOR circuit 43 of B3 compares the three input logical values of the memory array 41 of B3 with the three output logical values. The clock control circuit 44 to which the output signal of the EXOR circuit 43 is input cuts off the CK signal to the memory array 41 of B3 when the three input logical values of the memory array 41 of B3 and the three output logical values are the same, The clock input of the memory array is fixed at "L" level. Further, when the three input logical values and the three output logical values of the memory array 41 of B3 are different, the clock control circuit 44 inputs the CK signal to the memory array 41.

Further, when the output data of the circuit block B3 is determined in the state where the CK signal is supplied to the memory array 41 of the circuit block B4, 3 is synchronized with the CK signal.
One data is stored in the memory array 41 of B4. Then, the EXOR circuit 43 of B4 is connected to the memory array 4 of B4.
The three input logic values of 1 and the three output logic values are compared. The clock control circuit 44, to which the output signal of the EXOR circuit 43 is input, cuts off the CK signal to the B4 memory array 41 when the three input logical values of the B4 memory array 41 and the three output logical values are the same, The clock input of the memory array is fixed at "L" level. Also, B
When the three input logical values and the three output logical values of the four memory array 41 are different, the clock control circuit 44 inputs the CK signal to the memory array 41.

In this way, according to the semiconductor integrated circuit of the sixth embodiment of the present invention, each of the circuit blocks B1 to B
Since the EXOR circuit 43 of 4 compares the three input logical values of the memory array 41 with the three output logical values of each block, the three output data Q1 of the memory array 41 are compared.
To Q3, when the three input data D1 to D3 do not change, the clock control circuit 44 of each circuit block
Cuts off the CK signal to the memory array 41 and fixes the clock input of the memory array 41 to the “L” level. Therefore, unlike the first, second, third, fourth and fifth embodiments, The power consumption of the memory array 41 in the standby state can be reduced in circuit block units.

[0073]

As described above, according to the semiconductor integrated circuit of the present invention, since the comparator circuit compares the output logical value of the memory circuit with the input logical value, the output logical value of the memory circuit is input. When the logic value does not change, the power supply control circuit disconnects the storage circuit from the power supply, so that the power consumption of the standby storage circuit becomes zero.

According to another semiconductor integrated circuit of the present invention, since the comparison circuit compares the output logical value of the memory circuit with the input logical value, when the input logical value does not change with respect to the output logical value of the memory circuit. Since the clock control circuit cuts off the supply of the clock signal to the memory circuit and fixes the clock input of the memory circuit to a constant potential, the power consumption of the memory circuit in standby can be reduced.

According to another semiconductor integrated circuit of the present invention, since the comparison circuit compares a plurality of input logical values of the memory array with a plurality of output logical values, a plurality of input logical values are output for the plurality of output logical values. When the value does not change, the power supply control circuit disconnects the memory array from the power supply, so that the power consumption of the standby memory array can be reduced to zero. According to another semiconductor integrated circuit of the present invention, since the comparison circuit compares a plurality of input logical values of the memory array with a plurality of output logical values, the plurality of input logical values change with respect to the plurality of output logical values. If not, the clock control circuit cuts off the clock signal to the memory array and fixes the clock input of the memory array to a constant potential, so that the power consumption of the memory array in standby can be reduced.

When these semiconductor integrated circuits are combined, the storage circuit and the memory array can be suspended for each circuit block, and the power consumption can be reduced for each circuit block. This greatly contributes to lower power consumption of portable electronic devices and the like having the semiconductor integrated circuit as in the present invention built therein.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is an internal configuration diagram of a flip-flop circuit according to each embodiment of the present invention.

FIG. 3 is a configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 5 is a configuration diagram of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 6 is a configuration diagram of a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 7 is a configuration diagram of a semiconductor integrated circuit according to a sixth embodiment of the present invention.

FIG. 8 is a configuration diagram of a flip-flop circuit according to a conventional example.

[Explanation of symbols]

10, 11, 21, FF11 to FF13, FF21 to FF23,
FF31 to FF33 ... D-type flip-flop circuit (memory circuit), 12 ... Latch circuit (output circuit), 13, 33 ...
EXNOR circuit (comparison circuit), 14, 34 ... P-type field effect transistors (power supply control circuit), 15 ... Output buffer (output circuit), 22, 43 ... EXOR circuit (comparison circuit), 23, 44 ... Clock control circuit , 31, 41 ... Memory array, 32, 42 ... Output section, 1, 101, 201 ... Master latch circuit, 2, 102, 202 ... Slave latch circuit, 3, 103, 203 ... Clock distribution circuit, INV1, INV
2, INV11, INV12, INV21, INV32, INV31, INV32
Inverter, TG11, TG12, TG21, TG22 ... Transfer gate, B1 to B4 ... Circuit block.

Claims (5)

[Claims] 1. A storage circuit that stores data based on a clock signal, an output circuit that holds an output logic value of the storage circuit, an output logic value of the storage circuit held by the output circuit, and the storage circuit. When the input logic value of the storage circuit is the same as that of the comparison circuit for comparing the input logic value of the storage circuit and the output signal of the comparison circuit, the power supply to the storage circuit is cut off, and the storage circuit of the storage circuit is turned off. A semiconductor integrated circuit comprising: a power supply control circuit that supplies power to the storage circuit when the input logical value and the output logical value are different. 2. A memory circuit for storing data based on a clock signal, a comparator circuit for comparing an output logical value of the memory circuit with an input logical value of the memory circuit, and an input signal of the comparator circuit. When the input logical value and the output logical value of the memory circuit are the same, the clock signal to the memory circuit is cut off to fix the clock input of the memory circuit to a constant potential, and the input logical value and the output logical value of the memory circuit are fixed. And a clock control circuit for inputting a clock signal to the memory circuit. 3. A memory array for storing a plurality of data based on a clock signal, an output circuit for holding a plurality of output logical values of the memory array, and a plurality of outputs of the memory array held by the output circuit. A comparator circuit for comparing a logical value with a plurality of input logical values of the memory array, and an output signal of the comparing circuit is input, and when the input logical value and the output logical value of the memory array are the same, A semiconductor integrated circuit comprising a power supply control circuit that supplies power to the memory array when the power supply is turned off and the input logical value and the output logical value of the memory array are different. 4. A memory array that stores a plurality of data based on a clock signal, a comparison circuit that compares a plurality of output logical values of the memory array with a plurality of input logical values of the memory array, and the comparison circuit. When the input logical value and the output logical value of the memory array are the same, the clock signal to the memory array is cut off, and when the input logical value and the output logical value of the memory array are different, the memory array And a clock control circuit for inputting a clock signal to the semiconductor integrated circuit. 5. The semiconductor integrated device according to claim 1, further comprising an amplifier circuit for amplifying output data of the storage circuit or the memory array. circuit.