JPH098553A - Frequency converter - Google Patents

Abstract

PURPOSE: To constitute a frequency converter by a digital circuit to obtain a stable characteristic with a little change. CONSTITUTION: This converter is provided with a zero interpolation device 301 performing a frequency conversion by performing a zero interpolation for the signal of a low speed sampling frequency by using a switch and a band pass filter 302 taking out the necessary frequency component from the signal for which a sampling frequency conversion is performed by this zero interpolation device 301. The band pass filter 302 is divided into a numerator part 302 and a denominator part 304 and each part is composed of delay circuits 305 to 309, 312, 313 and adders 310 and 311. A multistage connection may be performed for the band filter, the band pass filter may be arranged before and after the zero interpolation device, and a pipeline processing may be performed for the band pass filter of the poststage for performing a high speed operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency converter for converting the frequency of a transmitted signal from a low frequency to a high frequency in a transmitter.

[0002]

2. Description of the Related Art FIG. 14 shows an example of a conventional frequency converter of this type. In FIG. 14, an input signal 1401 having a low sampling frequency (f ₁ Hz) digitally obtained by a DSP (digital signal processor) or the like is converted into an analog signal 1403 by a D / A (digital / analog) converter 1402, and a return signal is generated. Is removed by a bandpass filter 1404, and its analog signal 1405
In the mixer 1407, a sine wave having a frequency f ₂ Hz is multiplied. At this time, the frequency becomes (f ₁ + f ₂ ) Hz.

[0003] Thus, in the above conventional frequency conversion device, the input signal of the frequency f ₁ Hz using an analog mixer and the frequency f ₁ Hz sine wave oscillator (f ₁ + f ₂₎ H
can be converted to z.

[0004]

However, in the above-mentioned conventional frequency conversion device, since the device is constituted by an analog circuit, there is a problem that the characteristics change due to temperature change or aging change.

The present invention solves such a conventional problem, and an object thereof is to provide a frequency converter capable of obtaining stable characteristics with little change.

[0006]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention is a device in which a device is constituted by a digital circuit, and a 0-interpolation interpolation is performed on a signal of a low sampling frequency by using a switch. A zero interpolation interpolator for performing frequency conversion by means of and a bandpass filter for extracting a required frequency component from the frequency-converted signal are provided.

[0007]

Therefore, according to the present invention, by realizing the frequency conversion device with the digital circuit of the 0-interpolation interpolator and the bandpass filter, a frequency conversion device with stable characteristics that is resistant to temperature changes and aging changes is provided. Can be realized. In addition, since the device is realized by a digital circuit, there is an effect that it is easy to achieve one chip with the modulator.

[0008]

【Example】

 (Embodiment 1) FIG. 1 shows the frequency in the first embodiment of the present invention.
FIG. 2 shows the configuration of the number conversion device, and FIG.
The principle of conversion is shown. First, referring to FIG.
The operating principle will be described. In FIG. 2, the input signal
The sampling frequency is f₁, The sampling time interval is T
₁(= 1 / f₁) And the center frequency is f₁/ 4
You. This signal is multiplied by L frequency (sampling frequency L *
f₁, Center frequency L * f ₁Frequency conversion to / 4)
U. In FIG. 2, L = 5.

[0009] In this frequency converter, the center frequency f _1/4 with a sampling frequency f ₁ as shown in FIG. 2 (a)
The modulated wave of is input. First, 0 interpolation is performed in order to increase the sampling frequency of this signal to L times. Zero interpolation is one of the methods of increasing the sampling frequency from low speed to high speed. When the sampling frequency is increased to L times, the value of the low sampling frequency is (L−
1) It is a method of setting 0 times. By performing the 0 interpolation, the frequency spreads as shown in FIG. Then, the frequency as shown in FIG. 2 (c) the signal of frequency L * f _1/4 in this - taking out a band-pass filter having an amplitude characteristic. The taken out result is as shown in FIG.

[0010] Thus, the input signal (sampling frequency f _1, the center frequency f _1/4) to L times the frequency (sampling frequency L * f _1, the center frequency L * f _1/4)
The frequency can be converted to.

Next, a frequency converter for performing the above operation will be described with reference to FIG. In FIG. 1, 10
1 is a 0 interpolation interpolator using a switch, 102 is a bandpass filter, 103 is an input signal, 104 is a signal obtained by multiplying the sampling frequency by L, and 105 is an output signal after frequency conversion.

[0012] Of the frequency conversion device configured as described above
The operation will be described. The 0 interpolation interpolator 101 is a high-speed
Once the sampling frequency is connected to the a side, the input signal 10
3 is taken in, and (L-1) times is joined to the b side and 0 is taken
Put in. Timing control is f ₁CLK0 repeated at Hz
Perform in. CLK0 H level and L level duty
Is 1: (L-1) or (L-1): 1. 0 interpolation
A signal in which the sampling frequency is set to L times by the interpolator 101
The signal 104 is input to the bandpass filter 102.
The bandpass filter 102 has L * f₁Hz CLK
Since 1 is input, the center frequency L * f₁Out of / 4
The force signal 105 is taken out. In this way, the input signal
No. (sampling frequency f₁, Center frequency f₁/ 4)
L times frequency (sampling frequency L * f₁, Center frequency
Number L * f₁The frequency can be converted to / 4).

As described above, the present embodiment has the following effects. (1) Since the frequency conversion device is configured by the digital circuit of the 0 interpolation interpolator using a switch and the bandpass filter, it is possible to realize a device that is resistant to temperature changes and temporal changes. (2) Since the frequency conversion device is composed of a digital circuit, it is easy to form a single chip with the modulation device.

(Embodiment 2) Next, a second embodiment of the present invention will be described. In this embodiment, the bandpass filter in the first embodiment is composed of only an adder and a delay circuit. The method for realizing this will be described below.

The transfer function H (z) of the bandpass filter is shown in (Equation 1). In this example, L is an odd number.

[Equation 1]

A frequency conversion circuit having a bandpass filter having this transfer function is shown in FIG. That is,
The frequency conversion circuit includes a 0 interpolation interpolator 301 and a bandpass filter 302. Next, as shown in FIG. 3B, the bandpass filter 302 is divided into a numerator portion 303 and a denominator portion 304 of its transfer function. In this configuration, the numerator portion 303 and the denominator portion 304 both operate at the sampling frequency L * f ₁ . Then, when this transfer function is converted into an actual circuit, as shown in FIG.
Adders 310 and 311 and delay circuits (mD) 305 and 3
06, 307, 308, 309, 312, 313.

Next, the operation of this embodiment shown in FIG.
explain about. Fall of kth clock to CKL1
It is assumed that a garri is input. The rising edge of the clock
And the fall may be reversed. The 0 interpolation interpolator 301 composed of switches is a low-speed
Sampling frequency f ₁High-speed input signal 314
Sampling frequency L * f₁Joined to the a side only once
Interpolation is performed by joining the b side only L-1 times.
U. This changes the input to the adder 310, so
The adder 310 starts calculation. Input to the adder 311 after the value of the adder 310 is confirmed
Changes, the adder 311 starts calculation. this
The calculation must be completed by the rising edge of the kth clock.
I have to. Delay circuit at rising edge of clock 315 of CLK1
305, 306, 307, 308, 309, 312, 3
Take the value in 13. By the above operation, the input signal (sampling frequency
f₁, Center frequency f₁/ 4) is L times the frequency (sample
Frequency L * f₁, Center frequency L * f₁/ 4) frequency
Numbers can be converted.

As described above, according to the above embodiment, the following effects are obtained. (1) A bandpass filter can be configured with (2L + 2) * N delay circuits and 2 * N adders without the need for a multiplier. However, the word length of the data is N bits. (2) If the word length of the adder is increased, it is possible to execute an integer operation without an operation error. From the above, according to the present embodiment, the function of frequency-converting a baseband signal generated with high accuracy into a bandpass signal without delay distortion can be realized with a simple circuit.

(Embodiment 3) Next, a third embodiment of the present invention will be described. The second embodiment is an example of a frequency conversion device which does not require a multiplier and can be realized by (2L + 2) * N delay circuits and 2 * N adders, but here, the frequency conversion ratio L is increased. Then, it can be seen that the circuit scale increases substantially in proportion to L. This is a limitation in the frequency conversion device, and this embodiment solves this point.

In the second embodiment described above, FIG.
The conversion from (b) to (b) is as described above. Here, considering the numerator part 303, the input signal to the numerator part 303 is a signal which is 0-interpolated and interpolated L times, so that the time a * L * T ₁ (a = 0, 1, 2 ,. Has a value at time (a * L + b) * T ₁ (a = 0, 1,
2,. . . / B = 0, 1 ,. . . , L-1) has a value of 0
Becomes Therefore, the calculation result of the numerator portion 303 is also the time a.
* L * T ₁ (a = 0, 1, 2, ...) Has a value,
Time (a * L + b) * T ₁ (a = 0, 1, 2, ... /
b = 0, 1 ,. . . , L-1) has a value of 0. Using this property, the numerator part 303 is operated at a low sampling frequency f ₁ which is the same as the input signal of the frequency conversion device at a low speed, and a 0 interpolation interpolator 301 for performing 0 interpolation is brought after the numerator part 303. What is different is the configuration of FIG.

As shown in FIG. 4A, the numerator portion 403 which operates at low speed and the zero interpolation interpolator 40 which operates at high speed.
The number of delay circuits in the numerator portion 403 can be reduced from 2 * L * N to 2 * N by the configuration of 1 and the denominator portion 404, and the frequency conversion device can be operated at a low speed with a block operating at a low speed. By dividing into operating blocks, the power consumption of the entire device can be reduced. A frequency conversion device shown in FIG. 4B is a circuit in which such a configuration is converted into an actual circuit. 401 is a 0 interpolation interpolator, and 405 and 40.
6, 409, 410 are delay circuits (mD), 407, 40
8 is an adder.

Next, the operation of this frequency converter will be described. It is assumed that the rising edge of the i-th clock is input to CLK2 (f ₁ Hz) and the rising edge of the j-th clock is input to CLK1 (L * f ₁ Hz). The rising and falling edges of the clock may be reversed. The signal 411 at time i is input at the rising edge of CLK2. As a result, the input to the adder 407 changes, so that the adder 407 operates at the signal 411 at the time i and at the time i-2.
The calculation with the signal 412 of 1 is started. This operation is CLK2
Must end by the fall of. The 0 interpolation interpolator 401 is switched to the b side at CLK0. The 0 interpolation interpolator 401 must prevent the adder 407 from changing when it is indefinite. As a result, the input to the adder 408 changes,
The adder 408 starts calculation of the signal 413 at time j and the signal 414 at time j−2. This calculation must be completed by the falling edge of CLK1. Values are loaded into the delay circuits 405 and 406 at the falling edge of CLK2. Values are loaded into the delay circuits 410 and 409 at the falling edge of CLK1. The above operation, the input signal (sampling frequency f _1, the center frequency f _1/4) may be frequency-transformed to L times the frequency (sampling frequency L * f _1, the center frequency L * f _1/4).

As described above, according to the above embodiment, the following effects are obtained. (1) A bandpass filter can be configured with 4 * N delay circuits and 2 * N adders without requiring a multiplier. However, the word length of the data is N bits. (2) The circuit configuration and scale of the frequency conversion device are constant regardless of L. (3) If the word length of the adder is increased, it can be executed by an integer operation without an operation error. (4) About 1/2 of the circuit operates at a low speed, so that the power consumption can be reduced. As described above, the present embodiment can realize the function of frequency-converting a baseband signal generated with high accuracy into a bandpass signal without delay with a simple circuit.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described. What is important in the frequency conversion device is that the frequency band required by the band pass filter is passed without distortion and the other frequency bands are not passed. However, the bandpass filter shown in (Equation 1) may not obtain the required cutoff characteristic,
In such a case, in this embodiment, the bandpass filter shown in (Equation 1) is cascade-connected to improve the cutoff characteristic.
By connecting M stages in cascade, it is possible to improve to M * xdB when the attenuation amount of the frequency in one stage is xdB.

The same bandpass filter is connected after the bandpass filter 302 shown in FIG.
It is divided into a numerator part and a denominator part as shown in (b). That is, the numerator portion 303 and the denominator portion 304 are further connected in cascade after the denominator portion 304. Since the sampling frequencies of the numerator part and the denominator part are the same, the same parts are arranged in the structure shown in FIG. 501 is a 0 interpolation interpolator, 502 and 503 are numerator parts, and 504 and 505 are denominator parts. This is 0 as in the third embodiment.
The 0 interpolation interpolator 501 for performing interpolation is used as the numerator part 50.
What was brought after 2, 503 is the configuration of FIG.

As shown in FIG. 5B, the numerator parts 502 and 503 which operate at low speed, the zero interpolation interpolator 501 which operates at high speed, and the denominator parts 504 and 505,
By dividing the frequency conversion device into blocks operating at low speed and blocks operating at high speed, the power consumption of the entire device can be reduced. The frequency conversion device shown in FIG. 5C is a circuit in which such a configuration is converted into an actual circuit.
501 is a 0 interpolation interpolator, 506, 507, 509, 51.
0, 513, 514, 516, 517 are delay circuits (m
D), 508, 511, 512 and 515 are adders.

Next, the operation of this frequency converter will be described. It is assumed that the rising edge of the i-th clock is input to CLK2 (f ₁ Hz) and the rising edge of the j-th clock is input to CLK1 (L * f ₁ Hz). The rising and falling edges of the clock may be reversed. The signal 518 at time i is input at the rising edge of CLK2. As a result, the input to the adder 508 changes, so that the adder 508 changes the signal 518 at time i and the time i-2
The calculation of the signal 519 is started. This calculation must be completed by the falling edge of CLK2. After the value of the adder 508 is determined, the input to the adder 511 changes, so the first stage output 520 at time i and the time i-
The calculation with the first stage output 521 of 2 is started. This calculation must be completed by the falling edge of CLK2. The 0 interpolation interpolator 501 is switched to the b side at CLK0. The 0 interpolation interpolator 501 must prevent the adder 511 from changing when it is indefinite. This changes the input to the adder 512, so
The adder 512 outputs the signal 522 at time j and 1 at time j-2.
The calculation with the stage output 523 is started. This operation is CL
It must be completed by the fall of K1. After the value of the adder 512 is fixed, the input to the adder 515 changes, so the first-stage output 524 at time j and the time j−
The calculation with the second stage output 525 of 2 is started. This calculation must be completed by the falling edge of CLK1. At the falling edge of CLK2, delay circuits 506, 507,
The values are taken into 509 and 510. At the falling edge of CLK1, the delay circuits 514, 513,
The values are loaded into 517 and 516. The above operation, the input signal (sampling frequency f _1, the center frequency f _1/4) may be frequency-transformed to L times the frequency (sampling frequency L * f _1, the center frequency L * f _1/4).

As described above, according to the above embodiment, the following effects are obtained. (1) No multiplier required, 4 * M * N delay circuits and 2 *
A bandpass filter can be configured with M * N adders. However, the word length of the data is N bits. (2) The circuit configuration and scale of the frequency conversion device are constant regardless of L. (3) If the word length of the adder is increased, it can be executed by an integer operation without an operation error. (4) About 1/2 of the circuit operates at a low speed, so that the power consumption can be reduced. (5) By connecting the bandpass filters in multiple stages,
The stopband attenuation can be increased. As described above, the present embodiment can realize the function of frequency-converting a baseband signal generated with high accuracy into a bandpass signal without delay with a simple circuit.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described. The carrier frequency used in the currently used transmitter is several hundred MHz to several GHz, and the input signal to the frequency converter is several hundred kHz when it is produced by a DSP or the like. From this fact, when the frequency conversion device of the present invention is actually used, the frequency conversion ratio L becomes a large value and high speed operation is required. Therefore, in the present embodiment, a frequency conversion device that achieves high speed by implementing a pipeline is realized.

FIG. 6A is the same as FIG. 5C. With such a configuration, in the denominator part after the 0 interpolation interpolator 601 which operates at high speed, the calculation of the adders connected in two stages in cascade must be completed per unit operation time T ₁ / L. Therefore, high-speed real-time operation becomes impossible when the operation bit length is large or the number of stages is large. Therefore, in the present embodiment, as shown in FIG. 6B, the adder in the subsequent stage of the 0 interpolation interpolator 601 is pipelined to realize high speed.

FIG. 7 shows the concept for pipelining adders. The basic configuration of FIG. 7A is as shown in FIG.
The configuration is the same as the latter stage of (a), and one adder A and two delay units D are cascaded in two stages. A delay circuit D-FF is inserted into the circuit to make a synchronous circuit, and each delay circuit D-F
By optimizing F as shown in FIG. 7 (c), the operation of one stage is completed within the unit operation time T ₁ / L. In this way, a structure in which the processing of one adder is performed in one unit time is called a pipeline structure, and is called a pipeline processing.

Next, the frequency conversion device in this embodiment shown in FIG. 6B will be described. 601 is a 0 interpolation interpolator, 606, 607, 609, 610, 613, 61
4, 616, 617 are delay circuits (mD), 608, 61
1, 612 and 615 are adders. Delay circuit 606,
The operation of the numerator portion that performs the low-speed operation composed of 607, 609, 610 and the adders 608, 611, and the operation of the 0 interpolation interpolator 601 that follows the operation are the same as those in the fourth embodiment.
The operation of the denominator part after the 0 interpolation interpolator 601 will be described below.

It is assumed that the falling edge of the i-th clock is input to CLK2 (f ₁ Hz) and the falling edge of the j-th clock is input to CLK1 (L * f ₁ Hz). The rising and falling edges of the clock may be reversed. The 0 interpolation interpolator 601 is switched to the b side at CLK0. The 0 interpolation interpolator 601 must prevent the adder 611 from changing when it is indefinite. CLK1 at the same time
Delay circuit 613, 614, 616, 61 at the rising edge of
Set the value to 7. The value of the delay circuit 613 is the time j−
1, the value of the delay circuit 614 is the time j−2, the delay circuit 616
Is the value at time j-1, and the value of the delay circuit 617 is the value at time j-2. This changes the input to the adder 612, so
The adder 612 outputs the signal 622 at time j and 1 at time j-2.
The calculation with the stage output 623 is started. This operation is CL
It must be completed by the rise of K1. After the value of the adder 612 is fixed, the input to the adder 615 changes, so the first stage output 624 at time j and the time j−
The calculation with the second stage output 625 of 2 is started. This calculation must be completed by the rising edge of CLK1. Since the adders 612 and 615 can be processed in parallel in this way, only one operation needs to be performed within the unit time, and the operation speed is not affected by the number of stages of the bandpass filter. The above operation, the input signal (sampling frequency f _1, the center frequency f _1/4) may be frequency-transformed to L times the frequency (sampling frequency L * f _1, the center frequency L * f _1/4).

As described above, according to the above embodiment, the following effects are obtained. (1) No multiplier required, 4 * M * N delay circuits and 2 *
A bandpass filter can be configured with M * N adders. However, the word length of the data is N bits. (2) The circuit configuration and scale of the frequency conversion device are constant regardless of L. (3) If the word length of the adder is increased, it can be executed by an integer operation without an operation error. (4) About 1/2 of the circuit operates at a low speed, so that the power consumption can be reduced. (5) By connecting the bandpass filters in multiple stages,
The stopband attenuation can be increased. (6) By arranging the delay circuit between the adder of the denominator part which operates at high speed and the adder, each adder only needs to perform one calculation per unit time, and high speed operation can be achieved. As described above, the present embodiment can realize the function of frequency-converting a baseband signal generated with high accuracy into a bandpass signal without delay with a simple circuit.

(Embodiment 6) Next, a sixth embodiment of the present invention will be described. The frequency conversion device of the present invention uses the frequency conversion ratio L and the number of stages M of the bandpass filter as parameters. In the fifth embodiment, a delay circuit D-FF is provided for each stage of the adder unit for pipeline processing, and the operation per stage is completed within the unit operation time T ₁ / L. As a result, it is possible to realize a device that does not affect real-time processing even if the number M of stages of the bandpass filter of the frequency conversion device is increased. In this embodiment, the frequency conversion ratio L will be considered.

In the frequency conversion device of the present invention, the bandpass filter has L ^M-1 gain at the frequency L * f ₁ . This is because the gain becomes 1 / L by the 0 interpolation and the gain becomes L ^M by the bandpass filter.
Therefore, the number of bits of the adder must be expanded by the number of bits shown in (Equation 2) so that overflow does not occur due to the bandpass filter calculation.

[Equation 2]

Due to this extension of the bit length, the bit length of the adder is increased, and the maximum frequency at which real-time operation can be performed is lowered. The present embodiment solves such a problem.

(1) Carrier propagation time by parallel adder: When the adder is realized at high speed, carrier propagation becomes a problem. As an example, a description will be given using FIG. 3.1 on p. In the parallel adder, addition is performed bit by bit from the lower bit. At this time, at the nth bit, the addition operation of the n-1th bit carrier and the nth bit augend is performed. Therefore, in the parallel adder, when the time for the addition of 1 bit and delta _1, in order to perform the addition of N bits by propagation of the carrier, is required calculation time of Enuderuta _1. As a result, when N increases, high speed operation becomes impossible. (2) Speeding up of adder: A method for speeding up a multi-bit adder is described in the document "High-speed computing method of computer: Modern Kagakusha", Chapter 3, etc. Even when the carry look ahead method or the conditional sum adder described in this document is used, the total addition time increases as the number of bits increases, and the constraint makes high-speed operation impossible. It becomes a condition. (3) Description of a method for realizing a frequency conversion circuit that is speeded up by using a pipelined configuration of a parallel adder: Therefore, in this embodiment, a multi-bit adder can be operated at a sufficiently high speed. Pipeline processing is performed separately for each minority bit adder. With such a configuration, it is possible to realize a frequency conversion device that can operate at high speed without depending on the frequency conversion ratio L.

This embodiment will be described below with reference to FIG.
In FIG. 8, the denominator portion of the L-fold frequency conversion device having a bandpass filter having a two-stage configuration (M = 2) that operates at high speed will be described as an example. Here, the adder uses two m-bit parallel adders in two stages, and the total number of bits is 2m-1.
Realizes the adder of. In FIG. 8, mFA is an m-bit parallel adder, and there are various configuration methods such as a ripple carry adder, a carry look ahead adder, and a conditional sum adder. D is a 1-bit delay circuit,
mD is an m-bit parallel delay circuit.

Carry propagation becomes a problem when an adder is implemented at high speed. Here, the operation of the adder mFA will be described. Operation at the kth clock of CLK1 (L * f ₁ Hz). The lower m bits 801 are input to the delay circuit 802.
The upper m bits 824 are input to the delay circuit 825.
This is the upper m bits of the input signal at the kth clock. The operation result m bit 806 of the mFA 805 is input to the delay circuit 807. Carry 820 of mFA805
Is input to the delay circuit 821. The m bits 808 are input to the delay circuit 809. The m-bit 826 is the delay circuit 8
27. Calculation result of mFA812 m bit 8
13 is input to the delay circuit 814. The carry 822 of the mFA 812 is input to the delay circuit 823. m bit 8
15 is input to the delay circuit 816. The operation result m bit 831 of the mFA 830 is input to the delay circuit 832.
The m bit 833 is input to the delay circuit 834. The m bits 815 are input to the delay circuit 818. mFA837
The operation result m bits 838 are input to the delay circuit 839. The m bits 840 are input to the delay circuit 841.

When the values of the delay circuits 802 and 809 change, the inputs 803 and 810 to the mFA 805 change, so that the mFA 805 starts calculation. This is the operation result of the lower m bits of the input signal at the kth clock. When the values of the delay circuits 807 and 816 change, mFA
Since the inputs 808 and 817 to 812 change, mFA
812 starts calculation. Delay circuits 827, 834 and 8
When the value of 21 changes, the inputs 828, 835, and 829 to the mFA 830 change, so the mFA 830 starts calculation. When the values of the delay circuits 832, 841 and 823 change, the inputs 833, 842 and 836 to the mFA 837.
Changes, the mFA837 starts calculation. These operations must be completed by the (k + 1) th clock of CLK1 (L * f ₁ Hz).

The operation for the lower m bits 801 and the upper bits 824 input at the kth clock will be described. The lower m bits 801 of the kth clock are latched by the delay circuit 802.
The input 803 to the mFA 805 changes and the calculation is performed. 806 is the sum of the operation result of the lower bits,
0 is a carry. The upper m bits 824 are the delay circuit 82.
5 is latched. k + 1st clock The sum 806 of the calculation result of the lower m bits is the delay circuit 807.
Latched on. The input 808 to the mFA 812 changes and the operation is performed. Reference numeral 813 is a sum of the operation result of the second stage of the lower bit, and 822 is a carry. Lower m
The carry 820 of the bit operation result is latched by the delay circuit 821. The upper m bits 826 are latched by the delay circuit 827. mFA830 is the upper m bits 8 of time k
28 and the carry 829 of the operation result of the first stage of the lower m bits at the time k. 831 is the upper m bits of 2
It is the sum of the calculation result of the first row. The sum 813 of the operation result of the second stage of the k + 2nd clock lower m bits is latched by the delay circuit 814. The carry 822 of the second stage operation result of the lower m bits is latched by the delay circuit 823.
The sum 831 of the second stage operation result of the upper m bits is latched in the delay circuit 832. mFA837 is 1 at time k
2 of the upper m bits 833 of the stage and the lower m bits of time k
An operation with the carry 836 of the operation result of the stage is performed. 83
Reference numeral 8 is a sum of the calculation result of the second stage of the upper m bits. The sum 815 of the second stage operation result of the k + 3rd clock lower m bits is latched by the delay circuit 818. The sum 838 of the operation result of the second stage of the upper m bits is latched by the delay circuit 839. As described above, the calculation result of the input signal at the kth clock is determined when the k + th 3rd clock is input.

In this way, the maximum operable frequency depends on the operation time of the m-bit parallel adder by implementing the adder with m-bit parallel adders and performing pipeline processing. , M, the maximum operable frequency can be increased. Although the parallel adder is used in two stages here, it can be realized in any number of stages as required.

As described above, according to the above embodiment, the following effects are obtained. (1) No multiplier required, 4 * M * N delay circuits and 2 *
A bandpass filter can be realized with M * N adders.
However, the word length of the data is N bits. (2) The circuit configuration and scale of the frequency conversion device are constant regardless of L. (3) If the word length of the adder is increased, it can be executed by an integer operation without an operation error. (4) Since half of the circuit operates at a low speed, low power consumption can be achieved. (5) By connecting the bandpass filters in multiple stages,
The stopband attenuation can be increased. (6) By placing a delay circuit between the adder of the denominator part that operates at high speed and the adder, each adder is set to 1 per unit time.
Only one calculation is required, and high speed operation can be achieved. (7) The N-bit adder in the denominator part that operates at high speed is pipelined by a parallel adder for every n bits, so that even if the bit length increases, it is possible to perform operations per unit time and achieve high-speed operation. . From the above, according to the present embodiment, the function of frequency-converting a baseband signal generated with high accuracy into a bandpass signal without delay distortion can be realized with a simple circuit.

(Embodiment 7) Next, a seventh embodiment of the present invention will be described. In the fifth embodiment described above, in order to achieve high speed operation, an N-bit adder is divided into n-bit units to realize a device having a pipeline structure. In this configuration, the speed can be increased, but the number of adders that determine the circuit scale must be 2 * M * N (M is the number of stages of the bandpass filter, and N is the bit length of the adder). . Reducing the number of full adders is very important for practical use. In this embodiment, the number of adders is reduced. The method for realizing this will be described below. 1) Circuit example of 1-bit successive adder: FIG. 9 shows a circuit example of a 1-bit successive adder, and FIG. 10 shows a timing chart example. In FIG. 9, S is a switch, FA is a 1-bit adder, D is a 1-bit delay circuit, and mSR is an m-bit shift register. The timing chart is 4 bits (m =
4 shows an operation example when performing the calculation of 4). The operation will be described below. Operation at φ ₀₀ : A value is input to Di 901. The m-bit shift registers 907 and 909 are shifted by 1 bit, and the result of the 1-bit adder 905 is stored in the MSB of the m-bit shift register 907 as the m-bit shift register 909.
The MSB of the m-bit shift register 907 is stored in the MSB of. The carry 911 is stored in the delay circuit 912. The switch 903 is joined to the a side. Carry input 90
Reference numeral 2 is a carry output in the preceding stage. It is 0 if there is no preceding stage. Since the input values 901, 910 and 904 change, the 1-bit adder 905 starts calculation. This operation is φ
Must finish by ₁₀ . Operation at φ ₁₀ : Same as operation at φ ₀₀ , but the switch 903 is connected to the b side. This calculation must be completed by φ ₂₀ . Operation at φ ₂₀ : Same as operation at φ ₁₀ . This calculation must be completed by φ ₃₀ . Operation at φ ₃₀ : Same as operation at φ ₁₀ . This operation must be completed by φ ₄₀ . In this way, the 1-bit adder FA and the m-bit shift register mS
Using R, switch S and 1-bit delay circuit D, an m-bit addition operation can be performed.

2) Description of a method for realizing a frequency conversion device that reduces the number of full adders by using a pipelined configuration of a 1-bit successive adder: This embodiment will be described below with reference to FIG. In FIG. 11, as an example, the denominator part of the L-fold frequency conversion device in which the bandpass filter has a two-stage configuration (M = 2) operates at high speed. Here, as the adder, a 1-bit sequential adder that adds two m bits is used in two stages to realize an adder with a total number of bits N = 2m. In FIG. 11, mSR is an m-bit shift register, and mSFA is a 1-bit successive adder.

Each unit of the circuit operates at L * f ₁ Hz. CLK3 (L * f ₁ Hz) and CLK in each unit
It operates at 4 (m * L * f ₁ Hz). The operation in each unit is as described in 1) above. Since the operation between the units is the same as the operation between the units when the parallel adder of the fifth embodiment is used, the duplicate description will be omitted.

As described above, according to this embodiment, the following effects are obtained. (1) No multiplier required, 4 * M * N delay circuits and 2 *
A bandpass filter can be realized with M * N adders.
However, the word length of the data is N bits. (2) The circuit configuration and scale of the frequency disguising device are constant regardless of L. (3) If the word length of the adder is increased, it can be executed by an integer operation without an operation error. (4) About 1/2 of the circuit operates at a low speed, so that the power consumption can be reduced. (5) By connecting the bandpass filters in multiple stages,
The stopband attenuation can be increased. (6) By placing a delay circuit between the adder of the denominator part that operates at high speed and the adder, each adder is set to 1 per unit time.
Only one calculation is required, and high speed operation can be achieved. (7) The number of 1-bit adders is changed from 4 * M * N to (number It can be reduced as in 3).

[0049]

(Equation 3) From the above, according to the present embodiment, the function of frequency-converting a baseband signal generated with high accuracy into a bandpass signal without delay distortion can be realized with a simple circuit.

(Embodiment 8) Next, an eighth embodiment of the present invention will be described. As described in the sixth embodiment, in the frequency conversion device of the present invention, the bandpass filter has the frequency L *.
It has a gain of L ^{M- 1 at} F ₁ . This is because the gain becomes 1 / L by the 0 interpolation and the gain becomes L ^M by the bandpass filter. Therefore, the number of bits of the adder must be expanded by the number of bits shown in (Equation 2) so that overflow does not occur due to the bandpass filter calculation. Due to this extension of the bit length, the bit length of the delay circuit increases, and the circuit scale increases.

However, since the frequency conversion device of the present invention performs fixed decimal point arithmetic, when the required number of input bits is y, the output is expanded to x + y bits. In the configuration of the fifth embodiment, considering the variables together, the input is x + y bits and the output is x + y bits. However, the output requires only y bits from the higher order and the lower x bits are unnecessary. Similarly, since the input is the lower y bits of x + y, the delay circuit for the upper x bits is unnecessary.

Utilizing such a property, the present embodiment is intended to reduce the number of delay circuits, and its configuration is shown in FIG. In FIG. 12, the input bit number is m bits, the word length expansion by the bandpass filter is m bits, and the output bit number is m bits. In FIG. 12, mD is an m-bit delay circuit, mFA is an m-bit parallel adder, and D is a 1-bit delay circuit.

The operation will be described below. Operation at the kth clock of CLK2 (L * f ₁ Hz): The lower m bits 1201 are input to the delay circuit 1202. Calculation result of mFA1205 m bit 1206
Is input to the delay circuit 1207. The carry 1218 of the mFA 1205 is input to the delay circuit 1219. The m bits 1208 are input to the delay circuit 1209. mFA1
The operation result m bit 1213 of 212 is the delay circuit 1214.
Is input to The carry 1220 of the mFA 1212 is input to the delay circuit 1221. The m bits 1215 are input to the delay circuit 1216. Calculation result of mFA1224 m
Bit 1225 is input to delay circuit 1226. The m bits 1227 are input to the delay circuit 1228. mFA
The operation result m bit 1232 of 1231 is the delay circuit 123.
Input to 3. The m bit 1234 is the delay circuit 1235.
Is input to

When the values of the delay circuits 1202 and 1209 change, the inputs 1203 and 1210 to the mFA 1205 change, so the mFA 1205 starts calculation. This is the operation result of the lower m bits of the input signal at the kth clock. When the values of the delay circuits 1207 and 1216 change, the inputs 1208 and 1217 to the mFA 1212 change, so that the mFA 1212 starts calculation. When the values of the delay circuits 1228 and 1219 change, the mFA122
Since the inputs 1229 and 1223 to 4 change, mFA
1224 starts calculation. Delay circuits 1226 and 123
When the values of 5 and 1221 change, the inputs 1227, 1236, and 1230 to mFA1231 change, so mF
A1231 starts the calculation. These operations are CLK1
It must be completed by the (k + 1) th clock of (L * f ₁ Hz). Next, the operation for the lower m bits 1201 input at the kth clock will be described. kth clock: Lower m bits 1201 are latched by the delay circuit 1202. Input to mFA1205 12
03 changes and the operation is performed. Reference numeral 1206 is a sum of the calculation result of the lower m bits, and reference numeral 1218 is a carry. k + 1st clock: Sum 1206 of the operation result of the lower m bits is latched in the delay circuit 1207. mFA
The input 1208 to 1212 changes and the operation is performed. 1213 is a sum of the operation result of the lower m bits,
1220 is a carry. The carry 1218 of the calculation result of the lower m bits is latched by the delay circuit 1219. mF
A 1224 performs an operation on the carry 1223 and the input 1222 of the operation result of the first stage of the upper m bits at time k.
1225 is a sum of the calculation result of the second stage of the upper m bits. k + 2nd clock: Sum 1213 of the second stage operation result of the lower m bits is latched in the delay circuit 1214. However, this data is not used as output. The carry 1220 of the second stage operation result of the lower m bits is latched in the delay circuit 1221. The sum 1225 of the operation result of the first stage of the upper m bits is latched in the delay circuit 1226. The mFA 1231 performs an operation on the upper m bits 1227 of the first stage at time k and the carry 1230 of the operation result of the lower m bits of the time k on the second stage. 1232 is the top m
It is the sum of the operation result of the second stage of the bit. k + 3rd clock: The sum 1232 of the second stage operation result of the upper m bits is latched by the delay circuit 1233. As described above, the calculation result of the input signal at the kth clock is determined when the k + th 3rd clock is input, and is output from the delay circuit 1233.

In this way, when the arithmetic circuit is expanded from the input m bits to the output 2 m bits, the configuration as shown in FIG. 12 is used to eliminate overflow and reduce unnecessary delay circuits. Therefore, the circuit scale can be optimally reduced. Although the parallel adder is used in two stages here, it can be realized in any number of stages as necessary in consideration of the gain in each stage of the bandpass filter.

As described above, according to the above embodiment, the following effects can be obtained. (1) A bandpass filter is added to the adder 2 without the need for a multiplier.
It can be realized with * M * N pieces. However, the word length of the data is N bits. (2) The maximum number of delay devices is 4 * M * N, but it can be reduced in consideration of the gain at each stage of the bandpass filter. (3) If the word length of the adder is increased, it can be executed by an integer operation without an operation error. (4) About 1/2 of the circuit operates at a low speed, so that the power consumption can be reduced. (5) By connecting the bandpass filters in multiple stages,
The stopband attenuation can be increased. (6) By placing a delay circuit between the adder of the denominator part that operates at high speed and the adder, each adder is set to 1 per unit time.
Only one calculation is required, and high speed operation can be achieved. (7) The N-bit adder of the denominator part that operates at high speed is pipelined by a parallel adder for every m bits, so that even if the bit length increases, it is possible to perform operations per unit time and achieve high-speed operation. . From the above, according to the present embodiment, the function of frequency-converting a baseband signal generated with high accuracy into a bandpass signal without delay distortion can be realized with a simple circuit.

(Ninth Embodiment) Next, a ninth embodiment of the present invention will be described. In the frequency converter according to the third embodiment shown in FIG. 4, the numerator part operates at the same low speed as the sampling frequency of the input signal, and the 0 interpolation interpolator and the denominator part operate at L times the sampling frequency of the input signal. There is. The fact that it can be divided into a low-speed operation unit and a high-speed operation unit in this way is very suitable for realizing the low-speed operation unit with a DSP that generates a modulated wave and operating the high-speed operation unit with a gate array.

FIG. 13 shows the configuration of a frequency conversion device according to the ninth embodiment of the present invention, which uses a DSP and a gate array. A parallel port is used as the interface between the DSP and the gate array, but a configuration using a serial port is naturally conceivable. In FIG. 13, 130
Reference numeral 1 denotes a DSP, which includes a modulation circuit 1302, two delay circuits (D) 1303 and 1304, and an adder 1305. A gate array 1306 includes a 0 interpolation interpolator 1307, an adder 1308, and two delay circuits 1
309 and 1310.

The DSP 1301 operates at CLK2 (f ₁ Hz), performs the operation of the low speed operation section, and outputs the N-bit calculation result from the parallel port. Gate array 130
6 operates at CLK1 (L * f ₁ Hz), the 0 interpolation interpolator 1307 is connected to the a side once, and the value of the low speed operation unit is 13
11 is taken in, L-1 times are joined to the b side, and the adder circuit 1
Input to 308. Adder circuit 1308 and delay circuit 131
Both 0 and 1309 operate at CLK1 (L * f ₁ Hz). In this way, the DSP 1301 and the gate array 1306 can form a frequency conversion device.

[0060]

As is apparent from the above embodiment, the present invention realizes a frequency conversion device with a digital circuit of a 0-interpolation interpolator and a bandpass filter, which is resistant to temperature changes and aging changes. A frequency converter having stable characteristics can be realized. In addition, since the device is realized by a digital circuit, there is an effect that it is easy to achieve one chip with the modulator.

[Brief description of drawings]

FIG. 1 is a block diagram of a frequency conversion device according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the theory of operation of the frequency conversion device according to the first embodiment of the present invention on the frequency axis.

FIG. 3 is a block diagram of a frequency conversion device according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a frequency conversion device according to a third embodiment of the present invention.

FIG. 5 is a block diagram of a frequency conversion device according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram of a frequency conversion device according to a fifth embodiment of the present invention.

FIG. 7 is a block diagram illustrating an exchanging method for pipeline processing of an adder circuit according to a fifth embodiment of the present invention.

FIG. 8 is a block diagram of a configuration (when the number of bandpass filter stages is two) that implements an N-bit adder m-bit parallel adder by pipeline processing according to a sixth embodiment of the present invention.

FIG. 9 is a block diagram of a 1-bit successive addition circuit according to a seventh embodiment of the present invention.

FIG. 10 is a timing chart of a 1-bit successive addition circuit according to a seventh embodiment of the present invention.

FIG. 11 is an N-bit adder m according to the seventh embodiment of the present invention.
Block diagram of a configuration in which a bit sequential adder is realized by pipeline processing (when the number of bandpass filter stages is two)

FIG. 12 is a block diagram of a frequency conversion device according to an eighth embodiment of the present invention.

FIG. 13 is a block diagram of a frequency conversion device according to a ninth embodiment of the present invention.

FIG. 14 is a block diagram of a conventional frequency conversion device.

[Explanation of symbols]

101, 301, 401, 501, 601, 1307
0 interpolation interpolator 102, 302, 303, 304, 403, 404, 5
02, 503, 504, 505, 602, 603, 60
4,605 band pass filter L frequency conversion ratio M number of stages of band pass filter N 1 bit length of addition unit (parallel adder or 1-bit successive adder) f ₁ sampling frequency of input signal (f ₁ = 1/1 /
T ₁ ) T ₁ input signal sampling time interval (f ₁ = 1 / T
₁ ) L * f ₁ Sampling frequency of signal after frequency conversion (L * f ₁ = L / T ₁ ) T ₁ / L Sampling time interval of signal after frequency conversion (L * f ₁ = L / T ₁ ) FA 1-bit adder mFA m-bit parallel adder mSFA 1-bit successive adder (adds m bits) D 1-bit delay circuit mD m-bit delay circuit mSR m-bit shift register

Claims (9)

[Claims] 1. A 0-interpolation for frequency-converting a low-frequency sampling frequency signal by performing a 0-interpolation interpolation using a switch when converting the frequency of a transmitted signal from a low frequency to a high frequency in a transmitter. A frequency conversion device comprising an interpolator and a bandpass filter for extracting a necessary frequency component from the frequency-converted signal. 2. The frequency conversion device according to claim 1, wherein the bandpass filter comprises an adder and a delay circuit. 3. The frequency conversion device according to claim 2, wherein a bandpass filter including an adder and a delay circuit is connected in multiple stages. 4. A zero interpolation interpolator is arranged between the front bandpass filter and the rear bandpass filter.
The described frequency conversion device. 5. The frequency conversion device according to claim 4, wherein the addition operation is realized by pipeline processing by arranging delay circuits in the band pass filter at the subsequent stage in parallel. 6. In the latter bandpass filter, m
The frequency conversion device according to claim 4, wherein the addition processing is performed by pipeline processing every m bits using a parallel adder of bits, a delay circuit for storing a carrier, and a delay circuit for storing a sum. 7. A bandpass filter in the latter stage, wherein N
5. The frequency conversion device according to claim 4, wherein the bit adder is a 1-bit successive adder for each m bits, and the addition processing is performed for each m bits by pipeline processing. 8. In the latter stage bandpass filter, N
A bit adder is a m-bit parallel adder,
The frequency conversion device according to claim 4, wherein the addition processing is performed for each bit by pipeline processing. 9. The frequency conversion apparatus according to claim 4, wherein the front bandpass filter is composed of a digital signal processor, and the 0 interpolation interpolator and the rear bandpass filter are composed of a gate array.