JPH0983505A - Frame detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To more speedily and stably detect a frame even for an oblivion coefficient α similar to the conventional one by making input data smaller than a threshold zero with the average of input data as the threshold. SOLUTION: An arithmetic circuit 11 calculating an average value from input data and a judgment circuit 12 comparing input data and the threshold with the calculated value as the thresholds and making data inputted to a storage circuit 6 zero when input data is judged to be smaller than the threshold as the result are provided between a data input terminal 1 and a switch 4 in series. Then, data inputted to the storage circuit 6 is controlled. The arithmetic average of input data is calculated and input data smaller than the arithmetic average of input data is controlled to be switched to zero by judged information obtained by comparing calculated data with input data with the calculated data as threshold. Thus, the storage content of the storage circuit 6 to which a data symbol is inputted can be reduced for the oblivion coefficient α similar to the conventional one.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a frame detection circuit of a receiver.

[0002]

2. Description of the Related Art In recent years, multi-valued QAM has been adopted as a highly efficient digital modulation system for improving frequency utilization efficiency and realizing high-speed data transmission. On the other hand, multi-level QAM
In order to detect the timing of a transmission frame by periodically transmitting a known pilot symbol, for example, "Communications Research Institute Quarterly Vol. 37, No. 1, pp. 99-10.
7 ".

A conventional technique will be described with reference to FIG. FIG.
FIG. 4 is a block diagram showing a conventional example of a multilevel QAM receiver frame detection circuit, and 16 QAM will be described as an example. 16
QAM is a digital modulation method in which a carrier is modulated by 16 symbols shown in FIG. 6 corresponding to 4-bit digital data and transmitted. Further, in order to correctly detect the signal sequence demodulated by the receiver, a known pilot symbol (for example, point A in FIG. 6) having the maximum amplitude that defines the frame reference is shown in FIG. An example in which one pilot symbol is inserted for every −1 data symbol: n is an integer of 2 or more.

In the conventional circuit shown in FIG. 2, the squared amplitude value (= I ² + Q ² , I:
When the in-phase component, Q: quadrature-phase component) is input to the data input terminal 1, it is given to the switch 4 which makes one cycle at the frame period n. Each output of the switch 4 has n memory circuits 6
The storage circuit 6 averages the stored contents and the input data, gives the calculation result to the comparator 7, and updates the stored contents. On the other hand, a clock input from the clock signal input terminal 2 and synchronized with the reproduced symbol timing is connected to the timing circuit 3, and the output of the timing circuit 3 is given to the switch 4, the memory circuit 6 and the comparator 7. , A signal for determining the timing of switch switching, storage circuit switching for averaging, and data comparison. Therefore, the data at the same position in the frame is cumulatively averaged (synchronized addition) in each storage circuit 6.

The basic operation of the storage circuit 6 is as shown in FIG. 4, in which the forgetting factor α (0 <0
The value obtained by multiplying α <1) by the multiplier 9 is added by the adder 10, and the result is stored in the memory 8. Here, since the square amplitude value of the pilot symbol is 18, the content M _P of the memory 8 when the input of the storage circuit 6 is the pilot symbol (frame timing) is in a steady state, and M _P = 18 × (1 + α + α ² + α ³ + ...) = 18 / (1-.alpha.) ... (1). On the other hand, since the data symbol takes 16 symbols in FIG. 6 with the same probability, the expected value E of the squared amplitude value is E = (2 × 4 + 10 × 8 + 18 × 4) / 16 = 10. (2) Therefore, the content M _D of the memory 8 when the input of the memory circuit 6 is a data symbol is M _D = E × (1 + α + α ² + α ³ + ...) = 10 / (1−α) (3) , The following equation (4) holds.

M _P > M _D ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ (4) Even when fading exists in the transmission line, the fluctuation of the fading is in a steady state. If the above-mentioned synchronous addition is executed when it can be regarded, the relation of Expression (4) is established. Therefore, the frame timing is detected by comparing the magnitudes of the stored contents of all the storage circuits in the comparator 7 and detecting the data input timing to the storage circuit having the maximum stored content.

[0007]

In the above-mentioned conventional technique, the forgetting factor α determines the number of samples to be averaged and also determines the frame detection ability. That, alpha it is indicative that a small number of samples to average at the frame detection closer to 0, although the memory 8 converges in a short time, the difference between M _P and _{M D ΔM (= M P -M} D ) Becomes smaller, the code error rate characteristic deteriorates due to the occurrence of erroneous detection. Therefore, in order to reduce erroneous detection, it is necessary to set α sufficiently large to make ΔM larger, but at this time, the number of samples to be averaged is large, and it takes more time until the memory 8 converges than when α is small. It will take a lot of time.

In view of the above situation, it is an object of the present invention to provide a frame detection circuit capable of detecting a frame faster and more stably even with the same forgetting factor α as the conventional one.

[0009]

According to the present invention, in order to achieve the above object, an arithmetic circuit 11 for calculating an average value from input data of a frame detection circuit as shown in FIG.
And using the calculated value as a threshold value, compare the input data with the threshold value, and if the result is that the input data is less than or equal to the threshold value, the determination circuit 12 that makes the data input to the storage circuit 6 zero The data input terminal 1 and the switch 4 are provided in series to control the data input to the memory circuit 6.

[0010] In the present invention, as described above, as a threshold the average of the input data, a result of the structure to zero the following input data threshold value, the stored contents M _D of the memory circuit 6 to enter the data symbols in the steady state ' Is smaller than the conventional M _D , the difference ΔM ′ (= M _P −M _D ′) between the pilot symbol and the stored content M _P of the storage circuit 6 is ΔM ′ in comparison with the conventional ΔM. > ΔM (∵M _D ′ <M _D ) ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ (5). Further, in the present invention, in the transient state,
The difference between the stored content relating to the pilot symbol and the stored content relating to the data symbol reaches ΔM in a shorter time than in the conventional case. Therefore, even when the frame is detected using the same forgetting factor α as in the conventional case, the frame can be detected more quickly and stably.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIG. FIG. 3 is a block diagram showing an embodiment of the present invention. In this embodiment, the arithmetic mean of the input data is calculated,
The input data is switched to zero according to the determination information obtained by comparing the input data with the calculated data as a threshold.

This operation will be described below. In FIG. 3, when the squared amplitude value of the demodulated symbol is input from the data input terminal 1, the data via the switch 122 described later is input to the storage circuit 6 by the switch 4 and averaged with the contents of the storage circuit 6. The memory circuit 6 is connected to a comparator 7. This comparator 7 compares the stored contents of all the memory circuits and outputs information regarding the data input timing (frame timing) to the memory circuit having the maximum value. .
The output of the timing circuit 3 which receives the clock synchronized with the input data serves as a signal for determining the operation timing of each block.

On the other hand, the input data is also input to the arithmetic circuit 11 and the judging circuit 12, and the arithmetic circuit 11 calculates the arithmetic mean of the input data and outputs the calculation result to the judging circuit 12. The comparator 121 in the determination circuit 12 uses this calculation result as a threshold to compare and determine the magnitude of the input data value. Then, when it is determined that the input data is less than or equal to the threshold value, the switch 122 is controlled so that the data input to the switch 4 becomes zero.

For example, if the threshold value m is 10 <m <18, "2" and "10" in the input data ("2", "10", "18") are replaced with "0". , The expected value E ′ for the data symbol is E ′ = (0 × 4 + 0 × 8 + 18 × 4) /16=4.5 (6), and the storage content M _D ′ of the storage circuit 6 to which the data symbol is input. Becomes as shown in the following formula (7), which is 45% lower than that in the conventional case (formula (3)), and the difference ΔM ′ between the pilot symbol and the memory content M _P of the memory circuit 6 is input.
Is 169% of the conventional value.

M _D ′ = E × (1 + α + α ² + α ³ + ...) = 4.5 / (1-α) (7) In this embodiment, as described above, the arithmetic operation of the input data of the frame detection circuit is performed. By controlling the input data below the average to be switched to zero, the memory content of the memory circuit 6 to which the data symbol is input can be reduced even with respect to the same forgetting factor α as the conventional one. The difference from the stored contents of the circuit 6 is enlarged. Further, even when fading exists in the transmission path, if the fading fluctuation can be regarded as a steady state, if the frame detection method is executed, the average value also fluctuates according to the fluctuation of the input data due to fading. Similar effects are obtained.

[0016]

As described above, according to the method of the present invention, the same forgetting factor α as the conventional one is used in the frame detection circuit using the synchronous addition method in the system for transmitting the data symbol sequence including the pilot symbols. Even when the frame detection is performed by using the frame detection, the frame detection can be performed at higher speed and more stably.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of the present invention.

FIG. 2 is a block diagram showing an overall configuration of a conventional technique.

FIG. 3 is a block diagram showing one embodiment of the present invention.

FIG. 4 is a block diagram showing an operation principle of a memory circuit.

FIG. 5 is a diagram showing an example of a frame structure.

FIG. 6 is a diagram showing an example of a 16QAM signal space arrangement having pilot symbols.

[Explanation of symbols]

1 ... Data input end, 2 ... Clock signal input end, 3 ... Timing circuit, 4 ...
Switch, 5 ... Frame detection signal output terminal, 6 ...
Memory circuit, 7 ... Comparator, 8 ...
Memory, 9 ... Multiplier, 10 ...
Adder, 11 ... Arithmetic circuit, 12 ...
Judgment circuit, 121 ... Comparator, 12
2 ... switch.

Claims (2)

[Claims] 1. A frame detection circuit of a receiver in a digital signal transmission system, in which pilot symbols are periodically inserted between data symbol sequences, and a transmission frame is formed on the basis of the pilot symbols, the number being equal to the number of frame symbols. In a frame detection circuit having means for detecting frame timing using the storage circuit of, a means for calculating an average value from input information of the frame detection circuit and a comparison judgment with the input information using the calculated information as a threshold, A frame detection circuit having means for making input information to the storage circuit zero when it is determined that the value is equal to or less than a threshold value. 2. The frame detection circuit according to claim 1, wherein the information stored in the storage circuit is information obtained by averaging demodulation information at the same position in a time slot, and is used for comparison / determination with the input information. The reference threshold value is the average value information given from the means for calculating the average value from the input information of the frame detection circuit, and the method of determining the input information of the frame detection circuit is the average value information of the calculation means. As the threshold value is a method of determining whether the input information of the frame detection circuit is larger than the threshold value, and when it is determined that the input information is less than or equal to the threshold value from the comparison determination method,
A frame detection circuit having means for making input information to the storage circuit zero.