JPH0983296A - Filter circuit - Google Patents

Filter circuit

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Publication number
JPH0983296A
JPH0983296A JP23979295A JP23979295A JPH0983296A JP H0983296 A JPH0983296 A JP H0983296A JP 23979295 A JP23979295 A JP 23979295A JP 23979295 A JP23979295 A JP 23979295A JP H0983296 A JPH0983296 A JP H0983296A
Authority
JP
Japan
Prior art keywords
circuit
voltage
operational amplifier
filter
mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23979295A
Other languages
Japanese (ja)
Other versions
JP3497022B2 (en
Inventor
Yuji Yamamoto
有二 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP23979295A priority Critical patent/JP3497022B2/en
Publication of JPH0983296A publication Critical patent/JPH0983296A/en
Application granted granted Critical
Publication of JP3497022B2 publication Critical patent/JP3497022B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide the filter circuit consisting of capacitors and MOS transistors(TRs) and having a Q multiple circuit suitable for MOS circuit integration. SOLUTION: A voltage is applied to a noninverting input terminal of an operational amplifier 16 from a 1st stage of MOS diodes 8, 7 connecting in series with a constant current source 9 and a voltage is applied to a gate of MOS resistor 15 from a 2nd stage of MOS diodes 11, 12 connected in series with a constant current source 10. The DC operating point is made stable by using the MOS resistance 15. An output of a filter 3 is fed back by a coefficient consisting of a ratio of a capacitance 17 to a capacitance 14 and added to the input 4 to form a Q multiple circuit.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は,様々の周波数成分
をもつ入力信号の内から,所望の信号を選択又は除去す
るフィルタ回路に関する。更に詳しくは,該フィルタ回
路のMOS集積回路化に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a filter circuit for selecting or removing a desired signal from input signals having various frequency components. More specifically, it relates to a MOS integrated circuit of the filter circuit.

【0002】[0002]

【従来の技術】従来,高い選択度Qをもつフィルタを簡
単に構成する方法として M.E.VAN VANKE
NBURG,”Analog Filter Desi
gn”,Holt,Rinehart and Win
ston,NEW YORK,1982,PP217
等に見られるように,Q逓倍回路が知られている。一般
にQの高いフィルタは,大きい素子値の比を必要とする
ため,図2に示すように,加算回路とQの低いフィルタ
回路とを二段構成にして帰還をかけ,小さい素子値の比
で構成したQの低いフィルタ回路のQを逓倍するのが,
Q逓倍回路である。図2において,以下の数式1の伝達
関数で示される所謂2次のバンドパスフィルタ3の出力
(Vout)を,Kaのゲインを乗じて入力(Vin)
と加算し,前記2次のバンドパスフィルタ3の入力とす
るものである。ωは共振角周波数とする。
2. Description of the Related Art Conventionally, as a method for easily constructing a filter having high selectivity Q, M. et al. E. FIG. VAN VANKE
NBURG, "Analog Filter Desi
gn ", Holt, Rinehart and Win
stone, NEW YORK, 1982, PP217
Q multiplier circuits are known. In general, a filter having a high Q requires a large element value ratio, and therefore, as shown in FIG. 2, feedback is performed by providing feedback with a two-stage configuration of an adder circuit and a low Q filter circuit. Multiplying the Q of the configured low Q filter circuit is
It is a Q multiplication circuit. In FIG. 2, the output (Vout) of a so-called second-order bandpass filter 3 represented by the transfer function of the following Expression 1 is input by multiplying the gain of Ka (Vin).
Is added and is input to the second-order bandpass filter 3. ω is the resonance angular frequency.

【0003】[0003]

【数1】 [Equation 1]

【0004】図2の回路の入力Vinと出力Voutの
伝達関数は,
The transfer function of the input Vin and the output Vout of the circuit of FIG.

【0005】[0005]

【数2】 [Equation 2]

【0006】数式1と数式2の比較から,図2の回路
は,逓倍する前の2次のバンドパスフィルタ3に比べて
1/(1−Ka)倍のQを持っている。
From the comparison between Expression 1 and Expression 2, the circuit of FIG. 2 has a Q that is 1 / (1-Ka) times that of the second-order bandpass filter 3 before multiplication.

【0007】[0007]

【発明が解決しようとする課題】個別部品を用いて図2
の回路のKaの部分を構成する場合には,演算増幅器と
抵抗とを使用した,所謂抵抗結合加算回路で実現する場
合が多い。ところが抵抗と演算増幅器を使用した回路
を,単一電源動作のMOS集積回路で実現しようとする
と,直流ゲインを持つ為,演算増幅器のオフセット電圧
を増幅してしまい,動作点がずれるという問題点があっ
た。又,抵抗の代わりに容量を用いて容量結合の加算回
路を使用すると,オフセット電圧を増幅することはなく
なるが,直流動作点を設定する為に,容量に並列に,M
OS集積回路に不適な高抵抗が必要になるという問題点
あるいは課題があった。
With the use of individual parts, FIG.
In the case of configuring the Ka portion of the circuit (1), it is often realized by a so-called resistance-coupling addition circuit using an operational amplifier and a resistor. However, if a circuit using a resistor and an operational amplifier is to be realized by a MOS integrated circuit that operates with a single power supply, the offset voltage of the operational amplifier is amplified because it has a DC gain, and the operating point shifts. there were. Also, if a capacitance coupling adder circuit is used instead of a resistor, the offset voltage will not be amplified, but in order to set the DC operating point, in parallel with the capacitance, M
There is a problem or problem that an unsuitable high resistance is required for the OS integrated circuit.

【0008】[0008]

【課題を解決する為の手段】上述した従来の技術の課題
を解決するために,本発明は,MOS集積回路化に適し
た加算回路で,Qを逓倍するフィルタ回路を提供するこ
とを目的とする。かかる目的を達成するために,本発明
では,加算回路を容量結合の加算回路とし,直流動作点
の設定用の高抵抗の代わりに,MOSトランジスタ(以
下MOSTr)を用いたMOS抵抗を用いた。MOS抵
抗を設定する為のゲート電圧を得る為に,先ず,演算増
幅器については,ダイオード接続したMOSTrに定電
流を流して閾値電圧(以下Vth)近傍の電圧を得て,
該電圧を直流動作点として設定した。ここでダイオード
接続とは,ゲート電極とドレイン電極を共通に接続し
て,ソース電極との間に擬似的なダイオード特性を得る
ものである。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, it is an object of the present invention to provide a filter circuit for multiplying Q by an adder circuit suitable for MOS integrated circuit. To do. In order to achieve such an object, in the present invention, the adding circuit is a capacitive coupling adding circuit, and a MOS resistor using a MOS transistor (hereinafter referred to as MOSTr) is used instead of the high resistance for setting the DC operating point. In order to obtain the gate voltage for setting the MOS resistance, first, in the operational amplifier, a constant current is passed through a diode-connected MOSTr to obtain a voltage near a threshold voltage (hereinafter Vth),
The voltage was set as the DC operating point. Here, the diode connection is to connect a gate electrode and a drain electrode in common to obtain a pseudo diode characteristic between the gate electrode and the source electrode.

【0009】次に,ダイオード接続したMOSTrを2
段直列に接続したものに,定電流を流すことで,ほぼ2
倍のVthの電圧を作成し,MOS抵抗のゲート電圧と
した。更に,演算増幅器の直流動作点を定めるための,
定電流源とダイオード接続したMOSTrと,MOS抵
抗のゲート電圧を得るための,定電流源とダイオード接
続したMOSTrとを,何れも同様にダイオード接続し
たMOSTrを2段直列にしたものに定電流源で電流を
流す構成とし,なおかつ各々別に設け,電圧の取り出し
箇所を,前者は,1段目から取ることでVth近傍の電
圧を得,後者は,2段目から取ることで2×Vth近傍
の電圧を得る。
Next, two diode-connected MOSTrs are connected.
By applying a constant current to those connected in series, almost 2
A voltage of twice the Vth was created and used as the gate voltage of the MOS resistor. Furthermore, to determine the DC operating point of the operational amplifier,
A constant current source is a diode-connected MOSTr, and a constant current source and a diode-connected MOSTr for obtaining a gate voltage of a MOS resistor. In the former, the voltage is taken out from the first stage to obtain a voltage near Vth, and the latter is taken from the second stage. Get the voltage.

【0010】本発明によれば,フィルタ回路のQを逓倍
する回路を,容量結合の加算回路として構成し,更に演
算増幅器の直流動作点の設定用の抵抗を,MOSTrを
利用したMOS抵抗で実現した。MOS抵抗のゲート・
ソース電極間の電圧は,必要最小限の,ほぼVth近傍
の電圧を印加しているため,MOS抵抗に使用するMO
STrのサイズを小さくできる。又,MOS抵抗のゲー
ト電圧の発生回路と,演算増幅器の直流動作点の電圧の
発生回路は,同一構成の回路を別々に設け,回路内の干
渉を防いでいる。該電圧発生回路は,ダイオード接続し
たMOSTrを2段直列にしたものに定電流源の電流を
流す構成にしている。以上述べた何れの回路も,MOS
集積回路化が容易である。
According to the present invention, the circuit for multiplying Q of the filter circuit is configured as a capacitive coupling adder circuit, and the resistance for setting the DC operating point of the operational amplifier is realized by a MOS resistance using MOSTr. did. MOS resistance gate
Since the voltage between the source electrodes is the minimum required voltage, which is near Vth, the voltage used for the MOS resistor is
The size of STr can be reduced. Further, the circuit for generating the gate voltage of the MOS resistor and the circuit for generating the voltage at the DC operating point of the operational amplifier are separately provided with the same configuration to prevent interference in the circuit. The voltage generating circuit has a structure in which a current of a constant current source is passed through a diode-connected MOSTr in two stages connected in series. All of the circuits described above are MOS
Easy to be integrated circuit.

【0011】[0011]

【発明の実施の形態】以下図面を参照して,本発明の好
適な実施例を,詳細に説明する。図1は,本発明にかか
るフィルタ回路の一実施例を示す回路図である。電源1
9にはPチャンネルMOSトランジスタ(以下PMOS
Tr)9,10のソース電極が接続されている。PMO
STr9,10の各々のゲート電極・ソース電極間に
は,定電圧源18が接続されているので,PMOSTr
9,10はドレイン電極・ソース電極間の電圧にかかわ
らず,定電流特性を示す。PMOSTr9と10のドレ
イン電極には,各々,ゲート電極とドレイン電極を共通
に接続したNチャンネルMOSトランジスタ(以下NM
OSTr)8,11が,接続されている。更にNMOS
Tr8,11のソース電極には,各々NMOSTr7,
12のドレイン電極とソース電極が共通に接続されてい
る。NMOSTr7,12のソース電極はグランド電位
に接続されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a filter circuit according to the present invention. Power supply 1
9 is a P-channel MOS transistor (hereinafter referred to as PMOS
The source electrodes of Tr) 9 and 10 are connected. PMO
Since the constant voltage source 18 is connected between the gate electrode and the source electrode of each of the STr 9 and 10, the PMOSTr
9 and 10 show constant current characteristics regardless of the voltage between the drain electrode and the source electrode. The drain electrodes of the PMOSTrs 9 and 10 each have an N-channel MOS transistor (hereinafter NM) in which a gate electrode and a drain electrode are commonly connected.
OSTr) 8 and 11 are connected. Further NMOS
For the source electrodes of Tr8 and 11, NMOSTr7 and
Twelve drain electrodes and source electrodes are commonly connected. The source electrodes of the NMOSTrs 7 and 12 are connected to the ground potential.

【0012】ここでPMOSTr9,10は同じサイズ
に設定しているので,直列に接続しているNMOSTr
8と7,11と12には同じ電流が流れる。従って,N
MOSTr7のゲート電極・ドレイン電極の電位Va
と,NMOSTr12のゲート電極・ドレイン電極の電
位Vbは等しく,NMOSTrの所謂閾値電圧をVth
とすると,ほぼVthになる。同様に,NMOSTr8
のゲート電極・ドレイン電極の電位Vcと,NMOST
r11のゲート電極・ドレイン電極の電位Vdは等しく
ほぼ2×Vthになる。NMOSTr15のゲート電極
は,電位Vdに接続されているので,同様にほぼ2×V
thになる。
Since the PMOSTrs 9 and 10 are set to have the same size, the NMOSTrs connected in series are connected.
The same current flows through 8 and 7, and 11 and 12. Therefore, N
Potential Va of gate electrode / drain electrode of MOSTr7
And the potential Vb of the gate electrode / drain electrode of the NMOSTr12 are equal, and the so-called threshold voltage of the NMOSTr is Vth.
Then, it becomes almost Vth. Similarly, NMOSTr8
Gate electrode / drain electrode potential Vc and NMOST
The potentials Vd of the gate electrode and the drain electrode of r11 are equal to each other and are approximately 2 × Vth. Since the gate electrode of the NMOSTr15 is connected to the potential Vd, it is similarly about 2 × V.
It becomes th.

【0013】PMOSTr9,NMOSTr8,7で電
圧発生回路32を構成し,PMOSTr10,NMOS
Tr11,12で電圧発生回路31を構成している。演
算増幅器16の非反転入力端子は,電位Vaに接続さ
れ,演算増幅器16の反転入力端子は,容量13,1
4,17の一端と,NMOSTr15のソース電極とに
共通に接続されている。容量13の他端は入力端子4に
接続され,容量14の他端は演算増幅器16の出力と,
NMOSTr15のドレイン電極と,2次の伝達関数を
持つバンドパスフィルタ3の入力1とに共通に接続され
ている。容量17の他端は,前記バンドパスフィルタ3
の出力2と,フィルタ回路6の出力端子5に接続されて
いる。前記バンドパスフィルタ3は,図2の3と,数式
1に示した2次の伝達関数を持つものである。該伝達関
数の実現方法は種々知られているが,一例を図3にしめ
す。図3のフィルタ回路3は,所謂多重帰還型のバンド
パスフィルタで,入力1から出力2ヘの伝達関数を数式
1にする事ができる。
The voltage generation circuit 32 is composed of the PMOSTr9, the NMOSTr8 and 7, and the PMOSTr10 and the NMOS
The Tr11 and Tr12 form a voltage generating circuit 31. The non-inverting input terminal of the operational amplifier 16 is connected to the potential Va, and the inverting input terminal of the operational amplifier 16 has capacitors 13, 1
It is commonly connected to one ends of 4, 17 and the source electrode of the NMOSTr 15. The other end of the capacitor 13 is connected to the input terminal 4, and the other end of the capacitor 14 is the output of the operational amplifier 16,
The drain electrode of the NMOSTr15 and the input 1 of the bandpass filter 3 having a quadratic transfer function are commonly connected. The other end of the capacitor 17 is connected to the bandpass filter 3
Output 2 and the output terminal 5 of the filter circuit 6. The bandpass filter 3 has the quadratic transfer function 3 shown in FIG. Although various methods of realizing the transfer function are known, an example is shown in FIG. The filter circuit 3 shown in FIG. 3 is a so-called multiple feedback type bandpass filter, and the transfer function from the input 1 to the output 2 can be expressed by Equation 1.

【0014】図1において,容量13,14,17と演
算増幅機16は,所謂容量結合増幅回路を構成してい
る。容量結合増幅回路は容量比によってゲインが設定出
来る。交流的に図1の回路が,図2の等価回路に等しく
なるようにする為には,容量13,14,17の容量値
を其々C13,C14,C17とすると, Ka=C17/C14,C13/C14=1 直流的な動作点について説明する。演算増幅機16の非
反転入力端子の電圧はVa,即ちほぼVthになってい
る。演算増幅機16の出力と,反転入力端子は,NMO
STr15によって直流的な全帰還がかかっているので
等しくなり,電圧は,非反転入力端子の電圧とも等し
く,ほぼVthになる。つまり,NMOSTr15のソ
ース電極の電位は,ほぼVthになる。NMOSTr1
5を,オンさせるためには,ソース電極とゲート電極間
に,Vth以上の電圧がかかれば良い。
In FIG. 1, the capacitors 13, 14 and 17 and the operational amplifier 16 constitute a so-called capacitive coupling amplifier circuit. The gain of the capacitive coupling amplifier circuit can be set by the capacitance ratio. In order to make the circuit of FIG. 1 equal to the equivalent circuit of FIG. 2 in terms of alternating current, when the capacitance values of the capacitors 13, 14, 17 are C13, C14, C17, respectively, Ka = C17 / C14, C13 / C14 = 1 A DC operating point will be described. The voltage at the non-inverting input terminal of the operational amplifier 16 is Va, that is, almost Vth. The output of the operational amplifier 16 and the inverting input terminal are NMO
Since the DC-like total feedback is applied by the STr15, they are equal to each other, and the voltage is equal to the voltage of the non-inverting input terminal and is approximately Vth. That is, the potential of the source electrode of the NMOSTr15 becomes almost Vth. NMOS Tr1
In order to turn on 5, it is sufficient to apply a voltage of Vth or more between the source electrode and the gate electrode.

【0015】前述したように,NMOSTr15のゲー
ト電極には,ほぼ2倍のVthの電圧がかかっているの
で,NMOSTr15のソース電極とゲート電極の間に
は,ほぼVth以上の電圧がかかり常にオンする。NM
OSTr15のソース電極とゲート電極の間の,ほぼV
thの電圧は,NMOST15rをオンさせるのに最小
限度の電圧であるのでオンした時の抵抗値が大きい,し
たがって,例えば,ゲート電極に電源電圧を印加するよ
うな場合に比べると,比較的小さなトランジスタサイズ
で,大きな抵抗値を実現できる。
As described above, since the gate electrode of the NMOSTr15 is applied with a voltage of Vth which is almost doubled, a voltage of approximately Vth or more is applied between the source electrode and the gate electrode of the NMOSTr15 and is always turned on. . NM
Almost V between the source electrode and the gate electrode of the OSTr15
Since the voltage of th is a minimum voltage for turning on the NMOST 15r, the resistance value when turned on is large. Therefore, for example, as compared with the case where the power supply voltage is applied to the gate electrode, the transistor is relatively small. A large resistance value can be realized with the size.

【0016】直流電圧のみ考えると,前述したように,
Va=Vb,Vc=Vdなので,Va,Vc等の電圧発
生回路部分は,一系統だけでもよい。ところが,NMO
STr15は,所謂非飽和動作を行なわせているので,
ゲート・ソース間容量Cgdとゲート・ドレイン間容量
Cgsが大きい。特にCgdは所謂飽和動作時に比べて
桁はずれに増大する。又トランジスタサイズも高い抵抗
値を実現するためには,ゲート長を,ゲート幅に比べて
極端に長くする必要がある為,ゲート長×ゲート幅×単
位面積当たりのゲート容量,で決まるゲート容量も大き
くなっている。
Considering only the DC voltage, as described above,
Since Va = Vb and Vc = Vd, the voltage generating circuit portion for Va, Vc, etc. may be only one system. However, NMO
Since the STr15 causes so-called non-saturation operation,
The gate-source capacitance Cgd and the gate-drain capacitance Cgs are large. In particular, Cgd increases by an order of magnitude as compared with the so-called saturation operation. In order to realize a high resistance value for the transistor size, the gate length needs to be extremely longer than the gate width. Therefore, the gate capacitance determined by (gate length x gate width x gate capacitance per unit area) is also It is getting bigger.

【0017】例えば,演算増幅器16の非反転入力端子
をVaに,NMOSTr15のゲート電極をVcに接続
すると,演算増幅器16の出力がNMOSTr15のC
gdを通し,NMOSTr15のゲート電極にもれ,N
MOSTr8のCgsとNMOSTr7のCgsで分圧
されてVc,Vaに現わる。Vaは,演算増幅器16の
非反転入力端子に接続されていて,演算増幅器16の出
力との間に正帰還ループを形成するため,発振等の不安
定動作を招きやすい。
For example, when the non-inverting input terminal of the operational amplifier 16 is connected to Va and the gate electrode of the NMOSTr15 is connected to Vc, the output of the operational amplifier 16 is C of the NMOSTr15.
Through gd, leak to the gate electrode of NMOSTr15, N
The voltage is divided by Cgs of the MOSTr8 and Cgs of the NMOSTr7 and appears in Vc and Va. Since Va is connected to the non-inverting input terminal of the operational amplifier 16 and forms a positive feedback loop with the output of the operational amplifier 16, unstable operation such as oscillation is likely to occur.

【0018】そこで本発明においては,同じ電圧のV
a,VbとVc,Vdを各々別に発生させる回路を設け
て,片方は,演算増幅器16の非反転入力端子の電圧V
a発生用に,残るもう片方は,NMOSTr15のゲー
ト電圧Vd発生用に用いて不安定動作を回避している。
Therefore, in the present invention, V of the same voltage is applied.
A circuit for separately generating a, Vb and Vc, Vd is provided, one of which has a voltage V of the non-inverting input terminal of the operational amplifier 16.
The other one for generating a is used for generating the gate voltage Vd of the NMOSTr15 to avoid unstable operation.

【0019】図1の回路と,図2の原理図において,フ
ィルタ3の部分は,図2に示したバンドパスフィルタの
伝達関数だけでなく,以下の数式3で示されるバンドリ
ジェクトフィルタの伝達関数F(s)でも適用が可能で
ある。
In the circuit of FIG. 1 and the principle diagram of FIG. 2, not only the transfer function of the bandpass filter shown in FIG. 2 but also the transfer function of the band reject filter expressed by the following mathematical formula 3 It is also applicable to F (s).

【0020】[0020]

【数3】 (Equation 3)

【0021】数式3はよく知られているように図4に示
される回路で実現される,ただし,数式3の負号は,前
述の容量結合増幅回路で実現している。原理的には,数
式3を,図2の伝達関数3と,置き換えることにより,
新たな伝達関数G(s)は
Equation 3 is realized by the circuit shown in FIG. 4 as is well known, but the negative sign of Equation 3 is realized by the aforementioned capacitive coupling amplifier circuit. In principle, by replacing Equation 3 with the transfer function 3 of FIG.
The new transfer function G (s) is

【0022】[0022]

【数4】 (Equation 4)

【0023】となり,この場合は,数式3と数式4の比
較から,(1+Ka)倍にQが増加している。 図4の
回路は,直流をゲイン1で通すので,フィルタ3の入力
1と,出力2は,前段の容量結合増幅器の直流出力であ
る,ほぼVthの直流電圧がそのまま現われる。図4の
中に使用している演算増幅器20の入力と出力の直流電
圧も,0Vになることはなく,動作領域を確保してい
る。
In this case, Q is increased by (1 + Ka) times from the comparison between Expression 3 and Expression 4. Since the circuit of FIG. 4 passes a direct current with a gain of 1, the input 1 and the output 2 of the filter 3 are the direct current output of the capacitive coupling amplifier of the preceding stage, and the direct current voltage of approximately Vth appears as it is. The DC voltage of the input and output of the operational amplifier 20 used in FIG. 4 does not become 0V, and the operation area is secured.

【0024】又,図1の回路は,フィルタ3の出力2
を,容量17を用いて交流のみ帰還している。フィルタ
3の出力2の直流分が,前段の演算増幅器16には帰還
されないので,演算増幅器16の直流動作点は,フィル
タ3が直流を通すか否かに影響されない。従って,図4
のような,直流を通すフィルタのQを逓倍することがで
きる。
In addition, the circuit of FIG.
The capacitor 17 is used to feed back only the alternating current. Since the DC component of the output 2 of the filter 3 is not fed back to the operational amplifier 16 in the previous stage, the DC operating point of the operational amplifier 16 is not affected by whether or not the filter 3 passes DC. Therefore, FIG.
It is possible to multiply the Q of a filter that allows direct current to pass.

【0025】図5は,本発明によるフィルタ回路6を,
リモコン受信用回路29に適用した実施例を示す。数1
0kHzの発光周期を持つ赤外光30は,フォトダイオ
ード等の光電変換素子21により電気信号に変換され,
入力端子22を通してリモコン受信用回路29に入力さ
れる。リモコン受信用回路29では,発光周期数10k
Hzの赤外光が入射しているか,全く入射していないか
を検出する。一般的に,入力端子22の信号は最小で5
0μV以下と微弱である。リモコン受信用回路29の内
部では,入力信号を低雑音増幅器23で増幅し,次にリ
ミッタ24で振幅を一定値に制限し,前記発光周期に同
調したバンドパスフィルタ6で信号成分のみを抽出し,
検波回路25で検波を行ない,検波後の直流レベルを一
定の閾値と比較してHigh又はLowレベルを出力す
る比較回路26を通して,出力端子27に出力する。太
陽光下のような直流的な入力がある場合のは,直流レベ
ル設定回路28が作動し,入力端子22の直流レベルの
変動を抑えている。
FIG. 5 shows a filter circuit 6 according to the present invention,
An embodiment applied to the remote control receiving circuit 29 will be shown. Number 1
The infrared light 30 having a light emission cycle of 0 kHz is converted into an electric signal by a photoelectric conversion element 21 such as a photodiode,
It is inputted to the remote control receiving circuit 29 through the input terminal 22. In the remote control receiving circuit 29, the number of light emission cycles is 10 k
Detects whether the infrared light of Hz is incident or not. Generally, the signal at the input terminal 22 is at least 5
It is as weak as 0 μV or less. In the remote control receiving circuit 29, the input signal is amplified by the low noise amplifier 23, the amplitude is then limited by the limiter 24 to a constant value, and only the signal component is extracted by the bandpass filter 6 tuned to the light emission cycle. ,
The detection is performed by the detection circuit 25, and the detected direct current level is output to the output terminal 27 through the comparison circuit 26 which compares the direct current level with a fixed threshold value and outputs a high or low level. When there is a direct current input such as under sunlight, the direct current level setting circuit 28 operates to suppress the variation of the direct current level of the input terminal 22.

【0026】リモコン受信用回路29には,入力信号の
みを通すように,入力の発光周期に同調したQの高いバ
ンドパスフィルタ6が必要である。本発明によるバンド
パスフィルタ6は,Qが高いフィルタを容易に構成で
き,しかもCMOSプロセスで容易に実現が可能である
為,特にCMOS集積回路化したリモコン受信用回路2
9に適する。
The remote control receiving circuit 29 needs a bandpass filter 6 having a high Q, which is tuned to the light emission cycle of the input so as to pass only the input signal. Since the bandpass filter 6 according to the present invention can easily form a filter having a high Q and can be easily realized by a CMOS process, the remote control receiving circuit 2 which is particularly a CMOS integrated circuit is provided.
Suitable for 9.

【0027】[0027]

【発明の効果】以上説明したように,本発明によれば,
フィルタのQを向上させるQ逓倍回路に必要な加算回路
を,直流を増幅しない容量結合の加算回路で実現し,そ
の直流動作点の設定を,高抵抗の代わりにMOS抵抗を
用いている為MOS集積回路化に適している。
As described above, according to the present invention,
The addition circuit necessary for the Q multiplication circuit that improves the Q of the filter is realized by a capacitance-coupling addition circuit that does not amplify DC, and the DC operating point is set by using MOS resistance instead of high resistance. Suitable for integrated circuits.

【0028】更にMOS抵抗用のMOSトランジスタの
ゲート電極に印加する電圧の発生回路と,加算回路の直
流動作点設定用の電圧発生回路を分離して,干渉を防い
でいるため,安定な動作を行なえるQ逓倍回路を提供で
きる。
Further, the voltage generating circuit for applying the voltage to the gate electrode of the MOS transistor for the MOS resistor and the voltage generating circuit for setting the DC operating point of the adder circuit are separated to prevent interference, so that stable operation is achieved. It is possible to provide a Q multiplication circuit that can be performed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す回路図。FIG. 1 is a circuit diagram showing an embodiment of the present invention.

【図2】図1の回路の交流等価回路。FIG. 2 is an AC equivalent circuit of the circuit of FIG.

【図3】二次の伝達関数をもつバンドパスフィルタの一
例の回路図。
FIG. 3 is a circuit diagram of an example of a bandpass filter having a quadratic transfer function.

【図4】二次の伝達関数をもつバンドリジェクトフィル
タの一例の回路図。
FIG. 4 is a circuit diagram of an example of a band reject filter having a quadratic transfer function.

【図5】本発明の一実施例を示す回路図。FIG. 5 is a circuit diagram showing an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 フィルタの入力端子 2 フィルタの出力端子 3 フィルタ 4 Q逓倍回路付きフィルタの入力端子 5 Q逓倍回路付きフィルタの出力端子 6 Q逓倍回路付きフィルタ 7,8,11,12,15 NチャンネルMOSトラン
ジスタ 9,10 PチャンネルMOSトランジスタ 13,14,17 容量 16,20 演算増幅器 18,19 電圧源 21 光電変換素子 22 リモコン受信用回路の入力端子 23 低雑音増幅器 24 リミッタ 25 検波回路 26 比較回路 27 リモコン受信用回路の出力端子 28 直流レベル設定回路 29 リモコン受信用回路 30 赤外光 31,32 電圧発生回路
1 Filter input terminal 2 Filter output terminal 3 Filter 4 Q multiplier circuit filter input terminal 5 Q multiplier circuit filter output terminal 6 Q multiplier circuit filter 7, 8, 11, 12, 15 N-channel MOS transistor 9 , 10 P-channel MOS transistors 13, 14, 17 Capacitance 16, 20 Operational amplifier 18, 19 Voltage source 21 Photoelectric conversion element 22 Input terminal of remote control receiving circuit 23 Low noise amplifier 24 Limiter 25 Detection circuit 26 Comparison circuit 27 Remote control receiving Output terminal of the circuit 28 DC level setting circuit 29 Remote control receiving circuit 30 Infrared light 31, 32 Voltage generation circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】第1の電圧発生回路と,第2の電圧発生回
路と,ソース電極が演算増幅器の反転入力端子に接続さ
れドレイン電極が前記演算増幅器の出力に接続されゲー
ト電極が前記第1の電圧発生回路の出力端子に接続され
た第1のMOSトランジスタと,一端が入力端子他端が
前記演算増幅器の反転入力端子に接続された第1の容量
と,前記演算増幅器の反転入力端子と前記演算増幅器の
出力の間に配した第2の容量と,出力端子と前記演算増
幅器の反転入力端子との間に配した第3の容量と,前記
演算増幅器の出力と出力端子の間に配した2次の伝達関
数をもつフィルタ回路と,非反転入力端子は前記第2の
電圧発生回路の出力端子に接続した前記演算増幅器とで
構成されたフィルタ回路。
1. A first voltage generating circuit, a second voltage generating circuit, a source electrode connected to an inverting input terminal of an operational amplifier, a drain electrode connected to an output of the operational amplifier, and a gate electrode connected to the first electrode. A first MOS transistor connected to the output terminal of the voltage generating circuit, an input terminal at one end thereof connected to the inverting input terminal of the operational amplifier at the other end, and an inverting input terminal of the operational amplifier A second capacitor is provided between the output of the operational amplifier, a third capacitor is provided between the output terminal and the inverting input terminal of the operational amplifier, and a third capacitor is provided between the output of the operational amplifier and the output terminal. A filter circuit including a filter circuit having a quadratic transfer function and the operational amplifier whose non-inverting input terminal is connected to the output terminal of the second voltage generating circuit.
JP23979295A 1995-09-19 1995-09-19 Filter circuit Expired - Fee Related JP3497022B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23979295A JP3497022B2 (en) 1995-09-19 1995-09-19 Filter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23979295A JP3497022B2 (en) 1995-09-19 1995-09-19 Filter circuit

Publications (2)

Publication Number Publication Date
JPH0983296A true JPH0983296A (en) 1997-03-28
JP3497022B2 JP3497022B2 (en) 2004-02-16

Family

ID=17049950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23979295A Expired - Fee Related JP3497022B2 (en) 1995-09-19 1995-09-19 Filter circuit

Country Status (1)

Country Link
JP (1) JP3497022B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8208590B2 (en) 2006-11-13 2012-06-26 Panasonic Corporation Filter circuit, and receiver and electronic device using the same filter circuit
JP2017534171A (en) * 2014-10-22 2017-11-16 株式会社村田製作所 Pseudo resistance circuit and charge detection circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8208590B2 (en) 2006-11-13 2012-06-26 Panasonic Corporation Filter circuit, and receiver and electronic device using the same filter circuit
JP2017534171A (en) * 2014-10-22 2017-11-16 株式会社村田製作所 Pseudo resistance circuit and charge detection circuit

Also Published As

Publication number Publication date
JP3497022B2 (en) 2004-02-16

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