JPH098287A - Semiconductor circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor circuit device having a semiconductor element having an excellent ESD breakdown voltage by using the element having a diffused layer with low resistance by silicidizing and a method for manufacturing the same by suppressing the increase in the number of the steps to the minimum limit. SOLUTION: The semiconductor circuit device comprises a semiconductor element 1 having a pair of impurity diffused layers 3, 3 formed at the surface layer side of an Si substrate 2 as a semiconductor substrate and an electrode layer 5 formed on the surface of the substrate 2 at the pair of layer positions 3, 3 in such a manner that at least the opposed sides of the layer 5 are semiconductor layers 5a made of semiconductor material. In a method of manufacturing the semiconductor circuit device, a contact hole 7 for forming the layer 5a of the element 1 in the case of forming the contact hole of the other semiconductor element in the device, and the semiconductor material is embedded in the hole 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit device and a method of manufacturing the semiconductor circuit device, and more particularly to a semiconductor circuit device using a semiconductor element having a pair of silicided diffusion layers and a method of manufacturing the same. .

[0002]

2. Description of the Related Art Conventionally, an ESD (Electr) using an nMOS field effect transistor (hereinafter referred to as MOSFET) is used.
As a protection circuit (hereinafter, referred to as an ESD protection circuit) from an o-Static Discharge, for example, one having a configuration shown in FIG. 4 is known. The MOSFET 50 shown in FIG. 4 has its source electrode and gate electrode connected to the ground line 51 side, and its drain electrode connected to an input signal line 53 connecting an input terminal 52 and an internal circuit (not shown). , A n-type source / drain diffusion layer and a p-type silicon (Si) substrate constitute a parasitic npn bipolar transistor 54. That is, the n-type source and drain diffusion layers serve as the emitter and collector diffusion layers of the parasitic npn bipolar transistor 54, and the Si substrate sandwiched between these diffusion layers serves as the base.

Such a MOSFET 50 has a large number of Ms.
In a semiconductor circuit device using an OSFET, it is very effective and widely used as an element for an ESD protection circuit at its input / output terminal.

By the way, in the field of MOSFET manufacturing in recent years, in order to suppress the parasitic resistance in the source and drain of the MOSFET and to speed up the semiconductor circuit device, a Si substrate is formed on the surface of the Si substrate at the source and drain diffusion layers. Alloying layer with refractory metal (hereinafter referred to as silicide layer)
There is provided a so-called salicide structure that forms a.

[0005]

However, when the above-mentioned salicide structure MOSFET is used as an ESD protection circuit element, in the ESD protection circuit element, the collector and emitter diffusion layers of the parasitic bipolar transistor formed in the ESD protection circuit element are formed on the base side. Since a silicide layer having a low resistance exists, the discharge current flowing between the collector and emitter diffusion layers is excessively concentrated on the base side of the collector and emitter diffusion layers, and the current density in this portion is higher than that in other portions. Become.

As a result, the temperature on the base side of the collector / emitter diffusion layer becomes high, and thermal breakdown is likely to occur. Therefore, the ESD protection circuit element is a MOSFET without a salicide structure. The ESD withstand voltage is significantly inferior to the case of using the ESD protection circuit element. In particular, at the output terminal of the semiconductor circuit device, the output MOSFET itself also serves as an ESD protection circuit, so that it is difficult to avoid a decrease in ESD withstand voltage.

Further, not only MOSFET but also a semiconductor element having a silicided diffusion layer is used as an ESD protection circuit element, there is a disadvantage that the ESD breakdown voltage is lowered for the same reason as above. When the ESD withstand voltage of the ESD protection circuit element is lowered, the semiconductor circuit device is easily electrostatically damaged, resulting in a device failure.

On the other hand, in order to prevent a decrease in the ESD withstand voltage of the ESD protection circuit element composed of a salicide structure MOSFET, the MOSFET used for the ESD protection circuit element and the MOSFET used for the other internal circuits are made separately to form the former. It is also possible to consider a countermeasure such as not using a salicide structure. However, in this case, when forming the silicide layer, it is necessary to add a step of masking the MOSFET serving as the ESD protection circuit element, which significantly increases the number of manufacturing steps and increases the manufacturing cost.

The present invention has been made in order to solve the above problems, and uses a semiconductor element having a diffusion layer whose resistance is reduced by silicidation, and has an excellent ES.
A semiconductor circuit device including a semiconductor element having a D breakdown voltage;
It is an object of the present invention to provide a method for manufacturing a semiconductor circuit device, which can manufacture such a device with a minimum increase in the number of steps.

[0010]

A semiconductor circuit device according to the present invention comprises a pair of impurity diffusion layers formed on the surface side of a semiconductor substrate and electrode layers formed on the surface of the semiconductor substrate at positions of the pair of impurity diffusion layers. And a semiconductor layer having a semiconductor layer including a semiconductor material, and at least the sides of the electrode layers facing each other are semiconductor layers made of a semiconductor material.

According to the method of manufacturing a semiconductor circuit device of the present invention, a pair of impurity diffusion layers are formed on the surface side of the semiconductor substrate, and the semiconductor substrate and the refractory metal are formed on the surface of the semiconductor substrate at each position of the pair of impurity diffusion layers. And a pair of impurity diffusion layers are formed on the surface side of the semiconductor substrate, and an electrode layer is formed on the surface of the semiconductor substrate at each position of the pair of impurity diffusion layers. And a second semiconductor element in which at least opposite sides of the electrode layer are semiconductor layers made of a semiconductor material are manufactured. That is, in the first step, a plurality of pairs of impurity diffusion layers are formed on the surface layer side of the semiconductor substrate, and in the second step, the semiconductor substrate and the refractory metal are alloyed on the surface of the semiconductor substrate at each impurity diffusion layer position. Each layer is formed. Next, in a third step, an insulating film is formed on the semiconductor substrate while covering the alloyed layer, and in a fourth step, a mask for forming a contact hole is formed on the insulating film. Then, in a fifth step, a first contact hole reaching the impurity diffusion layer in the region for forming the first semiconductor element is formed in the insulating film by etching using the mask, and the second film is formed. A second contact hole reaching at least opposite sides of the pair of impurity diffusion layers in a region for forming a semiconductor element is formed. And in the sixth step,
A step of forming a wiring layer on the insulating film in a state of covering the side wall of the first contact hole and a step of burying a semiconductor material in at least the bottom of the second contact hole are performed.

According to the above invention, there are the following effects. In the semiconductor element constituting the semiconductor circuit device of the present invention, when the semiconductor substrate has, for example, p-type conductivity and the semiconductor layers constituting the impurity diffusion layer and the electrode layer have n-type conductivity, The impurity diffusion layer and the semiconductor layer form a parasitic npn bipolar transistor. In addition, since the semiconductor layer is generally high in resistance, and is formed on the sides of the pair of electrode layers facing each other, that is, on the base side of the npn bipolar transistor, even if the electrode layer has a low resistance in a portion other than the semiconductor layer. Even if the alloyed layer is formed, the resistance of the impurity diffusion layer on the base side is not lowered. Therefore, when this semiconductor element is used as an ESD protection circuit element in a semiconductor circuit device, the discharge current flowing between the impurity diffusion layers is not excessively concentrated on the base side of the pair of impurity diffusion layers, and the density of the discharge current in this portion is The temperature does not rise to the same level as when the resistance of the impurity diffusion layer is not reduced by the alloyed layer.

In the method of manufacturing a semiconductor circuit device according to the present invention, the first contact hole of the first semiconductor element is formed and at the same time the second contact hole for forming the semiconductor layer of the second semiconductor element is formed. A semiconductor circuit device is manufactured with the increase in the number being minimized.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory view showing a first embodiment of a semiconductor circuit device of the present invention, and is a view particularly showing a semiconductor element which is a feature of the present invention. 1A is a plan view of the main part of the semiconductor element, and FIG. 1B is a side sectional view of the main part of the semiconductor element.

The semiconductor circuit device of this embodiment is shown in FIG.
In the semiconductor element 1, a p-type S that serves as a semiconductor substrate of the present invention is provided.
On the surface side of the i substrate 2, a pair of n ⁺ -type impurity diffusion layers 3,
3 are formed. A field oxide film 4 is formed on the surface of the Si substrate 2 so as to surround the pair of impurity diffusion layers 3 and 3. An electrode is formed on the surface of the Si substrate 2 at the positions of the pair of impurity diffusion layers 3 and 3. Layer 5 has been formed. That is, a pair of electrode layers 5 and 5 are formed on the surface of the Si substrate 2 so as to face each other.

Each electrode layer 5 is a semiconductor layer 5 whose part is made of a semiconductor material such as n ⁺ type polysilicon or polycide.
The semiconductor layer 5a is formed on the side opposite to each other with the field oxide film 4 sandwiched between the pair of electrode layers 5 and 5. In addition, each electrode layer 5 is composed of a silicide layer 5b which is an alloyed layer of the Si substrate 2 and a refractory metal such as cobalt, tungsten or titanium except the semiconductor layer 5a. The semiconductor layer 5a is formed with a thickness that reaches the upper surface position of the interlayer insulating film 6 described later.

The silicide layer 5 is formed on the Si substrate 2.
The interlayer insulating film 6 is formed in a state of covering b and the side wall of the semiconductor layer 5a. That is, the semiconductor layer 5a is formed in a state of filling the contact holes 7 reaching the impurity diffusion layers 3 and 3 formed in the interlayer insulating film 6 on the Si substrate 2.

In a semiconductor circuit device having the semiconductor element 1 thus constructed, the semiconductor element 1 is a p-type Si.
Substrate 2, n ⁺ type impurity diffusion layers 3 and 3, and semiconductor layer 5
Since the lateral parasitic npn bipolar transistor is formed by a and the semiconductor element 1, the semiconductor element 1 can be used as an ESD protection circuit element in a semiconductor circuit device.

Next, one embodiment of a method for manufacturing a semiconductor circuit device according to the present invention will be described based on the method for manufacturing a semiconductor circuit device having the semiconductor element 1. Here, a semiconductor circuit including a first semiconductor element configured in the same manner as the semiconductor element 1 except that a silicide layer is formed instead of the electrode layer 5 and a second semiconductor element composed of the semiconductor element 1 A case of manufacturing the device will be described.

First, as a first step, impurities are introduced into the Si substrate 2 on which the field oxide film 4 is formed in advance by, for example, an ion implantation method or the like, and the first and second semiconductor elements are formed in each region. A pair of impurity diffusion layers 3 and 3 are formed on the surface side of the Si substrate 1 in the region. Then, as a second step, after forming a refractory metal film on the surface of the Si substrate 2 by a sputtering method, a silicidation reaction between the Si substrate 2 and the refractory metal is performed by a heat treatment, so that each impurity diffusion layer 3 has a position. A silicide layer is formed on the surface of the Si substrate 2.

Next, in a third step, an interlayer insulating film 6 is formed on the Si substrate 2 in a state of covering the silicide layer, and in a fourth step, a mask for forming a contact hole is formed on the interlayer insulating film 6 by lithography. Form. Then, in a fifth step, the first contact hole reaching the impurity diffusion layer 3 in the region where the first semiconductor element is formed is formed in the interlayer insulating film 6 by etching using the mask, and the second semiconductor is formed. Second contact holes reaching the at least opposite sides of the pair of impurity diffusion layers 3 in the region where the element is formed, that is, the above-mentioned contact holes 7 are formed. By this, the silicide layer 5b of the second semiconductor element is formed.

Then, in a sixth step, with the first contact hole masked, the contact hole 7 is filled with a semiconductor material by, for example, the CVD method. As a result, the electrode layer 5 including the semiconductor layer 5a and the silicide layer 5b is formed in the formation region where the second semiconductor element is formed. Further, a wiring layer made of, for example, aluminum is formed on the interlayer insulating film 6 and the semiconductor layer 5a so as to cover the side wall of the first contact hole. Through the above steps, the first semiconductor element in which the silicide layer is formed on the surface of the Si substrate 2 at the pair of impurity diffusion layers 3 and 3 and the electrode layer on the surface of the Si substrate 2 at the pair of impurity diffusion layers 3 and 3 are formed. A semiconductor circuit device having the second semiconductor element formed with 5, that is, the semiconductor element 1 of the above-described embodiment is manufactured.

In the semiconductor circuit device manufactured as described above, in the semiconductor element 1, the sides of the pair of electrode layers 5 and 5 facing each other, that is, the base side of the npn bipolar transistor is not the silicide layer 5b but the high resistance semiconductor layer. Since it is composed of 5a, that portion has a form in which the resistance is not lowered.

Therefore, when this semiconductor element 1 is used as an ESD protection circuit element in a semiconductor circuit device, the discharge current flowing between the impurity diffusion layers 3 and 3 is less likely to concentrate on the base side of the impurity diffusion layers 3 and 3. Impurity diffusion layers 3, 3
The discharge current density on the base side is equal to that when the impurity diffusion layers 3 and 3 are not silicided. As a result, E of the ESD protection circuit element including the semiconductor element 1
SD withstand voltage is E when a semiconductor element having a diffusion layer that is not silicided is used as an ESD protection circuit element.
Since the breakdown voltage is as high as the SD breakdown voltage, the semiconductor circuit device using the semiconductor element 1 as the ESD protection circuit element is less likely to deteriorate in device characteristics due to electrostatic breakdown.

In the method of manufacturing a semiconductor circuit device described above, the contact hole 7 of the semiconductor element 1 which is the second semiconductor element is formed at the same time when the first contact hole of the first semiconductor element is formed. Since the etching may be performed to the extent that the silicide layer is removed, the semiconductor circuit device having the semiconductor element 1 can be manufactured with the increase in the number of steps being suppressed to the minimum. Therefore, it is possible to manufacture the semiconductor circuit device including the semiconductor element 1 including the silicided diffusion layer and further including the semiconductor element 1 having an excellent ESD breakdown voltage while suppressing an increase in manufacturing cost.

In the above embodiment, the case where a part of each electrode layer 5 is composed of the semiconductor layer 5a has been described, but as shown in FIG. 2, all of the electrode layers 5 are composed of the semiconductor layer 5a. May be. In this case, even if the fourth step and the fifth step of the manufacturing method of the above embodiment are replaced with the self-aligned contact forming process, a semiconductor circuit having a semiconductor element in which each electrode layer 5 is entirely composed of the semiconductor layer 5a. The device can be manufactured. Further, such a semiconductor circuit device is
The same effect as the semiconductor circuit device of the above-described embodiment is obtained.

Further, in the above-mentioned embodiment, the case where the semiconductor material is buried up to the upper part of the contact hole 7 to form the semiconductor layer 5a has been described, but it is sufficient if the semiconductor material is buried at least in the bottom part of the contact hole 7. However, the present invention is not limited to the above embodiment.

Further, in the above embodiment, the semiconductor layer 5a
Was used as a so-called plug for filling the contact hole 7, but it is not always necessary to form the plug. For example, the semiconductor layer 5a in which the contact hole 7 is filled is used as an upper layer wiring together with the wiring layer covering the sidewall of the first contact hole. In this case, the sixth step of the above method may be carried out by covering the side wall of the first contact hole with the semiconductor material or at the same time as filling the contact hole 7 with the semiconductor material. Good. That is, in the sixth step of the method for manufacturing a semiconductor circuit device according to claim 3 of the present invention, a step of forming a wiring layer on the insulating film in a state of covering the sidewall of the first contact hole, and a second step Either of the steps of burying the semiconductor material in at least the bottom of the contact hole may be performed first, or these steps may be performed simultaneously. When these first and second semiconductor elements are connected to the upper aluminum wiring layer or the like, they may be directly connected to the silicide layer of the first semiconductor element by a separate process, or the semiconductor layer of the second semiconductor element. 5
It may be connected to a or the silicide layer 5b.

Next, a second embodiment of the semiconductor circuit device of the present invention will be described with reference to FIG. This embodiment differs from the first embodiment in that the semiconductor element in the semiconductor circuit device is a MOSFET.

That is, p as the semiconductor substrate of the present invention
A field oxide film 12 is formed on the surface of the Si substrate 11 of the mold so as to surround a region forming the MOSFET 10. A gate electrode 14 is formed in a region surrounded by the field oxide film 12 via a gate oxide film 13. Has been formed.
A side wall insulating film 15 is formed on the side wall of the gate electrode 14, and source and drain diffusion layers 16 and 16 which are n ⁺ type impurity diffusion layers are formed on the surface side of the Si substrate 11 on both sides of the gate electrode 14. Are formed respectively. Then, similarly to the above-described first embodiment, the electrode layer 17 including the semiconductor layer 17a made of a semiconductor material and the silicide layer 17b is formed on the surface of the Si substrate 11 at each of the source and drain diffusion layers 16 and 16 positions. In addition, the interlayer insulating film 18 is formed on the Si substrate 11.

In the MOSFET 10 thus constructed,
In addition, the p-type Si substrate 11 and the n-type ⁺Dose of type
By the in-diffusion layers 16 and 16 and the semiconductor layer 17a,
A lateral parasitic npn bipolar transistor
MOSFET 10 is used because it is made
Used as an ESD protection circuit element in semiconductor circuit devices
Can be. And the ESD protection circuit element in this case
The ESD withstand voltage of the child is the same as that of the first embodiment.
MOSFET that does not introduce salicide structure
As high as that of the ESD protection circuit element consisting of
Become.

Further, the MOSFET 10 is used as a second semiconductor element, and a silicide layer is formed in place of the electrode layer 17 of the second semiconductor element, that is, an MO of salicide structure.
Even when manufacturing a semiconductor circuit device having an SFET as the first semiconductor element, as in the method of the above embodiment, the S
After the interlayer insulating film 18 is formed on the i substrate 11, the first contact hole of the first semiconductor element and the contact hole 19 for forming the semiconductor layer 17a in the MOSFET 10 are simultaneously formed in the interlayer insulating film 18 using the same mask. Can be formed. Therefore, the salicide structure MOS
It is possible to manufacture a semiconductor circuit device including a semiconductor element which uses an FET and has an excellent ESD withstand voltage while minimizing an increase in the number of steps.

[0033]

As described above, the semiconductor element which constitutes the semiconductor circuit device of the present invention comprises a parasitic bipolar transistor, and a high resistance semiconductor layer is formed on the base side of the bipolar transistor. Therefore, when this semiconductor element is used as an ESD protection circuit element, the discharge current does not have a high density on the base side of the impurity diffusion layer of the semiconductor element, so that the ESD breakdown voltage is not reduced by the alloying diffusion layer. When the semiconductor element provided with is used as an ESD protection circuit element, the ESD withstand voltage is as high as that. Therefore, since the semiconductor circuit device of the present invention includes a semiconductor element having an excellent ESD withstand voltage even when using a semiconductor element including a diffusion layer having a low resistance, the device characteristics due to electrostatic breakdown are high. Is less likely to deteriorate.

In the method for manufacturing a semiconductor circuit device according to the present invention, the first contact hole of the first semiconductor element is formed and at the same time the second contact hole for forming the semiconductor layer of the second semiconductor element is formed. Since the first semiconductor element and the second semiconductor element can be formed while minimizing the increase in the number of steps, a semiconductor element having a diffusion layer whose resistance is reduced by alloying is used, and an excellent ESD withstand voltage is obtained. A semiconductor circuit device including the semiconductor element can be manufactured while suppressing an increase in manufacturing cost.

[Brief description of drawings]

FIG. 1 is an explanatory view showing a first embodiment of a semiconductor circuit device of the present invention, (a) is a plan view of a main part, and (b) is a side sectional view of the main part.

FIG. 2 is a side sectional view of an essential part of a semiconductor element in the semiconductor circuit device according to the first embodiment when all electrode layers are formed of semiconductor layers.

FIG. 3 is a side sectional view of an essential part showing a second embodiment of the semiconductor circuit device of the present invention.

FIG. 4 is a circuit diagram of a conventional ESD protection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 semiconductor element (second semiconductor element) 2, 11 Si substrate (semiconductor substrate) 3 impurity diffusion layers 5, 17 electrode layers 5a, 17a semiconductor layers 5b, 17b silicide layers 6, 18 interlayer insulating film 7, 19 contact hole (first 2 contact hole) 10 MOSFET (semiconductor element) 16 source / drain diffusion layer (impurity diffusion layer)

Claims (3)

[Claims] 1. A semiconductor element comprising a pair of impurity diffusion layers formed on a surface layer side of a semiconductor substrate, and an electrode layer formed on the surface of the semiconductor substrate at each of the pair of impurity diffusion layers, A semiconductor circuit device, wherein the electrode layers are semiconductor layers made of a semiconductor material at least on opposite sides. 2. The pair of impurity diffusion layers are a source diffusion layer and a drain diffusion layer, and the semiconductor element is MO.
The semiconductor circuit device according to claim 1, wherein the semiconductor circuit device is an S-type transistor. 3. A pair of impurity diffusion layers are formed on the surface side of the semiconductor substrate, and an alloyed layer of the semiconductor substrate and a refractory metal is formed on the surface of the semiconductor substrate at each position of the pair of impurity diffusion layers. A first semiconductor element formed by:
A pair of impurity diffusion layers are formed on the surface side of the semiconductor substrate, and an electrode layer is formed on the surface of the semiconductor substrate at each position of the pair of impurity diffusion layers, and at least the electrode layers face each other. A method of manufacturing a semiconductor circuit device having a second semiconductor element whose side is a semiconductor layer made of a semiconductor material, comprising: a first step of forming a plurality of pairs of impurity diffusion layers on a surface side of the semiconductor substrate; A second step of forming an alloyed layer of the semiconductor substrate and a refractory metal on the surface of the semiconductor substrate at each diffusion layer position; and forming an insulating film on the semiconductor substrate in a state of covering the alloyed layer. A third step, a fourth step of forming a mask for forming a contact hole on the insulating film, and an etching process using the mask to form a mask on the insulating film.
Forming a first contact hole reaching the impurity diffusion layer in a region where the first semiconductor element is formed,
A fifth step of forming a second contact hole reaching at least opposite sides of the pair of impurity diffusion layers in a region where the second semiconductor element is formed; and the insulating in a state of covering a sidewall of the first contact hole. A method for manufacturing a semiconductor circuit device, comprising: a step of forming a wiring layer on the film; and a sixth step of burying a semiconductor material in at least the bottom of the second contact hole.