JPH0982640A - Compound semiconductor substrate and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration in characteristics of a semiconductor device by relieving the stress caused by the multilayer epitaxial film structure, interlayer insulating film, etc., to suppress the warp and defects on a substrate. SOLUTION: In this compound semiconductor substrate 11 wherein a compound semiconductor layer 13 is epitaxially grown on a silicon substrate 12 plural semiconductor elements 10 are formed on the compound semiconductor layer 13, a sectional V shaped grooves 14 are formed on the boundary parts of the regions forming the semiconductor elements 10. Furthermore, the compound semiconductor layer 13 is continuously formed also in the grooves 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor substrate suitable for use in a metal semiconductor field effect transistor.

[0002]

2. Description of the Related Art Metal semiconductor field effect transistors (MESFETs)
As the ansistor]), a structure having a structure shown in FIG. 6 is conventionally known. In FIG. 6, reference numeral 1 is MESFE.
The MESFET 1 is a T-type semiconductor device, and the MESFET 1 has an n-G structure on a compound semiconductor substrate 4 formed by epitaxially growing an i-GaAs layer 3 which is a compound semiconductor layer on a silicon substrate 2.
An aAs layer 5 and an n ⁺ -GaAs layer 6 are epitaxially grown in this order, and an ohmic source electrode 7 and a drain electrode 8 are further formed on the n ⁺ -GaAs layer 6 to form an n-G layer.
A gate electrode 9 which is a Schottky electrode is formed on the aAs layer 5.

A part of the n ⁺ -GaAs layer 6 is etched to expose the underlying n-GaAs layer 5, and the gate electrode 9 is formed on the exposed portion to form the gate electrode 9. Is n-GaA as described above.
It is formed on the s layer 5. With this configuration, the MESFET 1 has a structure in which a voltage is applied to the gate electrode 9 to control the current between the source electrode 7 and the drain electrode 8.

[0004]

However, the above M
In ESFET1, GaAs is formed on the silicon substrate 2.
-Based compound semiconductor layer, i.e., i-GaAs layer 3, n-G
Since the aAs layer 5 and the n ⁺ -GaAs layer 6 are epitaxially grown, the multi-layer epitaxial film structure and the stress of the interlayer insulating film and the like formed on the electrodes 7, 8 and 9 which are not shown in FIG. As a result, warpage and defects occur in the silicon substrate 2. If such warpage or defects occur, the characteristics of the MESFET 1 will deteriorate.

The present invention has been made in view of the above circumstances. An object of the present invention is to alleviate the stress caused by the multilayer epitaxial film structure, the interlayer insulating film, etc., so that the substrate is warped or defective. It is an object of the present invention to provide a compound semiconductor substrate capable of suppressing the deterioration of the characteristics of a semiconductor device by suppressing the above.

[0006]

In the compound semiconductor substrate of the present invention, a groove having a V-shaped cross section is formed in a boundary portion of a region for forming a semiconductor element on a silicon substrate, and a compound semiconductor layer is formed in the groove. The continuous formation is also considered as the means for solving the above-mentioned problems. According to such a compound semiconductor substrate, the groove having a V-shaped cross section relaxes the stress of the compound semiconductor layer and the stress of the interlayer insulating film formed thereon, so that a warp or a defect occurs in the silicon substrate. Is suppressed.

In the method of manufacturing a compound semiconductor substrate of the present invention, a predetermined portion of the (100) plane of the crystal structure of the silicon substrate is anisotropically etched to form a V-shaped cross section at the predetermined portion of the silicon substrate. The method for forming the groove is provided, and the step of epitaxially growing the compound semiconductor layer on the surface of the silicon substrate on which the groove is formed is provided as the means for solving the problems. According to such a method of manufacturing a compound semiconductor substrate, by utilizing the etching rates of the (100) plane and the (111) plane on the crystal structure of the silicon substrate, the (100) plane of the silicon substrate is anisotropically etched. A groove having a V-shaped cross section can be easily formed on the surface. Then, since the compound semiconductor layer is epitaxially grown on the surface in which such a groove is formed, the stress of the compound semiconductor layer and the stress of the interlayer insulating film formed thereon are relaxed by the groove having the V-shaped cross section. As a result, it becomes possible to suppress the occurrence of warpage and defects in the silicon substrate.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to its embodiments. FIG. 1 is a diagram showing a schematic structure of a MESFET formed by using the compound semiconductor substrate of the present invention. In FIG. 1, reference numeral 10 is an ME called GaAsFET.
SFET, 11 is a silicon substrate (silicon wafer) 12
And a i-GaAs layer (compound semiconductor layer) 13 formed thereon, which is a compound semiconductor substrate. In addition, in FIG. 1 and FIGS. 3A to 3C described later, the thickness of each layer and the depth of the V-groove are completely different from the actual ones for the sake of clarity, and therefore the relative values thereof are not shown. The present invention is not limited to the description of the drawings in terms of size and the like.

The compound semiconductor substrate 11 is arranged so that the crystal structure of the silicon substrate 12 is such that the surface on which the i-GaAs layer 13 is formed is the (100) plane. A large number of grooves having a V-shaped cross section (hereinafter, referred to as V grooves) 14 are formed on the surface on which the grooves are formed. Here, in the V-grooves 14 ..., The (111) plane that is oblique to the (100) plane is exposed by the anisotropic etching of the silicon substrate 12 as described later, and as a result, the cross section V It is formed in a V-shaped groove. Further, these V grooves 14 ...
The MESFETs 10 ... Formed on the GaAs layer 13 are formed and arranged at the boundaries of the unit regions, and have an opening width of about 400 μm and a depth of about 300 μm.

The i-GaAs layer 13 functions as a semi-insulating substrate, and is epitaxially grown on the silicon substrate 12 to have a thickness of about 0.3 μm. Here, the i-GaAs layer 13 is naturally formed continuously in the V-groove 14 of the silicon substrate 12, and as described above, is formed with a film thickness sufficiently smaller than the depth of the V-groove 14. It was done. In addition, i-GaA
On the s layer 13, the conventional MESFET 1 shown in FIG.
Similarly to n-GaAs layer 15 and n ⁺ -GaAs layer 16
Are formed in this order by epitaxial growth. The n-GaAs layer 15 functions as an operating layer of the MESFET 10, and the n ⁺ -GaAs layer 16 is also provided.
Is the source electrode 17 and the drain electrode 1 formed on this
It was formed in order to ensure ohmic contact with No. 8. The n ⁺ -GaAs layer 16 is partially etched as in the conventional MESFET 1 shown in FIG.
The lower n-GaAs layer 4 is exposed, and the gate electrode 19 is formed on this exposed portion, so that the gate electrode 19 is formed on the n-GaAs layer 17, as described above. There is.

Source electrode 17 and drain electrode 18
Are laminated electrodes made of (AuGe / Ni / Au), and the gate electrode 19 is made of (Ti / Pt / A).
u) is a laminated electrode. In the unit area of the MESFET 10 defined by the V groove 14, the V
Isolation portions 20 are formed inside the grooves 14, respectively. The isolation section 20 is for element isolation, and is formed by implanting O ⁺ ions into the n ⁺ -GaAs layer 16 and the n-GaAs layer 15 as described later. Although not shown, the source electrode 17, on the n ⁺ -GaAs layer 16,
An interlayer insulating film is formed so as to cover the drain electrode 18 and the gate electrode 19. Then, the MESFET 10 for each unit is diced at a position above the V groove 14.
Is formed.

Next, the MESFET 10 having such a configuration
The manufacturing method of the compound semiconductor substrate of the present invention will be described based on the manufacturing method of. First, the crystal structure of the upper surface is (10
A silicon substrate (silicon wafer) 12 which is a (0) surface is prepared, and an oxide film [SiO _x ] (not shown) is deposited and formed on the upper surface of the silicon substrate 12 by a plasma CVD method. Next, a resist layer (not shown) is formed on the oxide film, and the resist layer is patterned by a known lithographic technique to form the V groove 14, that is, the MES.
A resist pattern (not shown) having an opening at the boundary of the region forming the structure of the FET 10 is formed.

Next, the oxide film is etched by using the formed resist pattern as a mask, and a boundary portion of a region in the oxide film where the structure of the MESFET 10 is formed is opened in a groove shape having a width of about 400 μm. Then, using the oxide film after this etching as a mask, using a KOH aqueous solution,
Anisotropic etching is performed by immersing the surface on which the oxide film is formed, that is, the (100) surface side of the silicon substrate 12 in the KOH aqueous solution. When anisotropic etching is performed in this manner, the silicon substrate 12 is at an angle of about 55 ° with respect to the (100) plane on the crystal structure (11
Since the etching rate of the 1) plane is as low as 1/200, the (100) plane of the silicon substrate 12 is etched to expose the (111) plane, which results in a V-shaped cross section as shown in FIG. , The V groove 14 is formed. After completing this anisotropic etching, H
The oxide film used as the mask is removed by the aqueous solution of F, and as a result, the silicon substrate 12 having the V-grooves 14 ...

Then, as shown in FIG. 3B, i-GaAs is formed on the silicon substrate 12 having the V-grooves 14 ...
The layer 13 is epitaxially grown to a thickness of about 0.3 μm, and then an n-GaAs layer 15 is formed on the layer 13 by 50 to 15 nm.
Epitaxial growth is performed to a thickness of about 0 nm, and an n ⁺ -GaAs layer 16 is further epitaxially grown thereon to a thickness of about 50 nm. Specifically, as the epitaxial growth, trimethylgallium ((CH ₃ ) ₃ Ga; TMG) and arsine (A) are used for the i-GaAs layer 13.
sH ₃ ) is used as a source gas to grow by MOCVD (metal organic chemical vapor deposition). In addition, the n-type GaAs layer 1
Regarding Nos. 5 and 16, SiH ₄ gas was added to the source gas in the MOCVD method described above to grow Si by doping Si.

Next, in order to perform element isolation, O ⁺ ions are implanted into necessary portions, that is, both sides of the V groove 14 in this example by a known resist method, and isolation is performed to form an isolation portion 20. Next, a resist pattern is formed at positions other than the positions where the source electrode 17 and the drain electrode 18 are formed, and AuGe /
Ni / Au was subjected to electron beam evaporation (EB evaporation), and then the resist pattern was removed by lift-off.
As shown in (c), the source electrode 17 is provided only at a predetermined position,
The drain electrode 18 is formed.

Next, a predetermined position of the n ⁺ -GaAs layer 16 is etched to form a recess structure, and the gate electrode 1
A resist turn is formed except for the position where 9 is formed, and Ti / Pt / Au is electron beam evaporated (EB evaporated) in that state.
I do. Then, by lifting off, as shown in FIG.
As shown in, the gate electrode 19 is formed only at a predetermined position. After that, these source electrode 17 and drain electrode 18
An interlayer insulating film (not shown) is formed to cover the gate electrode 19 and the gate electrode 19, and the single MESFET 10 as shown in FIG. obtain.

In the compound semiconductor substrate 11 used in the MESFET 10 as described above, the V groove 14 ...
Is the stress of the i-GaAs layer 13 (compound semiconductor layer) or n-
Since the stress of the GaAs layer 15, the n ⁺ -GaAs layer 16 and the interlayer insulating film formed thereon is relieved, the silicon substrate 12 can be prevented from being warped or defective. It is possible to prevent the characteristic deterioration of the MESFET 10 formed on the compound semiconductor substrate 11 due to the warpage and defects. In addition, the V groove 14 is i-G
Since it is formed deeper than the thickness of the aAs layer 13,
A groove portion corresponding to the V groove 14 is also formed in the i-GaAs layer 13, so that the stress of the n-GaAs layer 15 and the n ⁺ -GaAs layer 16 formed on the i-GaAs layer 13 is also relaxed. can do.

Further, when the compound semiconductor substrate 11 is diced after the MESFET 10 is formed, since the V-grooves 14 ... Are arranged at the boundary portion of the formation region of the MESFET 10 in the compound semiconductor substrate 11, the V-groove is particularly used. 14 is formed deeper than the thickness of the i-GaAs layer 13, the n ⁺ -GaAs layer 1 formed thereon
Since the groove is formed on the groove 6, the dicing process itself can be facilitated by dicing the groove. In addition, in the method of manufacturing the compound semiconductor substrate 11 as described above, the stress of the i-GaAs layer 13 (compound semiconductor layer) and the interlayer insulating film formed thereon are further formed by forming the V grooves 14. The stress of 1 can be relaxed, and as a result, warpage and defects in the silicon substrate 12 can be suppressed.

In the above example, the silicon substrate 12 was anisotropically etched using a KOH aqueous solution, but the present invention is not limited to this. For example, alkaline ones such as hydrazine and EPW (ethylenediamine-) are used. Anisotropic etching can also be performed using Pitecatechol-water), TMAH (tetramethylammonium hydroxide), or the like. Further, in the above example, only the i-GaAs layer 13 was used as the compound semiconductor layer of the present invention.
The n-GaAs layer 15 may be added thereto to form a compound semiconductor layer, and the n ⁺ -GaAs layer 16 may be added to form a compound semiconductor layer.

[0020]

As described above, in the compound semiconductor substrate of the present invention, the groove having a V-shaped cross section relieves the stress of the compound semiconductor layer and the stress of the interlayer insulating film formed thereon. It is possible to suppress warpage and defects from occurring in the silicon substrate, and thereby prevent characteristic deterioration of the semiconductor element formed on the compound semiconductor substrate due to the warpage and defects.

In addition, the method of manufacturing a compound semiconductor substrate of the present invention utilizes the etching rates of the (100) plane and the (111) plane on the crystal structure of the silicon substrate, whereby anisotropic etching of the silicon substrate is performed. (10
Since a groove having a V-shaped cross section can be easily formed on the (0) plane, the cross section V can be formed by epitaxially growing a compound semiconductor layer on the surface on which such a groove is formed. The V-shaped groove can relieve the stress of the compound semiconductor layer and the stress of the interlayer insulating film formed thereon, thereby suppressing warpage and defects in the silicon substrate.

[Brief description of drawings]

FIG. 1 is a MESFE using the compound semiconductor substrate of the present invention.
It is a principal part side sectional view which shows schematic structure of T.

FIG. 2 is a side sectional view showing the shape of a V groove.

3 (a) to 3 (c) are cross-sectional views of the main part for explaining the method of manufacturing the MESFET shown in FIG. 1 in the order of steps.

FIG. 4 is a plan view for explaining a state of a V groove formed on a silicon substrate.

FIG. 5 is an enlarged plan view showing a state of a single MESFET.

FIG. 6 is a side sectional view of a main part showing a schematic configuration of a conventional MESFET.

[Explanation of symbols]

10 MESFET 11 compound semiconductor substrate 12 silicon substrate 13 i-GaAs layer (compound semiconductor layer) 14 V groove 15 n-GaAs layer 16 n ⁺ -GaAs layer

Claims (3)

[Claims] 1. A compound semiconductor substrate in which a compound semiconductor layer is epitaxially grown on a silicon substrate and a plurality of semiconductor elements are formed on the compound semiconductor layer, wherein a region of the silicon substrate where the semiconductor element is formed. A groove having a V-shaped cross section is formed at a boundary portion of the compound semiconductor layer, and the compound semiconductor layer is continuously formed in the groove. 2. The compound semiconductor substrate according to claim 1, wherein the groove is formed deeper than the thickness of the compound semiconductor layer. 3. A crystalline structure of (10) on a silicon substrate.
0) plane is anisotropically etched to form a groove having a V-shaped cross section at a predetermined position of the silicon substrate, and a compound semiconductor layer is formed on the surface of the silicon substrate on which the groove is formed. And a step of epitaxially growing the compound semiconductor substrate.