JPH098258A - Manufacture of soi substrate - Google Patents

Manufacture of soi substrate

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Publication number
JPH098258A
JPH098258A JP17157395A JP17157395A JPH098258A JP H098258 A JPH098258 A JP H098258A JP 17157395 A JP17157395 A JP 17157395A JP 17157395 A JP17157395 A JP 17157395A JP H098258 A JPH098258 A JP H098258A
Authority
JP
Japan
Prior art keywords
substrate
active layer
layer
thickness
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17157395A
Other languages
Japanese (ja)
Other versions
JP2663923B2 (en
Inventor
Atsushi Ogura
厚志 小椋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17157395A priority Critical patent/JP2663923B2/en
Publication of JPH098258A publication Critical patent/JPH098258A/en
Application granted granted Critical
Publication of JP2663923B2 publication Critical patent/JP2663923B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE: To reduce the thickness of the active layer of a multilayered SOI substrate with high accuracy by a simple method. CONSTITUTION: After an Si oxide film 20 having a thickness of about 1μm is formed by thermally oxidizing an Si substrate which becomes the origin of an active layer 30, an SOI substrate is manufactured by putting the film 20 on another Si substrate which becomes a supporting substrate 10 and joining the film 20 to the substrate 10 through heat treatment. The thickness of the active layer 30 of the multilayer SOI substrate is reduced by polishing the layer 30 by using a chemimechanical polishing method. Then the active layer 30 is etched by using such an etchant as a mixture of hydrofluoric acid and nitric acid, etc., while the layer 30 is irradiated with light. At the thicker part of the layer 30, more carrier are generated and the etching is accelerated by the carriers. As the layer 30 becomes thinner, the light starts to reach the supporting substrate 10 side through the layer 30 and the produced amount of carriers becomes less, lowering the etching rate. Therefore, the thickness of the layer 30 is uniformized. In addition, the thickness of the layer 30 can be controlled by changing the wavelength of the irradiating light.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体基板上に絶縁膜
を介して半導体層が形成されたSOI(Sion insulato
r または Semiconductor on insulator )基板の製造方
法に関し、特に、貼り合わせ法によるSOI基板の活性
層側半導体基板の薄層化技術に関するものである。
The present invention relates to an SOI (Sion Insulato) in which a semiconductor layer is formed on a semiconductor substrate via an insulating film.
The present invention relates to a method for manufacturing a substrate, and more particularly, to a technique for thinning an active layer side semiconductor substrate of an SOI substrate by a bonding method.

【0002】[0002]

【従来の技術】絶縁膜上に半導体活性層を有するSOI
基板の形成方法の1つに、貼り合わせ法がある。この方
法では、2枚のシリコン基板の少なくとも一方を酸化し
て絶縁体であるシリコン酸化膜を形成し、シリコン酸化
膜を間に挟む配置で重ね合わせた後に熱処理を加えて貼
り合わせ、さらに活性層となるシリコン基板を薄層化す
る。この方法では、もともと単結晶であるシリコン基板
を薄層化するので、活性層の結晶性が極めてよいSOI
構造が得られる。
2. Description of the Related Art SOI having a semiconductor active layer on an insulating film
One of the methods for forming a substrate is a bonding method. In this method, at least one of the two silicon substrates is oxidized to form a silicon oxide film which is an insulator, and the silicon oxide films are stacked in an interposed position, and then heat-treated to be bonded. Of the silicon substrate to be thinned. In this method, the silicon substrate, which is originally a single crystal, is thinned, so that the SOI having extremely good crystallinity of the active layer
The structure is obtained.

【0003】従来、この活性層の薄層化の方法として
は、例えばジャーナル・オブ・エレクトリック・マテリ
アル21巻669頁〜676頁、1992年(Journal
of Electronic Material, Vol.21, No.7, pp.669-676,
1992)に詳しいが、化学機械的に研磨する方法や、エピ
タキシャル層をエッチストップに用いるエッチング法が
行われている。
Conventionally, as a method of thinning the active layer, for example, Journal of Electric Materials, Vol. 21, pp. 669-676, 1992 (Journal)
of Electronic Material, Vol.21, No.7, pp.669-676,
1992), a chemical mechanical polishing method and an etching method using an epitaxial layer as an etch stop are performed.

【0004】前者は、回転する研磨定盤上に研磨材(ス
ラリー)滴下しながら基板を押し付けて研磨する方法で
あり、後者は、高不純物濃度層/アンドープ層やSi層
/Si・Ge層/Si層等のエッチング性の異なる複数
の層をエピタキシャル成長させた後、そのエピタキシャ
ル層側を表にして支持基板に貼り付け、エッチングする
方法である。
The former method is a method in which a polishing material (slurry) is dripped onto a rotating polishing table and the substrate is pressed and polished, and the latter is a method in which a high impurity concentration layer / undoped layer or a Si layer / Si.Ge layer / In this method, a plurality of layers having different etching properties, such as a Si layer, are epitaxially grown, and the epitaxial layer is attached to a support substrate with its epitaxial layer side facing up and etched.

【0005】さらに、例えば1992年アイトリプルイ
ー・インターナショナル・SOIコンファレンス・プロ
シーディング152頁〜153頁(1992 IEEE Internat
ional SOI Conference Proceedings, pp.152-153)に
は、化学機械的に研磨した後に活性層膜厚を精密に測定
し、局所的なプラズマエッチングで厚い領域を他の領域
に比べて長くエッチングする方法を採用するこにより、
精度の高い活性層を形成できることが報告されている。
[0005] Further, for example, in 1992 I Triple E International SOI Conference Proceedings, pp. 152-153 (1992 IEEE Internat
ional SOI Conference Proceedings, pp.152-153), there is a method to precisely measure the thickness of the active layer after chemical mechanical polishing, and to etch the thicker region longer by local plasma etching than the other regions. By adopting
It is reported that a highly accurate active layer can be formed.

【0006】[0006]

【発明が解決しようとする課題】上述した従来技術のう
ち、化学機械研磨法を用いるものでは、均一な膜厚を得
ることが難しく、この方法で得られる典型的な活性層膜
厚と均一性は、例えば3μm±0.5μmであり結果的
に高品質な電子デバイスに有用な薄膜(例えば0.1μ
m±0.01μm)の形成はできなかった。また、エピ
タキシャル成長基板を用いる方法や局所的プラズマエッ
チング法を用いるものでは、いずれもプロセスが複雑に
なるため極めて高価なものになるという欠点があった。
Among the above-mentioned prior arts, the one using the chemical mechanical polishing method has difficulty in obtaining a uniform film thickness, and the typical active layer film thickness and uniformity obtained by this method are difficult. Is, for example, 3 μm ± 0.5 μm, and as a result, a thin film (eg, 0.1 μm
m ± 0.01 μm) could not be formed. Further, the method using an epitaxial growth substrate or the method using a local plasma etching method has a drawback that the process becomes complicated and extremely expensive.

【0007】したがって、本発明の目的とするところ
は、貼り合わせSOI基板の活性層の薄層化において、
複雑なプロセスを使用することなく精度の高い加工を可
能ならしめることであり、このことにより、結晶性のよ
い貼り合わせSOI基板の特長を活かして高性能の電子
デバイスを形成することのできる基板を低コストで提供
できるようにしようとするものである
Therefore, an object of the present invention is to reduce the thickness of the active layer of a bonded SOI substrate by reducing the thickness of the active layer.
This is to enable high-precision processing without using complicated processes, and this enables a substrate capable of forming a high-performance electronic device by utilizing the characteristics of a bonded SOI substrate having good crystallinity. Try to make it available at low cost

【0008】[0008]

【課題を解決するための手段】上記の目的を達成するた
めの本発明によるSOI基板の製造方法は、(1)支持
基板と活性層を構成するシリコン基板とを何れかの基板
に形成された絶縁膜を介して接着する工程と、(2)前
記活性層となるシリコン基板表面に光を入射して該シリ
コン基板内にキャリアを生成しながら該シリコン基板を
湿式またはドライ法にてエッチングする工程と、を備え
るものであり、あるいは、(1)支持基板と活性層を構
成するシリコン基板とを何れかの基板に形成された絶縁
膜を介して接着する工程と、(2)前記活性層となるシ
リコン基板表面に光を入射し該シリコン基板内にキャリ
アを生成しながら該シリコン基板に化学的もしくは電気
化学的な反応を起こさせて該シリコン基板表面に反応生
成物層を形成する工程と、(3)前記反応生成物層をエ
ッチング除去する工程と、を備えるものである。
According to the present invention, there is provided a method for manufacturing an SOI substrate, comprising the steps of: (1) forming a supporting substrate and a silicon substrate constituting an active layer on any one of substrates; Adhering via an insulating film; and (2) etching the silicon substrate by a wet or dry method while irradiating light to the surface of the silicon substrate to be the active layer to generate carriers in the silicon substrate. Or (1) a step of bonding a supporting substrate and a silicon substrate constituting an active layer via an insulating film formed on any one of the substrates, and (2) a step of bonding the active layer to the silicon substrate. Light is incident on the surface of the silicon substrate to generate a carrier in the silicon substrate and cause a chemical or electrochemical reaction on the silicon substrate to form a reaction product layer on the surface of the silicon substrate. And extent are those comprising, removing etching (3) said reaction product layer.

【0009】[0009]

【作用】半導体を化学的にエッチングする溶液(例えば
弗硝酸系、KOH系、ヒドラジン系溶液等)のほとんど
すべて、さらに一部のガス(プラズマを含む)によるエ
ッチングでは、そのエッチング速度は被加工物である半
導体中のキャリア(電子および正孔)の有無あるいはそ
の濃度に大きく依存する。また、多くの化学的あるいは
電気化学的な反応(例えば、酸化や陽極化成等)も、同
様にキャリアの量の多少がその反応速度に大きく影響を
与える。
The etching rate of almost all of the solutions for chemically etching semiconductors (for example, fluorinated nitric acid, KOH, and hydrazine solutions, etc.) and a part of the gas (including plasma) is not affected by the etching rate. Depends largely on the presence or concentration of carriers (electrons and holes) in the semiconductor. Also, in many chemical or electrochemical reactions (eg, oxidation and anodization), the amount of the carrier has a large influence on the reaction rate.

【0010】SOI基板活性層に所望の膜厚に対応した
波長の光を照射すると、活性層中に電子−正孔対が生成
する。エッチングが進行し、活性層のうち所望の膜厚に
達した領域では照射光が活性層で吸収されずに支持基板
側に突き抜け、電子−正孔対の生成に寄与しなくなる。
したがって、所望の膜厚に達した領域でエッチング速度
が低下し、均一な超薄膜活性層が得られる。また、化学
的あるいは電気化学的な反応により反応生成物を形成す
る際にも、同様に残りの活性層厚が所定の値に達した領
域では照射光は支持基板側へ突き抜け、電子−正孔対が
生成されなくなる。
When the SOI substrate active layer is irradiated with light having a wavelength corresponding to a desired film thickness, electron-hole pairs are generated in the active layer. Irradiation light is not absorbed by the active layer but penetrates to the support substrate side in a region of the active layer which has reached a desired thickness as etching proceeds, and does not contribute to generation of electron-hole pairs.
Therefore, the etching rate decreases in the region where the desired film thickness is reached, and a uniform ultrathin film active layer can be obtained. Also, when a reaction product is formed by a chemical or electrochemical reaction, similarly, in a region where the remaining active layer thickness has reached a predetermined value, irradiation light penetrates to the support substrate side, and electron-hole No pairs are generated.

【0011】以下に一例として弗硝酸系溶液(HF/H
NO3 /CH3 COOH混合溶液)を用いた化学的エッ
チングで、キャリアの存在がエッチ速度に影響を与える
メカニズムをより具体的に説明する。CH3 COOHを
緩衝剤として用いた、HF/HNO3 溶液でSiのエッ
チングを行う場合には、以下の(1)〜(3)式で示す
一連の反応によりエッチングが進行する。 Si+2h+ →Si2+ (1) Si2++2OH- →SiO2 +H2 (2) SiO2 +6HF→H2 SiF6 (水溶性)+2H2 O (3)
As an example, a fluorinated nitric acid solution (HF / H
The mechanism by which the presence of carriers affects the etching rate in chemical etching using a mixed solution of NO 3 / CH 3 COOH) will be described more specifically. When etching Si using an HF / HNO 3 solution using CH 3 COOH as a buffer, the etching proceeds by a series of reactions represented by the following equations (1) to (3). Si + 2h + → Si 2+ (1) Si 2+ + 2OH → SiO 2 + H 2 (2) SiO 2 + 6HF → H 2 SiF 6 (water-soluble) + 2H 2 O (3)

【0012】(1)式に示されるように、キャリア(こ
の場合はホール)の存在が、エッチングの進行に大きな
役割を果たす。したがって、エッチングが進行し照射し
た光が突き抜ける膜厚に達した時に、ホールが不足する
ことでエッチング速度が自動的に低下しエッチストップ
のメカニズムが働く。これにより、所望の膜厚の活性層
を高い精度で形成することができる。
As shown in equation (1), the presence of carriers (holes in this case) plays a large role in the progress of etching. Therefore, when the etching proceeds and reaches a film thickness through which the irradiated light can penetrate, the etching rate is automatically reduced due to the shortage of holes, and an etch stop mechanism operates. Thereby, an active layer having a desired film thickness can be formed with high accuracy.

【0013】[0013]

【実施例】次に、本発明の実施例について図面を参照し
て詳細に説明する。 [第1の実施例]図1(a)、(b)は、本発明の第1
乃至第3の実施例を説明するための工程順断面図であ
る。貼り合わせSOI基板は、活性層30の元となるp
型Si基板(比抵抗1〜3Ω・cm)を熱酸化して厚さ
約1μmのSi酸化膜20を形成した後、これを支持基
板10となるp型Si基板(比抵抗1〜3Ω・cm、厚
さ625μm)と重ね合わせ熱処理を加えて貼り合わせ
て作製した。貼り合わせ基板作製後、活性層30を通常
の化学機械的な研磨(Chemical Mechanical Polishing:
CMP)で膜厚3〜5μm、膜厚精度±0.5μmまで
薄膜化した。図1(a)は、この方法で得たSOI基板
の状態を示す断面図であり、化学機械的研磨法により形
成した従来の貼り合わせSOI基板と同等のものであ
る。
Next, embodiments of the present invention will be described in detail with reference to the drawings. [First Embodiment] FIGS. 1A and 1B show a first embodiment of the present invention.
FIG. 9 is a process order cross-sectional view for explaining the third to third embodiments. The bonded SOI substrate has p
A silicon oxide film 20 having a thickness of about 1 μm is formed by thermally oxidizing a Si-type Si substrate (specific resistance: 1 to 3 Ω · cm), and this is then converted to a p-type Si substrate (specific resistance: 1 to 3 Ω · cm) serving as a support substrate 10. , 625 μm in thickness) and heat treatment for superposition was applied to produce a laminate. After the production of the bonded substrate, the active layer 30 is subjected to ordinary chemical mechanical polishing (Chemical Mechanical Polishing:
The thickness was reduced to 3 to 5 μm with a thickness accuracy of ± 0.5 μm by CMP). FIG. 1A is a sectional view showing a state of an SOI substrate obtained by this method, which is equivalent to a conventional bonded SOI substrate formed by a chemical mechanical polishing method.

【0014】次に、Wランプ光を照射しながら、混合比
1:3:10のHF/HNO3 /CH3 COOH混合溶
液でエッチングを行った。エッチングは約10〜30分
進行した後に自動的に停止し、均一膜厚の活性層40が
得られた〔図1(b)〕。光学的膜厚測定機で測定した
半導体活性層膜厚は約0.5μm、その精度は±0.0
1μmであった。また、上記の混合溶液中の純粋なCH
3 COOHの代わりにヨウ素を飽和したCH3 COOH
を用いた混合溶液によるエッチングも行った。この場合
には、純粋なCH3 COOHを加えた溶液を用いた場合
に比べて、エッチング終了後の試料表面の平坦性が優れ
ていた。
Next, while irradiating the W lamp light, etching was performed with a HF / HNO 3 / CH 3 COOH mixed solution having a mixing ratio of 1: 3: 10. The etching was automatically stopped after proceeding for about 10 to 30 minutes, and an active layer 40 having a uniform thickness was obtained [FIG. 1 (b)]. The thickness of the semiconductor active layer measured by an optical film thickness measuring device is about 0.5 μm, and the accuracy is ± 0.0
It was 1 μm. Also, pure CH in the above mixed solution is used.
3 COOH CH 3 COOH to the iodine saturated instead of
Etching with a mixed solution using was also performed. In this case, the flatness of the sample surface after the completion of etching was superior to the case where a solution to which pure CH 3 COOH was added was used.

【0015】[第2の実施例]第1の実施例の場合と同
様に図1(a)に示す貼り合わせSOI基板を作製した
後、Wランプを用いて活性層表面を照射しながら、エッ
チング溶液にKOH30%溶液を用いてエッチングを行
った。溶液温度を50〜80℃に保ってエッチングを行
ったところ、約5〜10分でエッチングは自動的に停止
した。エッチング後の半導体活性層膜厚とその分布につ
いては、第1の実施例の場合と同様の結果が得られた。
[Second Embodiment] A bonded SOI substrate shown in FIG. 1A is manufactured in the same manner as in the first embodiment, and etching is performed while irradiating the active layer surface with a W lamp. Etching was performed using a 30% KOH solution. When etching was performed while maintaining the solution temperature at 50 to 80 ° C., the etching was automatically stopped in about 5 to 10 minutes. With respect to the thickness of the semiconductor active layer after etching and the distribution thereof, the same results as in the first embodiment were obtained.

【0016】半導体活性層のエッチングでは、弗硝酸や
KOH溶液の他に例えばヒドラジン溶液等大抵のエッチ
ング液においてキャリアの有無や濃度に依存してエッチ
レートが異なるため、同様な効果が期待できる。また、
特願平7−97338号にて提案した、溶液と活性層3
0と支持基板10のいずれか2つの間あるいは3者間に
電位差を与える方法を併用することにより、エッチスト
ップをより確実にすることもできる。
In the etching of the semiconductor active layer, the same effect can be expected because the etching rate differs depending on the presence or absence and concentration of carriers in most etching solutions such as a hydrazine solution in addition to a hydrofluoric acid or KOH solution. Also,
Solution and active layer 3 proposed in Japanese Patent Application No. 7-97338.
By using a method of giving a potential difference between any two of the 0 and the support substrate 10 or between the three, the etch stop can be made more reliable.

【0017】[第3の実施例]図1(a)に示す貼り合
わせSOI基板を作製した後、活性層にWランプの光を
照射し、CCl4 ガスを用いたプラズマエッチングを行
った。この場合、光が突き抜けてキャリアが少数しか存
在しない膜厚でのエッチング速度の低下割合が、ウエッ
ト法を用いる第1、第2の実施例の場合に比べて小さい
ため、薄膜化後に得られた活性層膜厚は約0.5μmで
あるものの、その分布は±0.1μmと均一性は劣っ
た。しかしながら、この均一性は、化学機械研磨法によ
る従来例に比べると優れており、また、ドライ法による
加工が可能である、他のプロセスとの整合性に優れる等
のガスエッチングが持つ他の利点を活かすことができ
る。CCl4 の他にも、半導体のエッチングが可能なガ
スでは同様の効果を期待できる。また、プラズマエッチ
ングでなくてもエッチングガスを用いた気相エッチング
法も同様に適用が可能である。
[Third Embodiment] After the bonded SOI substrate shown in FIG. 1A was manufactured, the active layer was irradiated with light from a W lamp, and plasma etching was performed using CCl 4 gas. In this case, the rate of decrease in the etching rate at a film thickness through which light penetrates and only a small number of carriers are present is smaller than in the first and second embodiments using the wet method, so that the film is obtained after thinning. Although the thickness of the active layer was about 0.5 μm, the distribution was ± 0.1 μm and the uniformity was poor. However, this uniformity is superior to the conventional example by the chemical mechanical polishing method, and other advantages of the gas etching, such as being capable of processing by the dry method and being excellent in compatibility with other processes, are provided. Can be utilized. In addition to CCl 4, a similar effect can be expected with a gas capable of etching a semiconductor. In addition, a vapor phase etching method using an etching gas can be similarly applied without using plasma etching.

【0018】[第4の実施例]図2(a)〜(d)は、
本発明の第4の実施例を説明するための工程順断面図で
ある。第1の実施例の場合と同様の手法により貼り合わ
せSOI基板を作製〔図2(a)〕した後、エチレング
リコール液内において、Wランプ光を照射しつつ、溶液
と活性層に、その間に流れる電流値が一定になるように
活性層側が正となる電圧を印加した。この方法は、陽極
酸化として知られており、半導体活性層が表面側から酸
化される。電流密度を20mA/cm2 と一定にし、電
圧が50V増加した際に膜厚100〜300ÅのSi酸
化膜50が形成された〔図2(b)〕。
[Fourth Embodiment] FIGS. 2 (a) to 2 (d)
FIG. 14 is a process order sectional view for explaining a fourth embodiment of the present invention. After a bonded SOI substrate is manufactured by the same method as in the first embodiment [FIG. 2 (a)], a W lamp light is irradiated in an ethylene glycol solution while the solution and the active layer are interposed therebetween. A voltage was applied so that the active layer side became positive so that the flowing current value became constant. This method is known as anodic oxidation, in which the semiconductor active layer is oxidized from the front side. The current density was kept constant at 20 mA / cm 2, and when the voltage was increased by 50 V, a Si oxide film 50 having a thickness of 100 to 300 ° was formed (FIG. 2B).

【0019】形成されたSi酸化膜50をHF液を用い
てエッチング除去した〔図2(c)〕。引き続き、同様
に陽極酸化とHFによる酸化膜のエッチングを繰り返し
て、活性層を薄膜化したところ、酸化反応は途中で停止
して、第1、第2の実施例の場合と同様の膜厚および膜
厚分布の均一膜厚の活性層40が得られた〔図2
(d)〕。陽極酸化を行うためには、エチレングリコー
ルの他にナトリウム・テトラボレートとほう酸の混液や
N−メチルアセトイミド溶液を用いてもよい。
The formed Si oxide film 50 was removed by etching using an HF solution (FIG. 2C). Subsequently, the anodic oxidation and the etching of the oxide film by HF were repeated in the same manner to make the active layer thinner. The oxidation reaction was stopped halfway, and the same film thickness and thickness as those in the first and second embodiments were obtained. An active layer 40 having a uniform film thickness with a film thickness distribution was obtained [FIG.
(D)]. In order to perform anodic oxidation, a mixed solution of sodium tetraborate and boric acid or an N-methylacetimide solution may be used in addition to ethylene glycol.

【0020】[第5の実施例]図3(a)〜(c)は、
本発明の第4の実施例を説明するための工程順断面図で
ある。第1の実施例の場合と同様の手法により貼り合わ
せSOI基板を作製〔図3(a)〕した後、HF/エチ
ルアルコール=2:3の溶液内において、Wランプ光を
照射しつつ、溶液と活性層の間に活性層側が正となる5
〜15Vの電圧を印加した。この方法は陽極化成として
知られ、陽極化成中の電流値はおよそ20〜80mA/
cm2 であった。反応は5〜15分で停止し、半導体活
性層表面から多孔質Si膜60が形成された〔図3
(b)〕。弗硝酸溶液で多孔質Si膜60のみを除去し
た〔図3(c)〕後、活性層膜厚とその分布を測定した
ところ第1の実施例の場合と同等であった。
[Fifth Embodiment] FIGS. 3 (a) to 3 (c)
FIG. 14 is a process order sectional view for explaining a fourth embodiment of the present invention. After a bonded SOI substrate was manufactured by the same method as in the first embodiment (FIG. 3A), the solution was irradiated with W lamp light in a solution of HF / ethyl alcohol = 2: 3. Between the active layer and the active layer, the active layer side being positive 5
A voltage of 1515 V was applied. This method is known as anodization, and the current value during the anodization is approximately 20 to 80 mA /
cm 2 . The reaction was stopped in 5 to 15 minutes, and a porous Si film 60 was formed from the surface of the semiconductor active layer.
(B)]. After removing only the porous Si film 60 with a hydrofluoric acid solution [FIG. 3 (c)], the thickness of the active layer and its distribution were measured and found to be the same as in the first embodiment.

【0021】第3、第4の実施例で挙げた反応に限ら
ず、半導体表面での化学反応もしくは電気化学反応を利
用した他の反応物生成方法においても、反応速度がキャ
リアの有無およびその濃度に大きく影響されるものがあ
り、それらの反応はいずれも本発明による利用が可能で
ある。
Not only in the reactions described in the third and fourth embodiments, but also in other reactant producing methods utilizing a chemical reaction or an electrochemical reaction on the semiconductor surface, the reaction rate is determined by the presence or absence of the carrier and the concentration thereof. And any of those reactions can be used according to the present invention.

【0022】以上好ましい実施例について説明したが、
本発明はこれら実施例に限定されるものではなく、特許
請求の範囲に記載された本願発明の要旨を逸脱しない範
囲内において各種の変更が可能である。例えば、上記実
施例では、照射する光の光源に比較的取り扱いの容易な
Wランプを用いたが、He−NeやAr、YAG等のレ
ーザを用いてもそれぞれの波長に応じた膜厚の活性層膜
厚が得られる。また、照射光の試料への照射角度を調節
し、全反射条件や多重反射条件を利用するとより高度な
膜厚制御が期待できる。また、反応の初期に反応を加速
して生産性高めるために、初めに照射光強度を高く設定
しておき徐々に低下させたり、初めに短波長と長波長の
2光源を用いて照射を行い反応の最終段階で長波長光の
みを照射するようにしてもよい。さらに、上記実施例で
用いた支持基板、活性層等の伝導型や抵抗率は、上記の
例に限定されるものではない。
While the preferred embodiment has been described above,
The present invention is not limited to these embodiments, and various changes can be made without departing from the gist of the present invention described in the claims. For example, in the above embodiment, a W lamp, which is relatively easy to handle, was used as a light source of the light to be irradiated. The layer thickness is obtained. Further, if the irradiation angle of the irradiation light to the sample is adjusted and the total reflection condition or the multiple reflection condition is used, more advanced film thickness control can be expected. Also, in order to accelerate the reaction at the beginning of the reaction and increase the productivity, the irradiation light intensity is set high first and then gradually decreased, or irradiation is first performed using two light sources of short wavelength and long wavelength. At the final stage of the reaction, only long-wavelength light may be irradiated. Further, the conductivity type and the resistivity of the support substrate, the active layer, and the like used in the above embodiment are not limited to the above examples.

【0023】[0023]

【発明の効果】以上説明したように、本発明によるSO
I基板の製造方法は、活性層に光を照射しつつエッチン
グを行いあるいは反応生成物を形成しこれを除去するも
のであるので、薄くかつ均一の膜厚の活性層を簡単なプ
ロセスで得ることが可能となり、高品質のSOI基板を
安価に提供することが可能になる。
As described above, the SO according to the present invention can be used.
Since the method of manufacturing the I-substrate involves etching while irradiating the active layer with light or forming a reaction product and removing the reaction product, it is necessary to obtain a thin and uniform active layer with a simple process. This makes it possible to provide a high-quality SOI substrate at low cost.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1乃至第3の実施例を説明するため
の工程順断面図。
FIG. 1 is a cross-sectional view in a process order for describing first to third embodiments of the present invention.

【図2】本発明の第4の実施例を説明するための工程順
断面図。
FIG. 2 is a cross-sectional view in a process order for explaining a fourth embodiment of the present invention.

【図3】本発明の第5の実施例を説明するための工程順
断面図。
FIG. 3 is a cross-sectional view in a process order for explaining a fifth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

10 支持基板 20、50 Si酸化膜 30 活性層 40 均一膜厚の活性層 60 多孔質Si膜 DESCRIPTION OF SYMBOLS 10 Support substrate 20, 50 Si oxide film 30 Active layer 40 Active layer of uniform thickness 60 Porous Si film

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 (1)支持基板と活性層を構成するシリ
コン基板とを何れかの基板に形成された絶縁膜を介して
接着する工程と、 (2)前記活性層となるシリコン基板表面に光を入射し
て該シリコン基板内にキャリアを生成しながら該シリコ
ン基板を湿式またはドライ法にてエッチングする工程
と、を備えることを特徴とするSOI基板の製造方法。
(1) a step of bonding a supporting substrate and a silicon substrate constituting an active layer via an insulating film formed on any one of the substrates; and (2) a step of adhering to a surface of the silicon substrate to be the active layer. Etching the silicon substrate by a wet or dry method while irradiating light to generate carriers in the silicon substrate.
【請求項2】 (1)支持基板と活性層を構成するシリ
コン基板とを何れかの基板に形成された絶縁膜を介して
接着する工程と、 (2)前記活性層となるシリコン基板表面に光を入射し
該シリコン基板内にキャリアを生成しながら該シリコン
基板に化学的もしくは電気化学的な反応を起こさせて該
シリコン基板表面に反応生成物層を形成する工程と、 (3)前記反応生成物層をエッチング除去する工程と、
を備えることを特徴とするSOI基板の製造方法。
2. A step of: (1) adhering a supporting substrate and a silicon substrate constituting an active layer via an insulating film formed on any one of the substrates; and (2) a step of adhering to a surface of the silicon substrate to be an active layer. Forming a reaction product layer on the surface of the silicon substrate by causing a chemical or electrochemical reaction on the silicon substrate while receiving light to generate carriers in the silicon substrate; (3) the reaction Etching away the product layer;
A method for manufacturing an SOI substrate, comprising:
【請求項3】 初期の段階では照明光強度を高く設定し
ておき徐々に低下させながら前記第(2)の工程を行う
ことを特徴とする請求項1または2記載のSOI基板の
製造方法。
3. The method for manufacturing an SOI substrate according to claim 1, wherein in the initial stage, the step (2) is performed while setting the intensity of the illumination light high and gradually decreasing the intensity.
【請求項4】 前記第(1)の工程と前記第(2)の工
程との間に、前記シリコン基板の表面を研磨する工程が
挿入されることを特徴とする請求項1または2記載のS
OI基板の製造方法。
4. The method according to claim 1, wherein a step of polishing the surface of the silicon substrate is inserted between the step (1) and the step (2). S
A method for manufacturing an OI substrate.
【請求項5】 前記研磨が化学機械研磨法により行われ
ることを特徴とする請求項3記載のSOI基板の製造方
法。
5. The method according to claim 3, wherein the polishing is performed by a chemical mechanical polishing method.
JP17157395A 1995-06-15 1995-06-15 Method for manufacturing SOI substrate Expired - Fee Related JP2663923B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17157395A JP2663923B2 (en) 1995-06-15 1995-06-15 Method for manufacturing SOI substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17157395A JP2663923B2 (en) 1995-06-15 1995-06-15 Method for manufacturing SOI substrate

Publications (2)

Publication Number Publication Date
JPH098258A true JPH098258A (en) 1997-01-10
JP2663923B2 JP2663923B2 (en) 1997-10-15

Family

ID=15925660

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2663923B2 (en)

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JP2005005674A (en) * 2003-05-21 2005-01-06 Canon Inc Method of manufacturing substrate and substrate treatment apparatus
JP2006511963A (en) * 2002-12-19 2006-04-06 アプライド マテリアルズ インコーポレイテッド Method and apparatus for planarizing materials by growing and removing sacrificial films
US7256104B2 (en) 2003-05-21 2007-08-14 Canon Kabushiki Kaisha Substrate manufacturing method and substrate processing apparatus
EP1857576A2 (en) * 2006-05-18 2007-11-21 Siltronic AG Method and device for treating a semi-conductor wafer
WO2007131635A1 (en) * 2006-05-11 2007-11-22 Siltronic Ag Method and device for processing a semiconductor wafer by etching
DE102007006151A1 (en) 2007-02-07 2008-08-14 Siltronic Ag A method of reducing and homogenizing the thickness of a semiconductor layer located on the surface of an electrically insulating material

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006511963A (en) * 2002-12-19 2006-04-06 アプライド マテリアルズ インコーポレイテッド Method and apparatus for planarizing materials by growing and removing sacrificial films
JP2005005674A (en) * 2003-05-21 2005-01-06 Canon Inc Method of manufacturing substrate and substrate treatment apparatus
US7256104B2 (en) 2003-05-21 2007-08-14 Canon Kabushiki Kaisha Substrate manufacturing method and substrate processing apparatus
WO2007131635A1 (en) * 2006-05-11 2007-11-22 Siltronic Ag Method and device for processing a semiconductor wafer by etching
EP1857576A2 (en) * 2006-05-18 2007-11-21 Siltronic AG Method and device for treating a semi-conductor wafer
EP1857576A3 (en) * 2006-05-18 2008-01-23 Siltronic AG Method and device for treating a semi-conductor wafer
US7799692B2 (en) 2006-05-18 2010-09-21 Siltronic Ag Method and apparatus for the treatment of a semiconductor wafer
DE102007006151A1 (en) 2007-02-07 2008-08-14 Siltronic Ag A method of reducing and homogenizing the thickness of a semiconductor layer located on the surface of an electrically insulating material
DE102007006151B4 (en) * 2007-02-07 2008-11-06 Siltronic Ag A method of reducing and homogenizing the thickness of a semiconductor layer located on the surface of an electrically insulating material
US7988876B2 (en) 2007-02-07 2011-08-02 Siltronic Ag Method for reducing and homogenizing the thickness of a semiconductor layer which lies on the surface of an electrically insulating material

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