JPH098158A - Nonvolatile semiconductor memory device and its manufacture - Google Patents

Abstract

PURPOSE: To increase the integration density of a memory cell, to prevent an access speed from being lowered and to enhance the data holding characteristic of the memory cell in a stack gate-type nonvolatile semiconductor memory device. CONSTITUTION: Floating gates FG whose size is nearly equal to the channel length and the channel width of memory transistors are formed on a tunnel oxide film. Insulating films 5 whose thickness is nearly equal to the thickness of the floating gates FG and which are extended to the direction of the channel width are formed in parts between the flating gates FG of the memory transistors which are adjacent to each other in the direction of the channel length. Control gates CG are formed via interlayer insulating films so as to be passed directly above the floating gates FG and the insulating films 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.

[0002]

2. Description of the Related Art A so-called stack gate type non-volatile semiconductor memory in which a control gate is stacked on a floating gate is known.

FIG. 57 shows a conventional stack gate type non-volatile semiconductor memory, and particularly shows the structure of its NOR type memory cell. Here, FIG. 57A is a plan view, and FIG.
FIG. 57B is a cross-sectional view taken along the line BB of FIG. 57A.

As shown in FIG. 57, in this conventional stack gate type nonvolatile semiconductor memory, a field such as a silicon dioxide (SiO ₂ ) film is formed on the surface of a p-type silicon (Si) substrate 101 by the LOCOS method. The insulating film 102 is selectively provided, thereby separating the elements. A p ⁺ type channel stopper 103 is provided in the p type Si substrate 101 in the lower portion of the field insulating film 102. On the surface of the active region surrounded by the field insulating film 102, a tunnel oxide film 104 made of a SiO ₂ film is formed by, for example, a thermal oxidation method.
Is provided.

A floating gate FG is formed on the tunnel oxide film 104 so as to extend on the field insulating film 102 on both sides in the channel width direction of the memory transistor.
'Is provided. This floating gate FG '
An interlayer insulating film (coupling insulating film) 105 is provided on the surface of the. Further, a control gate CG ′ is provided extending in the channel width direction of the memory transistor so as to pass directly above the floating gate FG ′.

Further, in the active region surrounded by the field insulating film 102, the floating gate FG ′ and the control gate CG ′ are formed on both sides of the floating gate FG ′ and the control gate CG ′ in the channel length direction. In contrast to n ⁺
A mold source region 106 and a drain region 107 are provided. The floating gate FG ′, the control gate CG ′ stacked on the floating gate FG ′ via the interlayer insulating film 105, and the source region 106 and the drain region 107 constitute one memory transistor. In this case, the source region 106 is provided so as to extend parallel to the control gate CG ′, and constitutes a source line.

In such a conventional stack gate type non-volatile semiconductor memory, the channel length of the memory transistor is determined by the width of the control gate CG '. The channel width of the memory transistor is determined by the width of the active region surrounded by the field insulating film 102 in the channel width direction. Of these, the channel width is important in determining the capability of the memory transistor.

[0008]

However, in the above-mentioned conventional stack gate type non-volatile semiconductor memory,
Since bird's beaks are generated at the end portions of the Si ₃ N ₄ film (not shown) used as an oxidation mask when forming the field insulating film 102 by the LOCOS method, the effect of the effective area of the active region is higher than that of the oxidation mask. There is a problem that the width is reduced. For this reason, a method has been adopted in which the width of the oxidation mask is determined in consideration of the reduction amount of the active region due to the occurrence of the bird's beak.

However, according to this method, the area occupied by one memory transistor becomes large, which is not desirable in terms of increasing the integration density of the memory cells.

Further, the floating gate FG 'extends on the field insulating film 102 in the channel width direction, and since the corners at both ends thereof are in the form of protrusions, the floating gate FG' has an interlayer insulating film 105 thereabove. The stacked control gates CG ′ are likely to cause step breaks at this portion. For this reason, it becomes difficult to apply a voltage to the control gates CG 'of the memory cells other than this memory cell, and the access speed may be reduced.

Further, there is a disadvantage that current leakage easily occurs at the corners of the floating gate FG 'on the field insulating film 102, resulting in deterioration of the data retention characteristic of the memory cell.

Therefore, an object of the present invention is to eliminate the problem of the effective width reduction of the active region due to the occurrence of bird's beaks, and thus to increase the integration density of memory cells in a stack gate type non-volatile semiconductor memory device. And to provide a manufacturing method thereof.

Another object of the present invention is a stack gate type non-volatile memory which has a high access speed and has a good data retention characteristic of a memory cell because there is no problem of breakage of the control gate and current leakage at the corners of the floating gate. To provide a conductive semiconductor memory device and a manufacturing method thereof.

[0014]

In order to achieve the above object, a first aspect of the present invention is a nonvolatile semiconductor memory device having a memory transistor having a structure in which a control gate is stacked on a floating gate. The channel length and the channel width of the transistor are determined by the size of the floating gate.

According to a second aspect of the present invention, in a nonvolatile semiconductor memory device having a memory transistor having a structure in which a control gate is stacked on a floating gate, the width of the floating gate in the channel length direction of the memory transistor is the channel length. It is characterized in that the widths of the floating gates of the memory transistor in the channel width direction are substantially equal to the channel width.

In one embodiment of the first invention of the present invention, the first floating gate of the first memory transistor and the second memory transistor adjacent to the first memory transistor in the channel length direction are provided. A diffusion layer forming a source region or a drain region in a self-aligned manner with the first floating gate and the second floating gate is provided in the semiconductor substrate in a portion between the second floating gate and the first floating gate.

In one embodiment of the first invention of the present invention, a first floating gate of the first memory transistor and a second memory transistor adjacent to the first memory transistor in the channel length direction are provided. A portion between the second floating gate and the second floating gate is filled with an insulating film. The thickness of this insulating film is preferably
It is chosen to be approximately equal to the thickness of the floating gate. This insulating film is specifically, for example, silicon dioxide (Si
O ₂ ) film.

A third aspect of the present invention is a method for manufacturing a non-volatile semiconductor memory device having a memory transistor having a structure in which a control gate is laminated on a floating gate, in a method of manufacturing a non-volatile semiconductor memory device on a gate insulating film formed on a semiconductor substrate. A step of forming a first conductive film for forming a floating gate whose width in the channel length direction of the memory transistor is substantially equal to the channel length; and a step of introducing an impurity into the semiconductor substrate by using the first conductive film as a mask Alternatively, the step of forming a diffusion layer forming a drain region, the step of forming an insulating film over a semiconductor substrate, and the step of planarizing the insulating film so that the surface of the insulating film is substantially aligned with the top surface of the first conductive film A step of forming an interlayer insulating film on the first conductive film and the insulating film, and a control gate on the interlayer insulating film. Forming a second conductive film for formation, and patterning the second conductive film, the interlayer insulating film, and the first conductive film so that the width of the memory transistor in the channel width direction is substantially equal to the channel width. And a step of forming a control gate and a floating gate.

In one embodiment of the third invention of the present invention, the insulating film formed on the semiconductor substrate is polished to planarize the insulating film. For this polishing,
For example, a chemical mechanical polishing method is used.

In another embodiment of the third aspect of the present invention, the insulating film formed on the semiconductor substrate is etched back to flatten the insulating film. A plasma etching method such as a reactive ion etching method is used for this etch back.

[0021]

In the nonvolatile semiconductor memory device according to the present invention, the channel length and channel width of the memory transistor are determined by the size of the floating gate. In other words, the width of the floating gate of the memory transistor in the channel length direction is substantially equal to the channel length, and the width of the floating gate of the memory transistor in the channel width direction is substantially equal to the channel width. Can be reduced to a dimension determined by processing accuracy. Therefore, the integration density of the memory cells can be increased.

Further, the portion between the first floating gate of the first memory transistor and the second floating gate of the second memory transistor adjacent to the first memory transistor in the channel length direction is By being filled with the insulating film, the underlying surface of the control gate is flattened. In particular, by setting the thickness of the insulating film to be substantially equal to the thickness of the floating gate, the underlying surface of the control gate can be almost completely flattened. For this reason, disconnection of the control gate does not occur. Furthermore, this allows a uniform voltage to be applied to the control gate, thus avoiding a reduction in access speed. In addition, since the current leakage does not occur at the corner of the floating gate, the data retention characteristic of the memory cell is improved.

In the method for manufacturing a non-volatile semiconductor memory device according to the present invention, the non-volatile semiconductor memory device can be manufactured by including the above steps.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 to 5 show a stack gate type nonvolatile semiconductor memory according to an embodiment of the present invention. Here, FIG. 1 is a plan view, and FIG. 2 is II-II of FIG.
1 is a sectional view taken along line III-III in FIG. 1, FIG. 4 is a sectional view taken along line IV-IV in FIG. 1, and FIG. Cross-sectional views along the line V are respectively shown.

As shown in FIGS. 1 to 5, in the nonvolatile semiconductor memory according to this embodiment, for example, p-type Si is used.
On the surface of the p-type semiconductor substrate 1 such as a substrate, for example, SiO
A tunnel oxide film 2 such as _two films is provided. On the tunnel oxide film 2, for example, n such as phosphorus (P) is formed.
A floating gate FG made of polycrystalline Si heavily doped with type impurities is provided. In the floating gate FG, the width of the memory transistor in the channel length direction is substantially equal to the channel length, and the width of the memory transistor in the channel width direction is substantially equal to the channel width.

In the p-type semiconductor substrate 1 in the portion between the floating gates FG of the memory transistors adjacent to each other in the channel length direction, the n ⁺ type source region 3 is self-aligned with these floating gates FG.
And drain regions 4 are alternately provided. These source region 3 and drain region 4 have a predetermined width in the channel length direction and are provided so as to extend in the channel width direction. Of these, the source region 3 constitutes a common source line, and the drain region 4 is used as a bit line.

An insulating film 5 such as a SiO ₂ film is provided so as to extend in the channel width direction between the floating gates FG of the memory transistors adjacent to each other in the channel length direction. Here, the thickness of the insulating film 5 is substantially equal to the thickness of the floating gate FG. An interlayer insulating film (coupling insulating film) 6 is provided on the floating gate FG and the insulating film 5, and the control gate CG extends on the interlayer insulating film 6 in the channel length direction so as to pass directly above the floating gate FG. It is provided there. The interlayer insulating film 6 is, for example, a SiO ₂ film / silicon nitride (Si ₃ N ₄ ) film / SiO ₂ film.
It has a three-layer structure composed of a film. Control gate CG
Has the same width in the channel width direction as the floating gate FG. This control gate CG constitutes a word line. Further, the control gate CG is formed of a polycide film in which a refractory metal silicide film such as a tungsten silicide (WSi ₂ ) film is stacked on a polycrystalline Si film doped with an n-type impurity such as P. It

In this embodiment, the floating gate FG, the control gate CG stacked on the floating gate FG via the interlayer insulating film 6, and the source region 3 and the drain region 4 provided in self alignment with the floating gate FG. One memory transistor is configured by.

Next, an operation example of the non-volatile semiconductor memory according to this embodiment configured as described above will be described. FIG. 6 shows an equivalent circuit of the nonvolatile semiconductor memory according to this embodiment. Here, the memory cell is configured as a NOR type.

In FIG. 6, the common source line SL is composed of the source region 3. In addition, the bit line BL1,
BL2, BL3, BL4, ... Are drain regions 4 respectively.
It consists of. These bit lines are arranged in the number of m in the channel length direction of the memory transistor. In this embodiment, the source sides of all memory transistors are connected to the common source line SL, and all drain sides are connected to any bit line. Each of the word lines WL1, WL2, WL3, WL4, ... Is composed of a control gate CG. These word lines are arranged in the number n in the channel width direction of the memory transistor.

The memory cells are selected by selecting these word lines W
This is performed by selecting any one of L1, WL2, WL3, WL4, ... And any one of the bit lines BL1, BL2, BL3, BL4 ,.

Here, a case where reading and writing are performed on the memory cell surrounded by a circle in FIG. 6 will be described.

First, when reading information from this memory cell, a voltage of, for example, + 5V is applied to the word line WL2, and the other word lines WL1, WL3, WL4, ... Are all set to 0V. Also, for example, +1 is applied to the bit line BL2.
V voltage is applied to the other bit lines BL1, BL3,
BL4, ... Are all set to 0V. The common source line SL is grounded and set to 0V.

Next, when writing information to this memory cell, a voltage of, for example, +12 V is applied to the word line WL2, and the other word lines WL1, WL3, WL4,
All are set to 0V. Further, for example, a voltage of + 5V is applied to the bit line BL2, and the other bit lines BL1 and B
L3, BL4, ... Are all set to 0V. The common source line SL is grounded and set to 0V.

Regarding erasing, there are cases of erasing in units of word lines and cases of erasing all memory cells at once. First, when erasing is performed in word line units, a voltage of, for example, −12 V is applied to the word line WL2
All other word lines WL1, WL3, WL4, ... Are 0
Set to V. In addition, all bit lines BL1, BL2,
BL3, BL4, ... Are open (floating), and the common source line SL is set to + 5V, for example. On the other hand, when erasing the information of all memory cells at once,
All the word lines WL1, WL2, WL3, WL4, ... Are set to, for example, −12 V, and the rest is the same as the case of erasing in word line units.

Next, a method of manufacturing the nonvolatile semiconductor memory according to this embodiment having the above-described structure will be described with reference to FIG.
~ It will be described with reference to FIG. Here, FIG. 7, FIG. 12, FIG. 17, FIG. 22, FIG. 27, FIG. 32, FIG.
2, FIG. 47 and FIG. 52 are plan views corresponding to FIG. 1, FIG. 8, FIG. 13, FIG. 18, FIG. 23, FIG.
8, FIG. 43, FIG. 48 and FIG. 53 are sectional views corresponding to FIG. 2, FIG. 9, FIG. 14, FIG. 19, FIG. 24, FIG. 29, FIG.
39, 44, 49 and 54 are sectional views corresponding to FIG. 3, FIG. 10, FIG. 15, FIG. 20, FIG. 25, FIG. 30, FIG. 35, FIG. 40, FIG. 45, FIG. Sectional view corresponding to FIG. 4, FIG. 11, FIG. 16, FIG. 21, FIG.
1, FIG. 36, FIG. 41, FIG. 46, FIG. 51 and FIG. 56 are sectional views corresponding to FIG.

That is, in order to manufacture the nonvolatile semiconductor memory according to this embodiment, as shown in FIGS. 7 to 11, first, for example, on the surface of a p-type semiconductor substrate 1 such as a p-type Si substrate, for example, A tunnel oxide film 2 such as a SiO ₂ film is formed by a thermal oxidation method. Next, the polycrystalline Si film 11 for forming the floating gate FG is formed on the entire surface by, eg, CVD method. Next, this polycrystalline Si film 11
Then, an n-type impurity such as P is doped by an ion implantation method or a thermal diffusion method. Next, a resist pattern 12 having a predetermined shape extending in the channel width direction of the memory transistor is formed on the polycrystalline Si film 11 by a lithography method.

Next, as shown in FIGS. 12 to 16, a polycrystalline Si film 11 is formed by using this resist pattern 12 as a mask.
Are etched and patterned. The width of the polycrystalline Si film 11 after this patterning determines the channel length of the memory transistor.

Next, as shown in FIGS. 17 to 21, using the polycrystalline Si film 11 and the resist pattern 12 as a mask, an n-type such as arsenic (As) is implanted into the p-type semiconductor substrate 1 by an ion implantation method. Dope impurities. Thereafter, if necessary, the resist pattern 12 is removed and then annealing for electrically activating the implanted impurities is performed.
As a result, the n ⁺ type source region 3 and the drain region 4 are formed in self-alignment with the polycrystalline Si film 11 for forming the floating gate FG.

Next, as shown in FIGS. 22 to 26, an insulating film 5 such as a SiO ₂ film is formed on the entire surface by, eg, CVD. This insulating film 5 has a thickness of at least polycrystalline S.
It is made thicker than the i film 11.

Next, a coating film (not shown) such as a resist is formed on the insulating film 5 to flatten the surface. Next, the coating film and the insulating film 5 are etched back in the direction perpendicular to the substrate surface by, for example, the reactive ion etching (RIE) method. This etch back is performed until the upper surface of the polycrystalline Si film 11 is exposed. As a result, as shown in FIGS. 27 to 31, the surface of insulating film 5 coincides with the upper surface of polycrystalline Si film 11, and the surface is almost completely flattened.

Next, as shown in FIGS. 32 to 36, for example, a SiO ₂ film / is formed on the entire surface by a thermal oxidation method or a CVD method.
An interlayer insulating film 6 having a three-layer structure of Si ₃ N ₄ film / SiO ₂ film is formed.

Next, as shown in FIGS. 37 to 41, for example, a polycide film 13 is formed for forming the control gate CG.
Is formed on the entire surface. This polycide film 13 is, for example, C
Forming a polycrystalline Si film by a VD method, doping the polycrystalline Si film with an n-type impurity such as P, and then forming a refractory metal silicide film on the polycrystalline Si film by, for example, a sputtering method. Formed by. next,
A resist pattern 14 having a predetermined shape extending in the channel length direction of the memory transistor is formed by the lithography method.

Next, using the resist pattern 14 as a mask, the polycide film 15 is etched and patterned. As a result, the control gate CG is formed as shown in FIGS.

Next, as shown in FIGS. 47 to 51, the interlayer insulating film 6 is etched by, for example, the RIE method using the resist pattern 14 and the control gate CG as a mask.

52 to 56, only the polycrystalline Si film 11 is selectively etched with respect to the insulating film 5 by using the resist pattern 14, the control gate CG and the interlayer insulating film 6 as a mask. The polycrystalline Si film 11 is etched under such etching conditions. As a result, the floating gate FG is formed with the same width as the control gate CG, and the channel width of the memory transistor is determined to be substantially equal to the width of the floating gate FG in the channel width direction. After that, the resist pattern 14 is removed.

Through the above steps, the desired nonvolatile semiconductor memory is completed.

As described above, in the non-volatile semiconductor memory according to this embodiment, the channel length and the channel width of the memory transistor are determined by the width in the channel length direction and the width in the channel width direction of the floating gate FG, respectively. Therefore, there is no problem of reducing the effective width of the active region due to the bird's beak as in the conventional case, and the size of the memory transistor, that is, the memory cell can be reduced to the minimum dimension determined by the processing accuracy. Therefore, high integration density of memory cells can be achieved.

Further, according to the non-volatile semiconductor memory according to this embodiment, the portion between the floating gates FG of the memory transistors adjacent to each other in the channel length direction has an insulating film whose thickness is substantially equal to the thickness of the floating gate FG. Since it is filled with 8, the underlying surface of the control gate CG is almost completely flattened. Therefore, the disconnection of the control gate CG does not occur. Further, as a result, a voltage is uniformly applied to the control gate CG, so that a reduction in access speed can be avoided. In addition, the floating gate F
Since the current leakage does not occur at the corner of G, the data retention characteristic of the memory cell is good.

Although one embodiment of the present invention has been specifically described above, the present invention is not limited to the above-described embodiment, and various modifications based on the technical idea of the present invention are possible. .

For example, the numerical values given in the above-mentioned embodiment are merely examples, and the present invention is not limited to these.

The interlayer insulating film 6 in the above-described embodiment may be a single layer of SiO ₂ film.

Further, in the above-described embodiment, as a method of flattening the insulating film 5, a method of forming a coating film on the insulating film 5 and then etching back these by the RIE method is used. A method of polishing the insulating film 5 by a chemical mechanical polishing method may be used.

Further, in the above-mentioned embodiment, the structure of the memory cell is of NOR type, but the structure of the memory cell in the nonvolatile semiconductor memory device according to the present invention is DINOR type, AND type, NAND type or the like. Any of the logic type memory cells may be used.

[0055]

As described above, according to the nonvolatile semiconductor memory device of the present invention, the channel length and the channel width of the memory transistor are determined by the size of the floating gate. In other words, in the channel length direction of the memory transistor. Since the width of the floating gate at is substantially equal to this channel length, and the width of the floating gate in the channel width direction of the memory transistor is almost equal to this channel width, the size of the memory transistor, that is, the memory cell, is the minimum dimension determined by the processing accuracy. Can be reduced to. Therefore, the integration density of the memory cells can be increased.

Further, according to the nonvolatile semiconductor memory device of the present invention, the portion between the floating gate of one memory transistor and the floating gate of the memory transistor adjacent to this memory transistor in the channel length direction is insulated. By being filled with the film, the underlying surface of the control gate is flattened. In particular, by making the thickness of this insulating film substantially equal to the thickness of the floating gate, the underlying surface of the control gate can be almost completely flattened. Therefore, the step break of the control gate does not occur. Furthermore, this allows a uniform voltage to be applied to the control gate, thus avoiding a reduction in access speed. In addition, since the current leakage does not occur at the corner of the floating gate, the data retention characteristic of the memory cell is improved.

Further, according to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, as described above, the nonvolatile density of the memory cells is high, the access speed is fast, and the data retention characteristics of the memory cells are good. Semiconductor memory device can be manufactured.

[Brief description of drawings]

FIG. 1 is a plan view showing a nonvolatile semiconductor memory according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line II-II in FIG.

FIG. 3 is a sectional view taken along the line III-III in FIG. 1;

FIG. 4 is a sectional view taken along the line IV-IV in FIG. 1;

5 is a cross-sectional view taken along the line VV of FIG.

FIG. 6 is an equivalent circuit diagram of a nonvolatile semiconductor memory according to an embodiment of the present invention.

FIG. 7 is a plan view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 8 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 10 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 11 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 12 is a plan view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 13 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 14 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 15 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 16 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 17 is a plan view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 18 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 19 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 20 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 21 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 22 is a plan view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 23 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 24 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 25 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 26 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 27 is a plan view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 28 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 29 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 30 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 31 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 32 is a plan view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 33 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 34 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 35 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 36 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 37 is a plan view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 38 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 39 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 40 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 41 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 42 is a plan view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 43 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 44 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 45 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 46 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 47 is a plan view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 48 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 49 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 50 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 51 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 52 is a plan view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 53 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 54 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 55 is a cross-sectional view for explaining the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 56 is a cross-sectional view for explaining the method for manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 57 is a plan view and a cross-sectional view showing a conventional stack gate type nonvolatile semiconductor memory.

[Explanation of symbols]

 1 p-type semiconductor substrate 2 tunnel oxide film 3 source region 4 drain region 5 insulating film 6 interlayer insulating film 11 polycrystalline Si film 12, 14 resist pattern 13 polycide film FG floating gate CG control gate WL1, WL2, WL3, WL4 word line BL1, BL2, BL3, BL4 Bit line SL Common source line

Claims (9)

[Claims] 1. A nonvolatile semiconductor memory device having a memory transistor having a structure in which a control gate is stacked on a floating gate, wherein a channel length and a channel width of the memory transistor are determined by the size of the floating gate. A characteristic non-volatile semiconductor memory device. 2. A nonvolatile semiconductor memory device having a memory transistor having a structure in which a control gate is stacked on a floating gate, wherein the width of the floating gate in the channel length direction of the memory transistor is substantially equal to the channel length. A nonvolatile semiconductor memory device, wherein the width of the floating gate in the channel width direction of the memory transistor is substantially equal to the channel width. 3. A portion between a first floating gate of a first memory transistor and a second floating gate of a second memory transistor adjacent to the first memory transistor in the channel length direction. 2. The semiconductor substrate according to claim 1 is provided with a diffusion layer forming a source region or a drain region in a self-aligned manner with respect to the first floating gate and the second floating gate. Non-volatile semiconductor memory device. 4. A portion between a first floating gate of a first memory transistor and a second floating gate of a second memory transistor adjacent to the first memory transistor in the channel length direction. 2. The non-volatile semiconductor memory device according to claim 1, wherein is filled with an insulating film. 5. The non-volatile semiconductor memory device according to claim 4, wherein the thickness of the insulating film is substantially equal to the thickness of the floating gate. 6. The nonvolatile semiconductor memory device according to claim 4, wherein the insulating film is a silicon dioxide film. 7. A method of manufacturing a non-volatile semiconductor memory device having a memory transistor having a structure in which a control gate is laminated on a floating gate, wherein a channel length direction of the memory transistor is formed on a gate insulating film formed on a semiconductor substrate. A first conductive film for forming a floating gate having a width substantially equal to the channel length, and a source region or a drain region by introducing impurities into the semiconductor substrate using the first conductive film as a mask. A step of forming a diffusion layer forming the insulating film, a step of forming an insulating film on the semiconductor substrate, and a step of flattening the insulating film so that the surface of the insulating film substantially matches the upper surface of the first conductive film. A step of forming an interlayer insulating film on the first conductive film and the insulating film, and A step of forming a second conductive film for forming a control gate, the second conductive film, the interlayer insulating film and the first conductive film having a width in the channel width direction of the memory transistor as the channel width. And a step of forming the control gate and the floating gate by patterning them to be substantially equal to each other. 8. The insulating film is flattened by polishing the insulating film.
A method for manufacturing the nonvolatile semiconductor memory device described. 9. The non-volatile according to claim 7, wherein a coating film is formed on the insulating film, and the insulating film is flattened by etching back the coating film and the insulating film. Of manufacturing a non-volatile semiconductor memory device.