JPH0981117A - Image control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the whole of an image control device from decreasing in a processing speed even if multiple backgrounds exist, not by displaying both backgrounds overlapped but by displaying them split with the boundaries of the display positions. SOLUTION: On a background plane BGB, for example, an area of 42 cells ×28 cells toward the center in one block consisting of 64 cells × 32 cells is defined as a displayable cell. Therefore, by rewriting display position coordinates (X, Y) of the register which shows an original point in the display area, relative scroll of the display screen on the background plane BGB becomes possible. And, when the display plane scrolls the area where background side BGA and background side BGB overlap, only the background plane BGB is displayed by split display. Further, the area which comes off both of the background planes BGA and BGB is included in the display screen, the area becomes a backdrop plane and is displayed transparently (monochrome).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image control device suitable for use in, for example, a video game device.

[0002]

2. Description of the Related Art Conventionally, a video game is connected to a television receiver to display a background image on its display (cathode ray tube) and display-control a plurality of characters moving in response to a game operation. The device is known. In this type of device, CPU, ROM, RA
An image control device including M and VRAM (video RAM) is provided, and each image data of the background image and the object image stored in the ROM is transferred to the VRAM under the instruction of the CPU. Each of the image data transferred to the VRAM is read out, converted into a video signal, and displayed on a display. In such an image control device, in order to provide a screen display effect, a plurality of background screens are often formed. For example, a plurality of background images formed by background image data are prepared, It realizes the effect of switching the background display as if "page turning" according to the scroll processing. Note that the scroll processing here means an operation of moving the display surface on the background surface and displaying the screen.

[0003]

In such a conventional image control apparatus, the background image is formed while displaying the moving image by controlling the display of the object image data for each horizontal scanning line. Therefore, when the display effect by the scroll processing described above is added, the background image data necessary for generating the background screen is read from the VRAM.
The number of accesses to this VRAM increases as the type of background screen increases. As the number of accesses to the memory increases, the processing speed of the entire device decreases as a result, so to avoid it, the number of objects that can be displayed on the horizontal scan line must be reduced accordingly. The problem is that it will not happen.

Therefore, an object of the present invention is to provide an image control device capable of switching and displaying a plurality of background screens without reducing the number of objects capable of displaying a moving image per horizontal scanning line.

[0005]

In order to achieve the above object, according to the invention as set forth in claim 1, there is provided a device for changing a background surface in accordance with scrolling of the display surface, wherein a display position for each of a plurality of background surfaces is provided. Position setting means, a background determination means for determining the type of the background surface located below the display surface based on the display position, and a background of the type determined by the background determination means according to the scroll position of the display surface. And a background control unit for instructing to divide and display different types of background surfaces with the display position as a boundary.

According to the second aspect of the present invention, the background storage means for storing the display attributes for each of the plurality of background planes and the image data forming the background planes respectively associated with these display attributes, and the plurality of background storage means are provided. Position setting means for setting a display position for each background surface, background determination means for determining the display attribute of the background surface located below the display surface based on the display position, and the background determination according to the scroll position of the display surface. Background reading means for reading the image data corresponding to the display attribute determined by the means from the background storing means, and a background surface is generated based on the image data read by the background reading means,
And a background control unit for instructing to divide and display the background surface having different display attributes at the display position.

According to the third aspect of the invention, the background storage means for storing the display attributes for each of the plurality of background surfaces and the image data forming the background surface associated with the display attributes, and the plurality of backgrounds. Position setting means for setting a display position for each surface; address generating means for generating an attribute read address for reading out display attributes for each background surface from the background storage means in correspondence with a scanning line position on the display surface; Of a plurality of background planes, a background plane including the scanning line position is selected based on a display position set by the position setting unit, and an attribute read address generated by the address generating unit, Address designation means for designating an attribute read address for reading out the display attribute of the background surface selected by the background selection means, and attribute reading means designated by the address designation means. The background generation means for generating a background surface by reading the corresponding display attribute and image data from the background storage means according to the address, and the background when the scanning line position enters a background surface having a different display attribute. And a display control means for instructing the generation means to switch the background surface. According to the invention of claim 4 which depends on claim 3, the display control means includes:
When the scanning line position is out of the background surface, the transparent display is instructed.

In the present invention, when the background surface is changed according to the scrolling of the display surface, the position setting means sets the display position for each of the plurality of background surfaces, and the background determining means sets the background position below the display surface. When the type of surface is determined based on the display position, the background control means generates only the background surface of the type determined by the background determination means according to the scroll position of the display surface, and the background of different types is bordered by the display position. Instruct to display the plane separately. Therefore, even if there are multiple background planes in the display plane, the two background planes are not displayed on top of each other, but are divided and displayed at the display position. The number of accesses to the device does not increase, and there is no fear of reducing the processing speed of the entire device. As a result, it is not necessary to reduce the number of objects that can be displayed on the horizontal scanning line.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The image control apparatus according to the present invention can be applied to, for example, a musical tone generating apparatus which generates musical tones while displaying musical score as musical notes on musical performance information generated in response to musical performance operations. . In the following, the musical tone generating apparatus will be described as an embodiment with reference to the drawings. A. Configuration of Embodiments (1) Overall Configuration FIG. 1 is a block diagram showing the overall configuration of a musical sound generating apparatus which is an embodiment to which an image control apparatus according to the present invention is applied. In the embodiment shown in this figure, the performance information or the automatic performance information generated according to the keyboard operation is displayed on the CRT of the television receiver TV as musical notes on the musical score as the music progresses, and the performance is performed. The musical tone corresponding to the information is generated.

In such an embodiment, 1 is a CPU, which detects an event corresponding to a panel switch operation or a key release operation based on a switch scan, and comprises constituent elements 5 to 7 described later according to the detected event content. The display control unit and the musical sound control unit including the constituent elements 8 to 10 are controlled. Reference numeral 2 denotes a ROM that stores various control programs executed by the CPU 1 as well as characters (object image data, background image data) for displaying musical scores, notes, characters, or a background image.

Reference numeral 3 denotes a RAM, which is provided with various register areas as a work area for the CPU 1 to temporarily store the calculation results and flag values. Reference numeral 4 is a keyboard and switch interface circuit. This interface circuit 4
Is an on / off operation of various operation switches arranged on a panel surface (not shown), or when a key switch provided for each key of a keyboard (not shown) is on / off operated by pressing and releasing keys. Switch event occurs and CP
Supply to U1.

A video display processor (hereinafter referred to as VDP) 5 corresponding to the image control apparatus according to the present invention functions as a so-called CRT controller. That is, the VDP 5 is
While the object image data and the background image data stored in the OM2 are DMA-transferred to a character generation memory (described later) inside itself or a VRAM6 described later, an image to be displayed from the image data stored in each of these memories. The data is extracted and a display control process for determining the display form and display position is performed, and the image data subjected to this process is converted into RGB data representing a display color and output. The configuration / operation of the VDP 5 relating to the gist of the present invention will be described later.

An encoder 7 superimposes a vertical / horizontal synchronizing signal on the RGB data output from the VDP 5 to generate a composite video signal. This composite video signal is supplied to the video input terminal of the television receiver TV, so that an image display-controlled by the VDP 5 is displayed on the cathode ray tube. Reference numeral 8 is a sound source configured by a well-known waveform memory reading method, which reads corresponding waveform data from the waveform ROM 9 based on performance information such as key-on / key-off or velocity generated by the CPU 1 in response to a key release operation. Generates musical tone data. Reference numeral 10 is a D / A converter for converting the musical sound data output from the sound source 8 into an audio output signal in an analog format. The audio output signal output from the D / A converter 10 is emitted as a musical sound by the speaker SP.

(2) Configuration of VDP5 Next, the interface section, the object control section, the background control section, and the color conversion section / synchronization signal generation section that configure the VDP5 will be described with reference to FIG. Interface part The interface part is formed from the components 50 and 51. Reference numeral 50 is a CPU interface circuit that is connected to the CPU bus and sends and receives data to and from the CPU 1. 51 is VR
It is a VRAM interface that manages data exchange with the AM6. Under the instruction of the CPU 1, background image data D _BG and character data D _OBJA are written in the _{VRAM 6} via the interface circuits 50 and 51, respectively. The background image data D _BG described above is data that forms a background surface,
On the other hand, the character data D _OBJA is data that forms an image of the object OBJA displayed on the background surface as a moving image. Further, when these image data are read from the VRAM 6, the read address is given from the CPU 1 side through the interface circuits 50 and 51 and the image data D _BG and D _OBJA read in response to the read addresses are given as in the case of _writing. Are supplied to the controllers 59 and 63 described later.

Object Control Unit The object control unit comprises components 52-62. 5
2 is OBJA for the number of objects displayed on the screen
It is an object memory in which codes and OBJB codes are stored. The OBJA code and the OBJB code are the character data D forming the object OBJA.
And _OBJA, is data representing the attributes of the character data D _OBJb forming the object OBJb. OBJA
The / OBJB code forms one object attribute with three words W0 to W2 each having a 16-bit length. The object attribute here is
The size (area) of the corresponding character data, the display position coordinates, the character name, the color block used, and the like are shown.

Reference numeral 53 is a control register for determining the operation mode of the VDP 5, which includes an object control register for designating the processing form of the object control unit and a group of background control registers for designating the processing form of the background control unit (to be described later). ) And. Among them, the object control register is a register having a total length of 16 bits, and the display control mode is set according to the register value set in each bit position by the CPU 1.

In the lower 5 bits from bit 0 to bit 4 of this object control register, register values S0 to S for designating the allocation form of the object type are designated.
4 is stored. Bit 5 to bit 7 include object A surface (OBJA surface) and object B surface (O
Register values L0 to L2 that define the screen priority order, which is the order in which the BJB surface) and the background surface (BG surface) are overlapped on display, are stored. Further, bits 8 to 10 have BG plane, OBJB plane and OBJ plane, respectively.
An on / off flag for setting display / non-display of the A side is stored. The on / off flag represents display when "1" and non-display when "0".

Reference numeral 54 is a character generation memory,
Character data D forming the object OBJB_OBJBIs written
Remembered. Character data stored in this memory 54
TA D O_BJBConsists of 8 dots in the vertical direction and 8 dots in the horizontal direction
It is formed in cell units. For each dot that makes up one cell
Is assigned a 1-bit color code, which is
In the case of "0", the code is transparent. 55 of CPU1
With a DMA controller that controls DMA transfer according to instructions
is there. The DMA controller 55 is the DM from the CPU 1.
In response to the transfer instruction
That is, the background image data D_BG,Character
Kuta data D_OBJA, Character data D_OBJBAnd OB
One of the JA / OBJB codes becomes the transfer destination
VRAM6, object memory 52 or character
Block transfer to one of the energy memories 54.

An object read controller 56 reads the object attribute corresponding to the horizontal scanning line position on the display side from the above-mentioned object memory 52, and reads the read object attribute from the register values S0 to S0 of the above-mentioned object control register.
The objects are sorted in the order according to the allocation form of the object type designated by S4, and the result is stored in the stack B memory 58 and the stack A memory 57 described later. Therefore, stack A memory 57 and stack B memory 58
Then, each object attribute that can be displayed in one horizontal scanning period, that is, the OBJA / OBJB code is stored, and the OBJA code and the OBJB code stored in these memories 57 and 58 are the controllers 59 and 60 described later. Are read out in the order of display.

The line buffer A controller 59 sequentially reads the OBJA codes stored in the stack A memory 57 in the display order, and reads the character data D _OBJA corresponding to the character name included in the OBJA code from the _VRAM 6. The controller 59 also writes the character data D _OB J _A read from the VRAM 6 in the line buffer A 61, using the X coordinate value included in the OBJA code as a write address. The color block extracted from the OBJA code is _added to the character data D _OBJA written in the line buffer A61.

The line buffer B controller 60 stores the O stored in the stack B memory 58 in display order.
The BJB code is read in order, the character data D _OBJB corresponding to the character name included in the OBJB code is read from the character generation memory 54, and written in the line buffer B62. When writing this, OB
The X coordinate value in the JB code is used as the write address. Further, the color block extracted from the OBJB code is _added to the character data D _OBJB written in the line buffer B62.

Line buffer A61, line buffer B
A plurality of line buffer memories for temporarily storing character data (image data) for one horizontal scanning line are provided in each of 62, and at least for the scanning lines displayed in synchronization with the current horizontal scanning. In addition to the character data, the character data for the scanning lines displayed in synchronization with the next horizontal scanning is also temporarily stored. Further, in the line buffer A61 and the line buffer B62, the above-described controllers 59 and 60 are controlled so as to alternately switch the buffer memories in synchronization with horizontal scanning to perform line reading or line writing. That is, the character data is read from one buffer memory while the character data is written in the other buffer memory.

Background Control Unit The background control unit is a constituent element relating to the gist of the present invention, and includes a background control register group (described later) included in the control register 53, a BG data read controller 63, and It is composed of a BG line buffer 64. The BG data read controller 63 selectively reads the character data D _BGA and D _BGB stored in the VRAM 6 in accordance with the scroll processing based on various display control data set in the background control register group described later, and The background surface BGA and the background surface BGB formed by the character data D _BGA and D _BGB are displayed separately. BG
The data register 64 stores at least one horizontal scanning line of either the background surface BGA corresponding to the divided display or the character data D _BGA , D _BGB forming the background surface BGB, and stored under a predetermined horizontal synchronization timing. Read out and supplied to the color conversion unit described later.

According to the present invention, even if a plurality of background planes are provided, this background control unit divides and displays these background planes, and only one background plane is always displayed on the screen. A reduction in processing speed is avoided without reducing the number of objects that can be displayed as moving images per line. The detailed configuration, data content, and processing form of the background control unit that divides and displays the background surface will be described later.

The color conversion section / synchronization signal generation section 65 gives a screen priority, and a color look-up table section for converting the image data of each screen to which the priority is given to color data (RGB data) and outputting it. Is. In the table section 65, first, the image data (character data D _OBJA , character data D _OBJB, and background) output from the above-described line buffer A61, line buffer B62, and BG line buffer 64 in synchronization with horizontal scanning. Priorities are given to the image data D _BG ). The priority order indicating the order of overlapping the screens is determined according to the register values L0 to L1 in the object control register described above.

Further, in the table section 65, the color blocks added to the respective image data (character data D _OBJA , character data D _OBJB and background image data D _BG ) to which the screen priority has been _assigned as described above. According to the above, the lookup table LUT of the corresponding color bank is selected, and based on the selected lookup table LUT, the character data D _OBJA , the character data D _OBJB, and the background image data D _BG are converted into color data (RGB data) and output. To do.

Next, 66 is a D / A converter, which converts the color data (RGB data) output from the color look-up table unit 65 into color signals for each color RGB and outputs the color signals. It should be noted that these color signals are sent to the encoder 7 described above.
In, the horizontal / vertical sync signals are superimposed to form a composite video signal. Reference numeral 67 is a synchronization signal generation unit for multiplying and oscillating the original oscillation clock of the crystal oscillator X'tal to generate a horizontal synchronization / vertical synchronization clock, and supplying this to each unit such as an object control unit and a background control unit in the VDP 5. Is.

(3) Structure of Background Control Unit Here, the contents of the background control registers provided in the control register 53 will be described first, and then, based on the display control data stored in these register groups. The configuration of the background control unit that divides and displays a plurality of background planes according to scroll processing will be described. The control register 53 described above is provided with a background control register group that stores various display control data that determines the operation mode of the background control unit. This register group
Register CES _BGA , Register SCR _BGA , Register CG
It is composed of an ES _BGA , a register CES _BGB , a register DCR _BGB , a register CGES _BGB and a register CESZ _BGA , and each register configuration will be sequentially described below.

First, the register CES _BGA is the VRAM 6
It is a register for storing the start address of the BGA code stored in. The BGA code represents the display attribute of the character data D _BGA forming the background surface BGA. The display attribute here is data that specifies a color block and a character name (image type). As shown in FIG. 4, this register CES _BGA has B in the upper 8 bits (9SB to MSB) of the 16-bit length register area.
GA code start addresses A10 to A17 are stored. The register SCR _BGA is a register for storing the coordinates (X, Y) of the position where scrolling is started on the background surface BGA, and as shown in FIG. 5, the coordinates (X, Y) are two words W0 to W1. Y). That is, the scroll start X coordinate value is the lower 11 bits (11S
B to LSB) while the scroll start Y coordinate value is the lower 10 bits (10SB to LSB) of the word W1.
It is expressed by.

The register CGES _BGA is a register for storing the start address of the character data D _BGA stored in the VRAM 6, and as shown in FIG. 6, in the upper 8 bits (9SB to MSB) of the 16-bit length register area. The start addresses A10 to A17 are stored. Register CES
_{The BGB} is a register for storing the start address of the BGB code stored in the VRAM 6 as with the register CES _BGA . The BGB code represents the display attribute of the character data D _BGB forming the background surface BGB. This register CES _BGA is set to 1 as shown in FIG.
Upper 8 bits of register area of 6-bit length (9SB ~
BGB code start addresses A10 to A17 are stored in MSB).

The register DCR _BGB is a register that stores the coordinates (X, Y) of the position where the background surface BGA and the background surface BGB are divided. As shown in FIG. 8, this register DCR _BGB represents the X coordinate value by the lower 11 bits (11SB to LSB) of the word W0 and the Y coordinate value by the word W.
It is represented by the lower 10 bits of 1 (10SB to LSB). The register CGES _BGB , like the register CGES _BGA described above, stores the character data D _BGB stored in the VRAM 6.
9, which is a register for storing the start address of, the start addresses A10 to A17 are stored in the upper 8 bits (9SB to MSB) of the 16-bit length register area. The register CESZ _BGA temporarily stores display control data that defines the size of the background surface BGA, and as shown in FIG. 10, stores the lower 2 bits (2SB, LSB) of the 16-bit length register area. Size accordingly.

Next, the above-mentioned registers CES _BGA , SC
R _BGA , CGES _BGA , CES _BGB , DCR _BGB , CGES
Display control data stored in _BGB and CESZ _BGA ,
The terms related to this will be explained. First, when the pixel area of 8 dots × 8 dots is defined as one cell, the background surface BGA is, as shown in FIG. 11, one block consisting of 64 cells in the horizontal direction × 32 cells in the vertical direction as a basic unit, and a maximum of 4 blocks.
It may have a display area for blocks (block 0 to block 3). In such a display area, the register SCR
_The scroll start coordinates (X, Y) stored in the _BGA specify the scroll position of the display surface DSP, that is, the cell in which the upper left corner of the display surface DSP is placed. The display surface DSP has a display range of up to 336 dots in the horizontal (X) direction and 224 lines in the vertical (Y) direction from the center dot of the cell designated by the scroll start coordinates (X, Y). This display range is displayed on the screen.

FIG. 12 shows the format of the BGA code that defines the background surface BGA. The BGA code is a display attribute indicating the display color and image type for each dot, and all 1
A color block representing the display color is assigned to the upper 4 bits of the 6-bit length, and a character name indicating the type of image is assigned to the lower 12 bits. Then, the BGA code for each dot is addressed in block order. The address shown in FIG. 12 is the background surface BG.
It represents a relative address from the origin of A (upper left corner).

The size of the background surface BGA is specified by the display control data stored in the lower 2 bits of the above-mentioned register CESZ _BGA . This display control data is "00"
At the time of, as shown in FIG.
One block consisting of 32 cells in the vertical direction is combined with two blocks in the vertical and horizontal directions to form a display area of 128 cells in the horizontal (X) direction × 64 cells in the vertical (Y) direction, which is composed of blocks 0 to 3. Further, the display control data is "01", "1".
In the case of "0" and "11", the display area is shown in FIGS. In the case of the present embodiment, in the following description, the background surface BGA has a display area of blocks 0 to 3 of 128 cells in the horizontal (X) direction × 64 cells in the vertical (Y) direction.

On the other hand, when the background surface BGB has a pixel range of 8 dots × 8 dots as one cell, as shown in FIG.
One block consisting of 64 cells in the horizontal direction and 32 cells in the vertical direction is the maximum display area. The origin of the display area, the display position coordinates are stored in the aforementioned register DCR _BGB (X,
Y). BGB that defines the background surface BGB
As shown in FIG. 15, the code is represented by one word 16 bits long per cell. A color block is assigned to the upper 4 bits and a character name is assigned to the lower 12 bits.

Background surface BGA defined by BGA code
And the display surface DSP have the relationship shown in FIG. That is, the origin (upper left corner) position of the display surface DSP is defined by the scroll start position coordinates (X, Y) stored in the above-mentioned register SCR _BGA (see FIG. 5), and scrolls in the vertical and horizontal directions from that position. Depending on the display surface DSP is background surface B
Move on GA. If the display surface DSP fits on the background surface BGA, the background surface BG of the portion corresponding to the display surface DSP
A is displayed on the screen. When the display surface DSP deviates from the background surface BGA, the deviated area becomes a back drop surface and is displayed in a single color.

On the other hand, on the background surface BGB, 64 cells × 32
42 cells near the origin in one block of cells x 28
The area of the cell is defined as a viewable cell. Therefore, by rewriting the display position coordinates (X, Y) of the register DCR _BGB indicating the origin of the display area, the display surface DSP can be relatively scrolled on the background surface BGB. However, in that case, the display position coordinates (X, Y)
When X ≧ 336 and Y ≧ 224, the display is out of the display surface and the display cannot be performed. When the display surface DSP is scrolled to an area where the background surface BGA and the background surface BGB overlap each other, FIG.
As shown in FIG. 8, only the background surface BGB is displayed on the screen by the split display. In addition, the background surface BGA,
When an area outside both of BGB is entered, the area becomes a back drop surface and is displayed transparently (single color).

Next, back to FIG. 3 again, the above-mentioned register _{CES BGA, SCR BGA, CGES BG} A, CES BGB, DC
The configuration of the background control unit that separately displays the background surface BGA and the background surface BGB according to the contents of R _BGB , CGES _BGB, and CESZ _BGA will be described. The BG code read controller 63 is formed of the components 63a to 63d. Reference numeral 63a is a BG control circuit, which controls data exchange between the elements 63b to 63d according to the contents of the respective register groups. Reference numeral 63b is a code address calculation unit, which includes BGA code address generation circuits 63b-1 and BGB.
Code address generation circuit 63b-2 and selection circuit 63
b-3. BGA code address generation circuit 63b-1 and BGB code address generation circuit 63b
-2 is a VRAM in response to an instruction from the BG control circuit 63a.
Read addresses ADC _BGA and ADC _BGB for reading the BGA code or the BGB code from the 6 side are calculated.

That is, the generating circuits 63b-1, 63b-
2, the start address of the BGA code stored in the register CES _BGA and the register CES _BGB respectively, BG
Read address ADC _BGA , AD in consideration of the cell position corresponding to the scroll processing to the start address of the B code
Generate C _BGB . The selection circuit 63b-3 has a register D
The address ADC _BGA , ADC depending on the division display position of the background surface BGA and the background surface BGB stored in CR _BGB.
Either _BGB is selected and supplied to the VRAM interface circuit 51. That is, if scrolling in the background surface BGA, the address ADC _BGA output from the generating circuit 63b-1 is selected, while if in the background surface BGB, ADC _BGB output from the generating circuit 63b-2. Select.

Reference numeral 63c is a character read address conversion circuit, which is VR according to the code read addresses ADC _BGA and ADC _BGB generated by the code address calculation unit 63b.
BGA code (or BG) read from the AM6 side
A character address CA for reading the corresponding character data D _BGA , D _BGB based on the (B code)
_BGA and CA _BGB are generated. Incidentally, the background storage area E _BG provided VRAM6, as shown in FIG. 19, the area background surface BGA, character data D _BGA forming the BGB, is D _B G _B is stored as shared E1 And area E2 where BGA code data is stored
And an area E3 in which BGB code data is stored.

As shown in FIG. 20, the character data D _BGA and D _BGB forming the background surfaces BGA and BGB are formed in a unit of 8 dots in the vertical direction × 8 dots in the horizontal direction, and each dot has 4 dots. A 16-color display including transparent colors is assigned by assigning a bit color code. As shown in FIG. 21, the color code for one cell is represented by 16 words, each word having a 16-bit length, that is, D0 to D15. That is, the color code of the dots d00 to d03 in one cell is stored in the word D0, and the next dot d04 to
d07 is stored in word D1. After that, each dot d1
0 to d13, d14 to d17, ..., d74 to d77 are sequentially stored in the words D1 to D15 in the same manner. Therefore, the area E in which the character data D _BGA and D _BGB forming the background surfaces BGA and BGB are stored so as to be shared
65536 as 16 words x 4096 cells in 1
Character data for words is stored.

Next, returning to FIG. 3 again, the structure of the background control section will be described. In FIG.
Reference numeral 3d is a line buffer write control circuit. This circuit 63d has a character address CA _BGA , CA generated by the character read address conversion circuit 63c described above.
_The character data D _BGA , D _BGB read from the area E1 (see FIG. 19) of the VRAM 6 in accordance with the _BGB is written to the BG line buffer 64 in the subsequent stage according to the horizontal synchronization clock. Reference numeral 63e is a line buffer read control circuit, which instructs the BG line buffer 64 to read.

The BG line buffer 64 has at least a buffer memory which outputs character data and a color block for one scanning line in response to a read instruction from the control circuit 63e in synchronization with the current horizontal scanning, and a control circuit 63d. And a buffer memory for temporarily storing character data and color blocks corresponding to the next horizontal scanning based on the writing instruction of the above. While reading character data and color blocks from one buffer memory, character data and color blocks are read to the other buffer memory. It is designed to write blocks. The character data output from the BG line buffer 64 is supplied to the above-described color lookup table unit 65 and converted into color data (RGB data).

Here, the color look-up table section 6
22 shows an example of the lookup table LUT provided in FIG. As shown in this figure, color data of 16 colors (output color code) is assigned to each color block, and the color data is composed of 12 bits of 4 bits for each color of RGB. Note that this lookup table L
UT is accessible from CPU1
Since the address and the read address at the time of table conversion are shared, it is possible to rewrite the look-up table LUT of a required color block.

B. Operation of Embodiment Next, as the operation of the present embodiment, the background display division display processing performed by the background control unit will be described. The operation described below is performed on the display surface D on the background surfaces BGA and BGB.
At the time of the scroll processing for moving the SP, the CPU 1 sets the scroll start position coordinate (X, Y) in the register SCR _BGA.
Shall be set to other registers CES _BGA , CG
ES _BGA , CES _BGB , DCR _BGB , CGES _BGB and C
Also for ESZ _BGA , the predetermined display control data is CPU
It shall be written by 1.

In such a state, scroll processing
Is instructed, the background control unit causes the display surface D
In order to form the background surface corresponding to the position of SP, it is shown in FIG.
Execute the processing flow. Below, data for each step
The details of the operation will be described. Calculation of BGA code read address When the process proceeds to step S1, the background control unit performs processing.
BG corresponding to the cell on the horizontal scan line to be processed
BGA code read address for reading A code
ADC_BGATo calculate. This read address ADC_BGA
Is the BGA code address generation circuit 63b-1 described above.
(See FIG. 3). Read BGA code
Address ADC_BGAIs displayed on the display surface DSP
The cell position on the horizontal scan line to be processed
Surface BGA cell coordinates (CX B_GA, CY_BGA)
It is nothing but a thing.

That is, the coordinate position CY _BGA is displayed on the display surface DS.
The horizontal scan line position currently processed on P and the register S
It is represented by the lower 6 bits after adding the scroll start Y coordinate value stored in the word W1 (see FIG. 5) of the CR _BGA and removing the lower 3 bits. The reason why the lower 3 bits are bit-shifted is that one cell is formed by 8 dots, so that the bit shift is expressed as a cell unit position. The lower 6 bits of the address data DY thus bit-shifted are assigned to the upper 6 bits of the BGA code read address ADC _BGA .

On the other hand, the coordinate position CX _BGA is the display surface DSP.
The horizontal position of the cell currently processed above and the register SCR
It is represented by the lower 6 bits after adding the scroll start X coordinate value stored in the word W0 (see FIG. 5) of the _BGA and removing the lower 3 bits. The lower 6 bits of the address data DX after the bit shift is assigned to the lower 6 bits of the BGA code read address ADC _BGA . Therefore, the BGA code read address ADC _BGA is composed of the address data DY assigned to the upper 6 bits and the address data DX assigned to the lower 6 bits.

In this embodiment, since the background surface BGA has a size of 2 × 2 blocks in the vertical and horizontal directions, the horizontal scanning line position currently processed on the display surface DSP and the register SCR.
_When the upper 2 bits (MSB, 9SB) of the added value of the _BGA scroll start Y coordinate value is other than "00", the transparent flag "1" is set on the assumption that the background surface BGA has been removed by scrolling. Similarly, the upper two bits of the sum of the scroll starting X-coordinate values of the lateral position and register SCR _BG A cell currently processed on the display screen DSP (MSB,
10SB) is other than "00", it is considered that the background surface BGA is off by scrolling, and M of the address data DX
The transparent flag "1" is set in SB.

Calculation of BGB code read address ADC BGA code read address ADC_BGARaw
If it is done, the background control unit performs step S2.
(See FIG. 23), and read BGB code read address
ADC_BGBTo calculate. This read address ADC_BGB
Is the BGB code address generation circuit 63b-2 described above.
(See FIG. 3). Read BGB code
Address ADC_BGBIs displayed on the display surface DSP
The cell position on the horizontal scan line to be processed
Cell coordinates of surface BGB (CX B_GB, CY_BGB)
Of. The background surface BGB has a size of 1 block.
You.

The coordinate position CY _BGB is set from the horizontal scan line position currently processed on the display surface DSP to the register DCR _BGB.
It is represented by the lower 5 bits after subtracting the Y coordinate value stored in the word W1 (see FIG. 8) and removing the lower 3 bits. The lower 5 bits of the address data DY after being shifted by 3 bits are the BGB code read address AD.
_{Assigned to} the upper 5 bits of C _BGB . In contrast,
At the coordinate position CX _BGB , the maximum display size in the horizontal direction is 33.
Since it is 6 dots and it is handled as a cell unit of 8 dot width, "0-43" is used as the cell number. Corresponding to this, the word in the register DCR _BGB from the horizontal position currently processed on the display surface DSP. The X coordinate value +9 stored in W0 (see FIG. 8) is subtracted. The lower 6 bits after subtracting the lower 3 bits from the subtraction result of the total 9-bit length become the address data DX, and the BGB code read address AD
_{Assigned to} the lower 6 bits of C _BGB . Therefore,
The BGB code read address ADC _BGB is composed of address data DY assigned to the upper 6 bits and address data DX assigned to the lower 6 bits.

Selection of BGA code / BGB code When the BGA code read address ADC _BGA and the BGB code read address ADC _BGB are generated, the background control unit advances the processing to step S3 to determine whether the background surfaces BGA and BGB are present. Since only one of them is displayed on the screen, one of the above addresses ADC _BGA and ADC _BGB is selected. This address selection process is performed by the selection circuit 6 described above.
3b-3 executed by the display surface DSP
The cell position (CS _X ,
If CS _Y) is an on background surface BGA, select the address ADC _BGA side for reading the BGA code, background plane BG
If it is on B, the address A for reading the BGB code
Select the DC _BGB side.

That is, in step S3, first, the value obtained by subtracting the cell Y coordinate value CS _Y from the Y coordinate value stored in the word W1 (see FIG. 8) of the register DCR _BGB is stored in the register DCR _BGB . X stored in word W0
From the value obtained by adding 8 dots to the coordinate value, the cell Y coordinate value CS _X
When the value obtained by subtracting is D, it is determined whether or not C ≦ 0 and D <0, that is, whether or not the background area BGB is included in the cell area of the cell number −1 currently being processed. Here, if C ≦ 0 and D <0, the cell area of the cell number −1 currently being processed is the background surface BGB, so the BGB code read address ADC _BGB side is selected. Address AD to read the code
C Select the _BGA side.

When the address ADC _BGA side is selected, this BGA code read address ADC
The _BGA, B stored in the register CES _BGA (see FIG. 4)
BGA code data is read from the storage area E2 (see FIG. 19) of the VRAM 6 according to the offset address obtained by adding the GA code area start address value. on the other hand,
When the address ADC _BGB side is selected, the register CES is set to the BGB code read address ADC _BGB.
From the storage area E3 (see FIG. 19) of the VRAM 6 to the BGB according to the offset address obtained by adding the BGB code area start address value stored in the _BGB (see FIG. 7).
Read the code data.

Calculation of Character Address Next, in step S4, the background control unit reads the code data of the background surfaces BGA and BGB corresponding to the scroll position from the VRAM 6, and the background surface is read based on the read code data. A character address CA _BGA for reading the character data D _BGA and D _BGB to be formed from the VRAM 6 is calculated. To convert the BGA code into the character address CA _BGA , the character name included in the lower 12 bits of the BGA code shown in FIG. 12 is replaced with the upper 12 bits of the character address CA _BGA , and the word W of the register SCR _BGA is converted.
Of the 10-bit length scroll start Y coordinate value stored in 1 (see FIG. 5), the lower 3 bits are allocated to 2SB to 4SB of the character address CA _BGA . further,
"0" is _{added to} the LSB of the address CA _BGA 16
1-bit bit address CA _BGA 0 and 16-bit 1-word address CA with "1" added to LSB
_BGA 1 and are generated.

Then, the two-word address CA _BGA
By giving 0, CA _BGA 1 to VRAM 6 in a time-sharing manner, the row / column position on the same memory is specified, whereby V
The corresponding character data D _BGA is read from the RAM 6. In the case of the present embodiment, as shown in FIG. 19, the character data is "0000" in the VRAM6.
Since it is addressed from "H", it is not necessary to perform the address offset, but when the character data is mapped to the offset address position, the register CGES _BGA (for the address CA _BGA 0 and the address CA _BGA 1 is described above). It is necessary to add the character generation area start address stored in (see FIG. 6).

On the other hand, in order to convert the BGB code into the character address CA _BGB , the character name stored in the lower 12 bits of the BGB code shown in FIG.
The upper 12 bits of the character address CA _BGB are replaced. The Y coordinate value stored in the word W1 (see FIG. 8) of the register DCR _BGB is subtracted from the horizontal scanning line position currently processed on the display surface DSP, and the lower 3 bits of the subtraction result are 2SB to the character address CA _BGB . Allocate to 4SB. Further, a 16-bit 1-word address CA in which "0" is added to the LSB of the address CA _BGB
BGB 0 and 16-bit 1-word address CA _BGB 1 in which “1” is _added to LSB are generated.

The address CA of these two words
_BGB 0 and CA _BGB 1 are sequentially applied to the VRAM 6 in a time division manner to read the corresponding character data D _BGB . Note that VR
For the convenience of mapping in AM6, when character data is offset-addressed, the character generation area start address stored in the above-mentioned register CGES _BGB (see FIG. 9) is added to address CA _BGB 0 and address CA _BGB 1. To do.

Writing to BG line buffer Character address C obtained as described above
When the character data is read from the VRAM 6 according to A _BGA and CA _BGB , the background control unit proceeds to step S5 and sets the color block and the character data in the BG line buffer 64. The BG line buffer 64 has a character buffer area in which character data for at least one horizontal scanning line is written. In the case of this embodiment, the character buffer area has a length of 4 bits × 352 dots. When the character data D _BGA forming the background surface BGA is written in this area, the cell position (0 to 43) on the horizontal scanning line currently processed on the display surface DSP is represented by the upper 6 bits, and within the corresponding cell. Line writing is performed according to a write address in which the dot position is represented by the lower 3 bits.

The color block is written in the color block buffer area in the BG line buffer 64. In this embodiment, the color block buffer area has a 4-bit length × 44 lines. The write address to this area is the cell position (0 to 43) on the horizontal scanning line represented by the upper 6 bits. The cell position on the horizontal scanning line currently processed on the display surface DSP is the background surface B.
The character data D that was read when the value was out of GA
Data for transparent display is buffer-set regardless of _BGA and color block.

On the other hand, when writing the character data D _BGB in the character buffer area, a write address having a total length of 12 bits is used. The upper 6 bits (MSB to 7SB) of this write address represent the cell position (0 to 43) on the horizontal scanning line currently processed on the display surface DSP.
The following 6SB to 4SB are word W of register DCR _BGB .
1 (see FIG. 8) corresponds to the lower 3 bits of the Y coordinate value. 3SB to LSB represent dot positions in the corresponding cell. The color block is written in the color block buffer area in the BG line buffer 64 according to the write address in which the cell position (0 to 43) on the horizontal scanning line is represented by the upper 6 bits.

Readout from BG line buffer 64 Next, in step S6, the background control section receives the character data and the character data written in the BG line buffer 64 in response to an instruction from the line buffer read control circuit 63e. Read a color block. The line buffer read control circuit 63e includes a base counter BCN1 that generates a counter output for reading the line buffer 64 in synchronization with the screen display timing.

A read address is generated by adding the lower 3-bit value of the word W0 of the register SCR _BGA (see FIG. 5) to the counter value of 9-bit length output from the base counter BCN1, and in response thereto. The character data D _BGA of the background surface _BGA is read from the line buffer 64. The color block is read out according to a read address in which cell positions (0 to 43) on the horizontal scanning line are represented by upper 6 bits.

On the other hand, the character data D of the background surface BGB
_When reading _BGB , the lower 3 bits of the 9-bit length counter value output from the base counter BCN1 are invalidated, and the lower 3 bits of the word W0 (see FIG. 8) of the register DCR _BGB are read. A total 9-bit read address is generated and used by adding the value obtained by adding "16" and the value of the lower 3 bits of the output of the counter that counts the horizontal synchronization counter value. The color block corresponding to this corresponds to the cell position (0
To 43) are read according to the read address represented by the upper 6 bits.

As described above, the character data and the color block for each background are stored in the BG line buffer 64.
However, in order to switch the background surface in accordance with the scroll position and display the background in a divided manner, it is necessary to switch the read address calculation algorithm described above. The operation of determining the switching will be described below. First, switching is determined according to the horizontal scanning line position. That is, word W1 of register DCR _BGB
The horizontal scanning line position currently processed is subtracted from the Y coordinate value stored in (see FIG. 8), and whether the result is 0 or less, that is, the horizontal scanning line currently processed is on the background surface BGB. To determine if it exists. Next, switching is determined according to the cell position on the horizontal scanning line.
From the counter value of the counter BCN1 described above to the register D
The X coordinate value stored in the word W0 of CR _BGB (see FIG. 8) is subtracted, and whether or not the result is 0 or more, that is,
The cell on the horizontal scanning line currently being processed is the background surface BG.
It is determined whether or not it exists on B.

Then, the read address corresponding to the background surface BGB is generated only when both of the above two determination conditions are satisfied, and in the other cases, the read address corresponding to the background surface BGA is generated. As a result, it becomes possible to switch the background surface in accordance with the scroll processing and display the background in a divided manner, and always display only the background surface on the display surface DS.
Since the screen is displayed on P, it is not necessary to reduce the number of objects that can be displayed as a moving image per horizontal scanning line.

Generation of Color Signal Next, in step S7 (FIG. 23), the background control unit stores the character data D _BGA , D _BGB and the color block read from the BG line buffer 64 as described above. Color lookup table section 65
To supply. In the table portion 65, the character data D
A color look-up table (see FIG. 22) of color blocks corresponding to _BGA and D _BGB is selected, and an output color code (RGB data: color signal) is converted based on the table. If the character data D _BGA , D _BGB and the color block are transparent data, the color of the monochromatic surface (backdrop surface) is displayed.

Next, with respect to the processing timings of the above items to be processed in the background control section, FIG.
This will be described with reference to FIG. First, when the VDP 5 is generating the RGB output of the horizontal scanning line n-1 at time t ₀ , the BGA code address generating circuit 63b-1 and the BGB code address generating circuit 63b-2 are respectively in the background control section. BGA code / BGB code read address ADC corresponding to horizontal scanning line n + 2
While calculating _BGA and ADC _BGB , the selection circuit 63b-3 selects and outputs either BGA / BGB code read address ADC _BGA or ADC _BGB according to the scroll position.

Next, when the address calculation is completed, the character
The cue read address conversion circuit 63c uses the address A
DC_BGA, ADC_BGBRead from VRAM6 side according to
Import the output BGA code or BGB code
Character data forming the horizontal scan line n + 2
D_BGA, D_BGBCharacter address CA for reading B
_GA, C_BGBGenerate And after this, the line buff
In the write control circuit 63d, the character address CA
_BGA, C_BGBHorizontal scanning read from the VRAM 6 according to
Character data D forming line n + 2_BGA, D_BGB
And the corresponding color block to the BG line bar.
Write to the buffer 64.

While the line buffer write control circuit 63d is writing the color block corresponding to the character data D _BGA and D _BGB to the BG line buffer 64,
BG is controlled by the line buffer read control circuit 63e.
The character data D _BGA , D _{BGB of the} current scanning line n and the color block corresponding to the character data are sequentially read from the line buffer 64, and are converted into RGB data in synchronization with the horizontal synchronizing clock and displayed on the screen.

In such processing, if scroll processing is performed within the background surface BGA, for example, as shown in FIG. 25, the background surface BGA that fits on the display surface DSP is displayed as it is as a background image, and the background surface BGA is displayed. The deviated area is displayed as a transparent (monochromatic) background surface. Further, as shown in FIG. 26, when the background surface BGB is arranged so as to partially overlap the background surface BGA, the background surface BGA and the background surface BGB are divided and displayed. That is, even if the background surface BGA and the background surface BGB exist on the display surface DSP, the background surfaces BGA and BGB are not overlapped and displayed on the screen, but are divided and displayed in a set area.

C. Modified Example In the above-described embodiment, the write address generation when the character buffer area has a 4-bit length × 352 dots and the color block area has a 4-bit length × 44 lines has been disclosed. Even when the color block area is 4 bits long × 64 bits and the color block area is 4 bits long × 8 lines, similar to the embodiment, “writing to the BG line buffer 64” and “BG” are performed.
"Reading from the read line buffer 64" will be described.

Writing to BG line buffer 64 In a character buffer area of 4 bits long × 64 bits,
Character data D forming the background surface BGA_BGAWrite
Cell position on the horizontal scan line currently processed
(0 to 43) is represented by 6 bits, and the lower 3 bits
Write address that represents the dot position in the corresponding cell
Using And 4-bit length x 8-line color blur
The data D in the lock buffer area B_GACorresponding to
-To write a block, the cell position on the horizontal scan line
Write the lower 3 bits of the 6-bit value representing (0 to 43)
Only address.

On the other hand, when writing the character data D _BGB forming the background surface BGB in the same area, the cell position (0 to 43) on the horizontal scanning line currently processed is set to the upper 6 bits and the register DCR _{BGB is set.} The lower 3 bits of the X coordinate value stored in the word W0 of FIG. 8 (see FIG. 8) are set to the lower 3 bits, and 3 bits representing the dot position in the corresponding cell are added to the data of the total 9 bits. 6 bits are used for the write address. As the address for writing the color block, the upper 3 bits of the write address of the character data D _BGB is used.

Reading from BG line buffer 64 In order to read the character data D _BGA of the background surface BGA from the character buffer area in response to the above-mentioned writing, the counter value of 9-bit length output from the above-mentioned base counter BCN1. To the word W of the register SCR _BGA
0 (see FIG. 5) The lower 6 bits of the value obtained by adding the lower 3 bits are used as the read address. Then, to read the color block corresponding to the data D _BGA from the color block buffer area, the character data D _BGA
The upper 3 bits of the read address are used.

On the other hand, the read address of the character data D _BGB of the background surface BGA is the base counter BC.
The register DCR _{BGB is used} for the invalid value of the lower 3 bits of the 9-bit length counter value output from N1.
Of the word W0 of FIG. 8 (see FIG. 8) and the value of the lower 3 bits of the output of the counter that counts the horizontal synchronization counter value and the lower 6 Use bits. The color block corresponding to this uses the upper 3 bits of the read address of the character data D _BGB .

Also in the modification, the algorithm for calculating the read address is switched according to the scroll position, as in the above-described embodiment. That is, it is determined whether or not the horizontal scanning line currently being processed is present on the background surface BGB, while it is determined whether or not the cell on the horizontal scanning line currently being processed is present on the background surface BGB. And the read address corresponding to the background surface BGB is generated only when all of these determination conditions are satisfied, and in other cases, the read address corresponding to the background surface BGA is generated. In this way, the BG line buffer 64
Even if the size of the character buffer area and the color block area of is changed, the write address /
It is understood that the background planes BGA and BGB can be divided and displayed according to the scrolling process by changing the generation mode of the read address, as in the above-described embodiment.

As described above, according to this embodiment,
Even if the background surface BGA and the background surface BGB exist on the display surface DSP, the background surface BGA and the background surface BGB are not overlapped and displayed on the screen, but are divided and displayed in a set area, so that the number of background surfaces increases. However, the number of accesses to the VRAM does not increase, and there is no fear of reducing the processing speed of the entire device. Therefore, it is not necessary to reduce the number of objects that can be displayed on the horizontal scanning line. Therefore, in the past, since a measure was taken to reduce the number of moving screens when a large number of types of background surfaces were displayed, the adverse effect of a monotonous display form occurred, whereas the present invention eliminates such adverse effects. As a result, it is possible to realize a variety of complicated display forms.

In the present embodiment, the background surfaces BGA, BG
Although there are two types of B, the present invention is not limited to these two backgrounds and can be applied to the case of having more than two backgrounds. The point is that the coordinate position for switching the background plane is determined in advance, and the address is generated so that the background is switched when the coordinate position is exceeded. Further, by providing a plurality of systems of the background control unit described above and operating these systems in a time-division manner, it is possible to realize a more varied and complicated display form without reducing the processing speed.

[0080]

According to the present invention, when the background surface is changed in accordance with the scrolling of the display surface, the position setting means sets the display position for each of the plurality of background surfaces, and the background discriminating means moves below the display surface. When the type of the background surface located on the display position is determined based on the display position, the background control means generates only the background surface of the type determined by the background determination means according to the scroll position of the display surface, and the display position is a boundary. Instruct to display different types of background planes separately. Therefore, even if there are multiple background planes in the display plane, the two background planes are not displayed on top of each other, but are divided and displayed at the display position. The number of accesses to the device does not increase, and there is no fear of reducing the processing speed of the entire device. As a result, it is possible to switch and display a plurality of background screens without reducing the number of objects that can display a moving image per horizontal scanning line.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment according to the present invention.

FIG. 2 is a block diagram showing a configuration of a VDP 5 in the embodiment.

FIG. 3 is a block diagram showing a configuration of a background control unit in the embodiment.

FIG. 4 is a diagram showing a configuration of a BGA code area start address register CES _{BGA in} the embodiment.

FIG. 5 is a diagram showing a configuration of a BGA start position register SCR _{BGA in} the embodiment.

FIG. 6 is a diagram showing a configuration of a BGA character generation area start address register CGES _{BGA in} the same embodiment.

FIG. 7 is a diagram showing a configuration of a BGB code area start address register CES _{BGB in} the embodiment.

FIG. 8 is a BGB display coordinate register DC in the embodiment.
It is a figure which shows the structure of R _BGB .

FIG. 9 is a diagram showing a configuration of a BGB character generation area start address register CGES _{BGB in} the embodiment.

FIG. 10 is a diagram showing a configuration of a BGA code area size register CESZ _{BGA in} the embodiment.

FIG. 11 is a diagram for explaining the relationship between the background surface BGA and the display surface DSP.

FIG. 12 is a diagram for explaining the data format of a BGA code.

FIG. 13 is a diagram for explaining a block combination of the background surface BGA.

FIG. 14 is a diagram for explaining the relationship between the background surface BGB and the display surface DSP.

FIG. 15 is a diagram illustrating a data format of a BGB code.

FIG. 16 is a diagram showing a relationship between a background surface BGA and a display surface DSP.

FIG. 17 is a diagram showing a relationship between a background surface BGB and a display surface DSP.

FIG. 18 is a diagram showing a relationship between a background surface BGA and a background surface BGB.

FIG. 19 is a memory map showing the structure of the VRAM 6 in the embodiment.

FIG. 20 is a diagram for explaining a cell configuration of character data D _BGA and D _BGB .

FIG. 21 is a diagram showing a data structure of character data D _BGA and D _BGB .

FIG. 22 is a diagram showing an example of a color lookup table.

FIG. 23 is a flow chart for explaining the operation in the embodiment.

FIG. 24 is a time chart for explaining the operation of the embodiment.

FIG. 25 is a diagram showing an operation example in the embodiment.

FIG. 26 is a diagram showing an operation example in the embodiment.

[Explanation of symbols]

1 CPU (position setting means) 2 ROM 3 RAM 5 VDP 6 VRAM 53 control register (position setting means) 63 BG data read controller (background determination means,
Background control means) 64 BG line buffer

Claims (4)

[Claims] 1. A device for changing a background surface according to scrolling of the display surface, wherein the position setting means sets a display position for each of a plurality of background surfaces, and the type of the background surface located below the display surface is set. Background discrimination means for discriminating based on the display position, and only background types of the type discriminated by the background discrimination means according to the scroll position of the display surface are generated, and different types of background planes are divided and displayed at the display position. An image control device, comprising: 2. A background storage unit for storing display attributes for each of a plurality of background surfaces and image data forming a background surface associated with each of the display attributes, and a display position for each of the plurality of background surfaces. The position setting means for setting, the background discriminating means for discriminating the display attribute of the background surface located below the display surface based on the display position, and the display attribute discriminated by the background discriminating means according to the scroll position of the display surface. Background reading means for reading corresponding image data from the background storage means, a background surface is generated based on the image data read by the background reading means, and the background surface having different display attributes is divided at the display position. An image control apparatus comprising: a background control unit for instructing display. 3. A background storage unit for storing display attributes for each of a plurality of background surfaces and image data forming a background surface associated with the display attributes, and setting display positions for each of the plurality of background surfaces. Position setting means, address generating means for generating an attribute read address for reading out display attributes for each background surface from the background storage means in correspondence with a scanning line position on the display surface, and among the plurality of background surfaces, A background selecting means for selecting a background surface including the scanning line position based on the display position set by the position setting means, and an attribute read address generated by the address generating means, selected by the background selecting means. The address specifying means for specifying the attribute read address for reading the display attribute of the background surface and the attribute read address specified by the address specifying means Background generation means for generating a background surface by reading corresponding display attributes and image data from the background storage means, and when the scanning line position enters a background surface having a different display attribute, the background generation means An image control apparatus comprising: a display control unit for instructing switching. 4. The image control apparatus according to claim 3, wherein the display control means instructs a transparent display when the scanning line position is out of the background plane.