JPH0974202A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device on which the potential of a channel region can be fixed without increasing the area of an element region. SOLUTION: A silicon layer 16, which is the element region to be used for a MOSFET, is formed on the buried oxide film 14 on a silicon substrate 10. A channel region 20, a source region 22 and a drain region 24 are formed on the silicon layer 16. The film thickness of the source region 22 and the drain region 24 is relatively thinner than the film thickness of the channel region 20. Silicon oxide films 26 and 28 are formed on the source region 22 of the drain region 24, and the upper surfaces of the silicon oxide films 26 and 28 and the channel region 24 are almost coincided with each other. A substrate electrode layer 30 is formed on the silicon oxide films 26 and 28 and the channel region 24. Said substrate electrode 30 is brought into contact with the channel region 24 only.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MOSFET having an SOI structure and a method of manufacturing the same. An SOI structure CMOS LSI using a thin semiconductor layer has low power consumption, excellent radiation resistance, and is capable of high-speed operation, and is expected as a high-performance LSI in the future.

[0002]

2. Description of the Related Art A conventional semiconductor device having an SOI structure is different from a semiconductor device formed on a bulk semiconductor substrate in that a semiconductor layer in a channel region is kept in a floating state without being fixed, for structural reasons. A floating channel structure is common.

However, the floating channel structure MOSFET has various problems such as a decrease in drain breakdown voltage. For this reason, the MOSFET of the floating channel structure has been limited to applications with a low power supply voltage such as mobile communication LSIs. In order to solve such a problem, an attempt has been made to fix an electric potential by connecting an external electrode to a channel region of a semiconductor layer of an SOI structure MOSFET.

[0004]

SUMMARY OF THE INVENTION However, SOI
Since the electrode cannot be directly provided on the back surface of the semiconductor layer having the structure, there is a problem in that a new region for drawing the channel region to the outside is needed and the area of the element region is increased. An object of the present invention is to provide a semiconductor device capable of fixing the potential of the channel region without increasing the area of the element region, and a manufacturing method thereof.

[0005]

A semiconductor device according to the present invention is a semiconductor device having an insulating layer, a channel region, and a source region and a drain region that are thinner than the channel region. A layer, a gate electrode layer formed in the insulating layer below the channel region, and an insulating film formed on the source region and the drain region of the semiconductor layer and having an upper surface substantially matching the upper surface of the channel region. A substrate electrode layer formed on the channel region of the semiconductor layer and the insulating film and contacting the channel region.

According to the present invention, since the substrate electrode layer is provided immediately above the channel region, the potential of the channel region can be fixed without increasing the area of the element region. The semiconductor device described above preferably further includes an element isolation oxide film surrounding the semiconductor layer. A method of manufacturing a semiconductor device according to the present invention includes a channel region having a relatively low impurity concentration on a surface of a first semiconductor substrate,
A first region which is formed so as to sandwich the channel region and which has a source region and a drain region having a relatively high impurity concentration;
And a second step of forming a first insulating layer in which a gate electrode layer is embedded on the channel region, and the first step.
A third step of laminating a second substrate on the insulating layer of
A fourth step of polishing the first semiconductor substrate from the back surface until the source region and the drain region are exposed; and the source region and the drain region having a relatively high impurity concentration, the impurity concentration being relatively low. A fifth step of selectively etching the channel region; a sixth step of forming a second insulating layer on the channel region, the source region and the drain region; Having a seventh step of polishing until an insulating layer remains on the source and drain regions and exposing the channel region, and an eighth step of forming a substrate electrode layer in contact with the exposed channel region. Is characterized by.

According to the present invention, the source region and the drain region are selectively etched by utilizing the difference in impurity concentration to leave the channel region thick, so that only the channel region is exposed on the surface. It is possible to form the substrate electrode layer that contacts only the channel region without increasing the area of the substrate electrode layer. In the method of manufacturing a semiconductor device described above, the first step further includes the step of forming an element isolation oxide film surrounding the channel region, the source region and the drain region on the surface of the first semiconductor substrate. In the fourth step, it is preferable that the first semiconductor substrate be polished from the back surface until the element isolation oxide film is exposed.

[0008]

A semiconductor device according to an embodiment of the present invention will be described with reference to FIG. The semiconductor device of this embodiment is an SOI structure MOSFET. The supporting silicon substrate 10 has a BPSG layer 12 of about 0.5 to 1.0 μm thick.
And a buried oxide film 14 having a thickness of about 1.0 μm is formed on the BPSG layer 12. M on the buried oxide film 14
A silicon layer 16 which is an element region for OSFET is formed. The silicon layer 16 is separated from the surrounding silicon layer 16 'by an element isolation oxide film 18 having a thickness of about 600 nm.

A channel region 20 having a relatively low impurity concentration of 1 × 10 ¹⁶ cm ⁻³ is formed in the silicon layer 16 which is an element region, and the impurity concentration is 1 × 10 6 on both sides of the channel region 20. ^A source region 22 and a drain region 24, which are relatively high at ²¹ cm ^-3 , are formed. In the silicon layer 16, the source region 22 and the drain region 24
Has a thickness of about 200 nm, and the channel region 20 has a thickness of about 3
00 nm, the source region 22 and the drain region 24 are relatively thin. Silicon oxide films 26 and 28 each having a thickness of about 100 nm are formed on the source region 22 and the drain region 24, respectively.
The upper surfaces of the channel region 24 and the channel region 24 substantially coincide with each other.

On the silicon oxide films 26 and 28 and the channel region 24, about 0.1 μm made of a conductive material such as doped polycrystalline silicon, silicide, or metal.
A thick substrate electrode layer 30 is formed. The substrate electrode layer 30 is in contact only with the channel region 24. The channel region 24 is fixed to the potential of the substrate electrode layer 30.

In the buried oxide film 14 below the channel region 24 of the silicon layer 16, a gate electrode made of a conductive material such as polycrystalline silicon or silicide having a thickness of about 400 nm is provided via a gate oxide film 32 having a thickness of about 8 nm. The layer 34 is formed. As described above, according to the present embodiment, the substrate electrode layer 30 for fixing the substrate potential is provided immediately above the silicon layer 16 which is the element region, and the substrate electrode layer 30 is set to a predetermined potential to thereby form the channel layer. The potential of 24 can be fixed. Therefore, the potential of the channel region 24 can be fixed without increasing the area of the element region, and it is possible to realize a semiconductor device having an SOI structure without inconvenience such as a decrease in drain breakdown voltage.

Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.
First, an element isolation oxide film 42 having a thickness of about 600 nm is formed on the surface of the silicon substrate 40 by the LOCOS method to define the element region. Impurities are added to the element region by, for example, ion implantation to form a source region 44 and a drain region 46 having an impurity concentration of 1 × 10 ²¹ cm ⁻³ . The impurity concentration between the source region 44 and the drain region 46 is 1 × 10.
It becomes a channel region 48 of ¹⁶ cm ^-3 . The depth of the source region 44 and the drain region 46 is about 500 nm, which is deeper than the depth of the isolation oxide film 42 (FIG. 2).
(A)).

Subsequently, about 8n is provided above the channel region 48.
A gate electrode layer 52 made of a conductive material such as polycrystalline silicon or silicide having a thickness of about 400 nm is formed through a gate oxide film 50 having a thickness of m, and a buried oxide film 54 is deposited on the entire surface by a CVD method to a thickness of about 1 μm. (FIG. 2 (a)). Next, the BPSG layer 56 is formed on the buried oxide film 54 by the CVD method.
Is deposited in a thickness of about 1 μm, and the surface is flattened by polishing (FIG. 2B).

Next, a silicon substrate 58 which is a supporting substrate.
Prepare The silicon substrate 40 is turned over and superposed on the upper surface of the silicon substrate 58, and the temperature is about 600 to 800 ° C.
It is heated and pressure-bonded (FIG. 2 (c)). Silicon substrate 40
The BPSG film 56 is thermocompression bonded to the surface of the silicon substrate 58. It is desirable to previously form a thermal oxide film on the surface of the silicon substrate 58 because the strength of thermocompression bonding becomes strong.

Next, the silicon substrate 40 is made to have a thickness of about 10 μm by using a grinder, and then the back surface thereof is polished. The silicon substrate 40 is polished until the element isolation oxide film 42 is exposed (FIG. 3A). As a result, a silicon layer 60 having a thickness of about 300 nm, which is separated from other element regions by the element isolation oxide film 42, is formed on the buried oxide film 54, and the channel region 48, The source region 44 and the drain region 46 are exposed (FIG. 3A).

Next, for example, hydrofluoric acid, nitric acid and acetic acid are added in a ratio of 1:
The silicon layer 60 is formed by using the etching solution mixed at 3: 8.
Are selectively etched. The etching solution selectively etches the source region 44 and the drain region 46 having a high impurity concentration and a low resistance value with respect to the channel layer 48 having a low impurity concentration. When the impurity concentration of the channel region 48 is 1 × 10 ¹⁶ cm ⁻³ and the impurity concentration of the source region 44 and the drain region 46 is 1 × 10 ²¹ cm ⁻³ , the selection ratio is about 200. After etching for about 0.5 minutes, the film thickness of the source region 44 and the drain region 46 is about 2
The thickness of the source region 44 and the drain region 46 is smaller than that of the source region 44 and the drain region 46 (FIG. 3B).

Next, about 0.5 μm is formed on the entire surface by the CVD method.
A thick silicon oxide film 62 is deposited (FIG. 3C). Before depositing the silicon oxide film 62, the silicon layer 6
The surfaces of the channel region 48, the source region 44, and the drain region 46 of 0 may be heat-treated to form a thin thermal oxide film. It is possible to suppress deterioration of interface characteristics. Next, the silicon oxide film 62 is polished until the channel region 48 is exposed (FIG. 4A). At this time, since the source region 44 and the drain region 46 are thinner than the channel region 48, polishing is completed with the silicon oxide film 62 left on the upper surface thereof (FIG. 4A).

Next, polycrystalline silicon to which impurities are added,
A conductive material such as silicide or metal is deposited on the entire surface, and then patterned into a predetermined shape to obtain about 0.1
A substrate electrode layer 64 having a thickness of μm is formed (FIG. 4B). As described above, according to the present embodiment, the source region 44 and the drain region 46 are selectively etched using the difference in impurity concentration to leave the channel region 48 thick, so that only the channel region 48 is left on the surface. Can be exposed. Thus, the substrate electrode layer 64 that contacts only the channel region 48 can be formed. Therefore, a semiconductor device having an SOI structure in which the potential of the channel region 48 is fixed can be easily manufactured without increasing the area of the element region.

The present invention is not limited to the above-described embodiment, but various modifications can be made. For example, it goes without saying that the materials, thicknesses, impurity concentrations, etc. in the above embodiments are merely examples, and are not limited to the configurations in the above embodiments.

[0020]

As described above, according to the present invention, since the substrate electrode layer is provided immediately above the channel region, the potential of the channel region can be fixed without increasing the area of the element region. Further, according to the present invention, since the source region and the drain region are selectively etched by utilizing the difference in impurity concentration to leave the channel region thick, only the channel region is exposed on the surface. The substrate electrode layer that contacts only the channel region can be formed without increasing the area.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process sectional view (1) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a process sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a process sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 12 ... BPSG layer 14 ... Buried oxide film 16, 16 '... Silicon layer 18 ... Element isolation oxide film 20 ... Channel region 22 ... Source region 24 ... Drain region 26, 28 ... Silicon oxide film 30 ... Substrate Electrode layer 32 ... Gate oxide film 34 ... Gate electrode layer 40 ... Silicon substrate 42 ... Element isolation oxide film 44 ... Source region 46 ... Drain region 48 ... Channel region 50 ... Gate oxide film 52 ... Gate electrode layer 54 ... Buried oxidation Film 56 ... BPSG layer 58 ... Silicon substrate 60 ... Silicon layer 62 ... Silicon oxide film 64 ... Substrate electrode layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/78 616S 621

Claims (4)

[Claims] 1. An insulating layer, a semiconductor layer formed on the insulating layer, the semiconductor layer having a channel region, a source region and a drain region having a film thickness smaller than that of the channel region, and the insulating layer below the channel region. A gate electrode layer formed therein; an insulating film formed on the source region and the drain region of the semiconductor layer and having an upper surface substantially matching the upper surface of the channel region; and a channel region of the semiconductor layer and the insulating film. A semiconductor device having a substrate electrode layer formed thereon and contacting the channel region. 2. The semiconductor device according to claim 1, further comprising an element isolation oxide film surrounding the semiconductor layer. 3. A channel region having a relatively low impurity concentration and a source region and a drain region having a relatively high impurity concentration are formed on the surface of the first semiconductor substrate, sandwiching the channel region. A first step, and a first step in which a gate electrode layer is embedded on the channel region
Second step of forming an insulating layer of, a third step of adhering a second substrate on the first insulating layer, and exposing the first semiconductor substrate from the back surface to expose the source region and the drain region. And a fourth step of selectively etching the source and drain regions having a relatively high impurity concentration with respect to the channel region having a relatively low impurity concentration, A sixth step of forming a second insulating layer on the channel region, the source region and the drain region, and the second insulating layer, the insulating layer remains on the source region and the drain region, 7. A method of manufacturing a semiconductor device, comprising: a seventh step of polishing until it is exposed, and an eighth step of forming a substrate electrode layer that contacts the exposed channel region. 4. The method for manufacturing a semiconductor device according to claim 3, wherein in the first step, element isolation for surrounding the channel region, the source region and the drain region on the surface of the first semiconductor substrate is performed. A method of manufacturing a semiconductor device, further comprising the step of forming an oxide film, wherein the fourth step polishes the first semiconductor substrate from the back surface until the oxide film for element isolation is exposed.