JPH0974140A - Compound circuit component - Google Patents
Compound circuit componentInfo
- Publication number
- JPH0974140A JPH0974140A JP25017795A JP25017795A JPH0974140A JP H0974140 A JPH0974140 A JP H0974140A JP 25017795 A JP25017795 A JP 25017795A JP 25017795 A JP25017795 A JP 25017795A JP H0974140 A JPH0974140 A JP H0974140A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- region
- transistor
- emitter
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Wire Bonding (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、プッシュプル増幅回路
装置に好適な複合回路部品に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite circuit component suitable for a push-pull amplifier circuit device.
【０００２】[0002]
【従来の技術】オーディオ増幅回路の出力段のＳＥＰＰ
（Ｓingle ended push pull ）回路の一対のトランジス
タ又は一対のダーリントントランジスタには比較的大き
な電流が流れる。このための出力段のトランジスタは放
熱性の良い金属支持板に固着される。また、出力段トラ
ンジスタのエミッタに抵抗が接続される。また、一対の
出力段トランジスタのベース間には温度補償用ダイオー
ドが接続される。2. Description of the Related Art SEPP of an output stage of an audio amplifier circuit
A relatively large current flows through the pair of transistors or the pair of Darlington transistors in the (single ended push pull) circuit. For this purpose, the output stage transistor is fixed to a metal supporting plate having good heat dissipation. A resistor is connected to the emitter of the output stage transistor. A temperature compensating diode is connected between the bases of the pair of output stage transistors.
【０００３】[0003]
【発明が解決しようとする課題】ところで、エミッタ抵
抗を出力段トランジスタと一体形成することが考えられ
る。しかし、このエミッタ抵抗は比較的小さい抵抗値を
有し且つ大きな電流容量を有するように形成しなければ
ならず、製造に困難を伴った。また、温度変化による特
性変動を小さくすることに困難を伴った。また、出力段
トランジスタとエミッタ抵抗とを含む複合回路素子、又
は更に温度補償用ダイオードを含む複合回路素子を外部
リードにワイヤボンディングによって接続することに困
難を伴った。即ち、複合回路素子に含まれる素子の数が
多くなり、ワイヤボンディングによる接続箇所も多くな
ると、複数のワイヤの相互間の接触を防止するための配
慮が必要になり、ワイヤボンディングが面倒になった。By the way, it is possible to form the emitter resistor integrally with the output stage transistor. However, this emitter resistance must be formed so as to have a relatively small resistance value and a large current capacity, which is difficult to manufacture. Further, it has been difficult to reduce the characteristic variation due to the temperature change. Further, it has been difficult to connect the composite circuit element including the output stage transistor and the emitter resistance or the composite circuit element including the temperature compensation diode to the external lead by wire bonding. That is, when the number of elements included in the composite circuit element increases and the number of connection points by wire bonding increases, it becomes necessary to consider to prevent mutual contact of a plurality of wires, which makes wire bonding troublesome. .
【０００４】そこで、本発明の目的は製造が容易であり
且つ特性が優れている少なくともトランジスタとエミッ
タ抵抗とを含む複合回路部品を提供することにある。Therefore, an object of the present invention is to provide a composite circuit component including at least a transistor and an emitter resistor, which is easy to manufacture and has excellent characteristics.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するため
の本発明は、エミッタ領域とベース領域とコレクタ領域
とを含むシリコン半導体基板と、前記半導体基板の一方
の主面に選択的に形成された絶縁膜と、前記半導体基板
の前記一方の主面側に配置され且つ前記エミッタ領域に
接続されたエミッタ電極と、前記半導体基板の前記一方
の主面側に配置され且つ前記ベース領域に接続されたベ
ース電極と、前記半導体基板の他方の主面側に配置され
且つ前記コレクタ領域に接続されたコレクタ電極と、前
記半導体基板の前記一方の主面の前記絶縁膜の上に配置
され且つその一端部が前記エミッタ電極に接続され且つ
ポリシリコンから成る抵抗膜と、前記抵抗膜の他端部に
接続された抵抗取り出し電極とを備えた複合回路部品に
係わるものである。なお、請求項２に示すように抵抗膜
の上に絶縁性薄膜を設け、抵抗値を絶縁性薄膜の幅に基
づいて決定することが望ましい。また、請求項３に示す
ように絶縁性薄膜のパターンを屈曲部を有するように形
成することが望ましい。また、請求項４に示すようにダ
イオードを形成することができる。また、請求項５に示
すようにトランジスタをダーリントントランジスタにす
ることができる。また、請求項６に示すように放熱支持
板と外部リードと中継基板とを設け、半導体基板上の各
電極を中継基板を介して外部リードに導線で接続するこ
とができる。According to the present invention for achieving the above object, a silicon semiconductor substrate including an emitter region, a base region, and a collector region, and selectively formed on one main surface of the semiconductor substrate. An insulating film, an emitter electrode arranged on the one main surface side of the semiconductor substrate and connected to the emitter region, and an emitter electrode arranged on the one main surface side of the semiconductor substrate and connected to the base region. A base electrode, a collector electrode arranged on the other main surface side of the semiconductor substrate and connected to the collector region, and one end of the collector electrode arranged on the insulating film on the one main surface of the semiconductor substrate. The present invention relates to a composite circuit component including a resistance film whose part is connected to the emitter electrode and is made of polysilicon, and a resistance extraction electrode connected to the other end of the resistance film. It is preferable that an insulating thin film is provided on the resistance film and the resistance value is determined based on the width of the insulating thin film. Further, it is desirable that the pattern of the insulating thin film is formed to have a bent portion as described in claim 3. Further, a diode can be formed as described in claim 4. Further, as described in claim 5, the transistor can be a Darlington transistor. Further, as described in claim 6, a heat dissipation support plate, external leads, and a relay substrate are provided, and each electrode on the semiconductor substrate can be connected to the external lead by a conductor through the relay substrate.
【０００６】[0006]
【発明の作用及び効果】本願の各請求項の発明によれ
ば、エミッタに直列に接続される抵抗をシリコン半導体
基板上の絶縁膜の上に形成し、且つポリシリコンで形成
するので、全体として小型化が達成されるのみでなく、
半導体基板と抵抗膜との熱膨張係数が互いに近い値にな
るので、抵抗膜の熱的に安定性及び信頼性が高くなる。
また、請求項２の発明によればエミッタ抵抗の値がエミ
ッタ電極と抵抗取り出し電極とのギャップ幅に依存しな
いで、絶縁性薄膜の幅に依存して決定され、エミッタ抵
抗の値を正確に得ることが可能になる。また、請求項３
によれば屈曲部の働きで微小抵抗値を小さなスペースで
得ることが可能になる。また、請求項４に従って半導体
基板にダイオードを設けると温度補償を容易に達成する
ことが可能になる。また、請求項５によればダーリント
ントランジスタによって増幅率を容易に高めることがで
きる。また、請求項６によれば半導体基板上の電極と外
部リードとの接続を中継基板の働きによって安定的に行
うことが可能になる。According to the inventions of the claims of the present application, the resistor connected in series to the emitter is formed on the insulating film on the silicon semiconductor substrate and is formed of polysilicon. Not only is miniaturization achieved,
Since the thermal expansion coefficients of the semiconductor substrate and the resistance film are close to each other, the resistance film has high thermal stability and reliability.
Further, according to the invention of claim 2, the value of the emitter resistance is determined not depending on the gap width between the emitter electrode and the resistance extraction electrode but on the width of the insulating thin film, and the value of the emitter resistance is accurately obtained. It will be possible. Claim 3
According to the method, the function of the bent portion makes it possible to obtain a minute resistance value in a small space. Further, when the diode is provided on the semiconductor substrate according to the fourth aspect, temperature compensation can be easily achieved. According to claim 5, the amplification factor can be easily increased by the Darlington transistor. Further, according to the sixth aspect, the connection between the electrodes on the semiconductor substrate and the external leads can be stably performed by the function of the relay substrate.
【０００７】[0007]
【実施例】次に、図１〜図６を参照して本発明の実施例
に係わる複合回路部品を説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a composite circuit component according to an embodiment of the present invention will be described with reference to FIGS.
【０００８】図１は本発明に従う複合回路部品を使用す
るＳＥＰＰ増幅回路を示す。このＳＥＰＰ増幅回路は、
第１及び第２の複合回路部品１、２をプッシュプル接続
することによって構成されている。第１の複合回路部品
１は同一のシリコン半導体基板に形成されており、ダー
リントン接続されたＮＰＮ型の第１及び第２のトランジ
スタＱ1 、Ｑ2 と２つのＰＮ接合ダイオードＤ1 、Ｄ2
と第１の抵抗Ｒ1 とから成る。第２の複合回路部品２も
同一のシリコン半導体基板に形成されており、ダーリン
トン接続されたＰＮＰ型の第３及び第４のトランジスタ
Ｑ3 、Ｑ4 と３つのショットキバリアダイオードＳＤ1
、ＳＤ2 、ＳＤ3 と第２及び第３の抵抗Ｒ2 、Ｒ3 と
から成る。FIG. 1 shows a SEPP amplifier circuit using a composite circuit component according to the present invention. This SEPP amplifier circuit
It is configured by push-pull connecting the first and second composite circuit components 1 and 2. The first composite circuit component 1 is formed on the same silicon semiconductor substrate, and has Darlington-connected NPN first and second transistors Q1 and Q2 and two PN junction diodes D1 and D2.
And a first resistor R1. The second composite circuit component 2 is also formed on the same silicon semiconductor substrate, and has third and fourth PNP type transistors Q3 and Q4 connected in Darlington connection and three Schottky barrier diodes SD1.
, SD2, SD3 and second and third resistors R2, R3.
【０００９】第１及び第２のトランジスタＱ1 、Ｑ2 の
コレクタは共にバイアス電圧源Ｂの正側端子に接続され
ている。第２のトランジスタＱ2 のエミッタは第１のト
ランジスタＱ1 のベースに接続されている。第１のトラ
ンジスタＱ1 のエミッタは第１及び第２の抵抗Ｒ1 、Ｒ
2 を介して第３のトランジスタＱ3 のエミッタに接続さ
れている。第３及び第４のトランジスタＱ3 、Ｑ4 のコ
レクタはバイアス電圧源Ｂのグランド側端子に接続され
ている。第４のトランジスタＱ4 のエミッタは第３のト
ランジスタＱ3 のベースに接続されている。スピーカか
ら成る負荷Ｌの一端はコンデンサＣを介して第１及び第
２の抵抗Ｒ1 、Ｒ2 の接続中点に接続され、他端は第３
のトランジスタＱ3 のコレクタに接続されている。The collectors of the first and second transistors Q1 and Q2 are both connected to the positive terminal of the bias voltage source B. The emitter of the second transistor Q2 is connected to the base of the first transistor Q1. The emitter of the first transistor Q1 has first and second resistors R1 and R1.
It is connected via 2 to the emitter of the third transistor Q3. The collectors of the third and fourth transistors Q3 and Q4 are connected to the ground side terminal of the bias voltage source B. The emitter of the fourth transistor Q4 is connected to the base of the third transistor Q3. One end of a load L composed of a speaker is connected to a connection midpoint between the first and second resistors R1 and R2 via a capacitor C, and the other end is connected to a third end.
Is connected to the collector of the transistor Q3.
【００１０】バイアス電圧の温度補償回路を形成するた
めに第２のトランジスタＱ2 のベースと第４のトランジ
スタＱ4 のベースとの間に第１及び第２のＰＮ接合ダイ
オードＤ1 、Ｄ2 と第１、第２及び第３のショットキバ
リアダイオードＳＤ1 、ＳＤ2 、ＳＤ3 と第３の抵抗Ｒ
3 の直列回路が接続されている。The first and second PN junction diodes D1 and D2 are formed between the base of the second transistor Q2 and the base of the fourth transistor Q4 to form a temperature compensation circuit for the bias voltage. The second and third Schottky barrier diodes SD1, SD2, SD3 and the third resistor R
3 series circuit is connected.
【００１１】プッシュプル増幅回路を駆動するためにバ
イアス電圧源Ｂと第２のトランジスタＱ2 のベースとの
間に第４の抵抗Ｒ4 が接続されている。交流信号を前段
増幅すると共に、バイアス回路を形成するために第５の
トランジスタＱ5 が第４のトランジスタＱ4 のベースと
バイアス電圧源Ｂのグランド側端子との間に第５の抵抗
Ｒ5 を介して接続されている。また、第６の抵抗Ｒ6 の
一端が第１及び第２の抵抗Ｒ1 、Ｒ2 の接続中点に接続
され、この他端が第５のトランジスタＱ5 のベースとの
間に接続されている。また、第５のトランジスタＱ5 の
ベースとバイアス電圧源Ｂのグランド側端子との間に第
７の抵抗Ｒ7 が接続されている。A fourth resistor R4 is connected between the bias voltage source B and the base of the second transistor Q2 for driving the push-pull amplifier circuit. A fifth transistor Q5 is connected between the base of the fourth transistor Q4 and the ground side terminal of the bias voltage source B via a fifth resistor R5 to form a bias circuit while pre-amplifying the AC signal. Has been done. Further, one end of the sixth resistor R6 is connected to the connection midpoint between the first and second resistors R1 and R2, and the other end thereof is connected to the base of the fifth transistor Q5. Further, a seventh resistor R7 is connected between the base of the fifth transistor Q5 and the ground side terminal of the bias voltage source B.
【００１２】図１の回路において第１及び第２のトラン
ジスタＱ1 、Ｑ2 から成る第１のダーリントントランジ
スタと第３及び第４のトランジスタＱ3 、Ｑ4 から成る
第２のダーリントントランジスタは第５のトランジスタ
Ｑ5 のベースの交流信号の正の半波及び負の半波に対応
して交互にオンになる。ＳＥＰＰ回路の動作は周知であ
るので詳しい説明は省略する。In the circuit of FIG. 1, the first Darlington transistor composed of the first and second transistors Q1 and Q2 and the second Darlington transistor composed of the third and fourth transistors Q3 and Q4 are connected to the fifth transistor Q5. The alternating turns on corresponding to the positive and negative half-waves of the base AC signal. Since the operation of the SEPP circuit is well known, detailed description will be omitted.
【００１３】２個のＰＮ接合ダイオードＤ1 、Ｄ2 と３
個のショットキバリアダイオードＳＤ1 、ＳＤ2 、ＳＤ
3 はバイアス電圧を安定化するためのものであり、交流
的には短絡されていると見なせるものである。第１及び
第２のトランジスタＱ1 、Ｑ2 から成る第１のダーリン
トントランジスタ及び第３及び第４のトランジスタＱ3
、Ｑ4 から成る第２のダーリントントランジスタのベ
ース・エミッタ間電圧が例えば温度上昇で低くなると、
温度補償回路のＰＮ接合ダイオードＤ1 、Ｄ2 とショッ
トキバリアダイオードＳＤ1 、ＳＤ2 、ＳＤ3 の順方向
電圧の低下も生じ、アイドリング時即ち交流信号の無い
時のトランジスタのベース電流及びコレクタ電流（バイ
アス電流）の増加を抑制する。なお、トランジスタＱ1
〜Ｑ4 の１個のベース・エミッタ間電圧の温度による変
化分は約−２．０〜−２．５ｍＶ／℃である。従って、
ＰＮ接合ダイオードＤ1 、Ｄ2 及びショットキバリアダ
イオードＳＤ1 〜ＳＤ3 は上述の温度による電圧変化に
相当する温度特性を有するように設定する。Two PN junction diodes D1, D2 and 3
Schottky barrier diodes SD1, SD2, SD
3 is for stabilizing the bias voltage and can be regarded as short-circuited in terms of AC. A first Darlington transistor consisting of first and second transistors Q1 and Q2 and a third and fourth transistor Q3.
, Q4 when the base-emitter voltage of the second Darlington transistor becomes low, for example due to temperature rise,
A decrease in the forward voltage of the PN junction diodes D1 and D2 and the Schottky barrier diodes SD1, SD2 and SD3 of the temperature compensation circuit also occurs, and the base current and collector current (bias current) of the transistor increase during idling, that is, when there is no AC signal. Suppress. The transistor Q1
The change of one base-emitter voltage of Q4 with temperature is about -2.0 to -2.5 mV / ° C. Therefore,
The PN junction diodes D1 and D2 and the Schottky barrier diodes SD1 to SD3 are set so as to have temperature characteristics corresponding to the above-mentioned voltage change with temperature.
【００１４】第１の複合回路部品１は、図２に示すよう
に、複合回路素子３と、金属板から成る放熱支持板４
と、第１、第２、第３及び第４の導体層６、７、８、９
を一方の主面上に有する中継基板５と、第１、第２、第
３、第４及び第５の外部リード１０、１１、１２、１
３，１４と、第１、第２、第３及び第４の導線１５、１
６、１７、１８と、点線で囲んで示す被覆絶縁体１９と
から成る。複合回路素子３の裏面はコレクタ電極であっ
て半田によって支持板４に固着されている。複合回路素
子３の上面には、ベース電極２０、ダイオード取り出し
電極２１、エミッタ電極２２、抵抗取り出し電極２３が
設けられており、これ等が第１〜第４の導線１５〜１８
によってセラミック中継基板５上の第１〜第４の導体層
６〜９及び第１〜第４の外部リード１０〜１３にワイヤ
ボンディング方法によって接続されている。小型の複合
回路素子３の４つの電極２０、２１、２２、２３を外部
リード１０〜１３に導線１５〜１８によって直接に接続
せずに、クランク状パターンの導体層６〜９を中継して
接続しているので、導線１５〜１８は相互に接触するこ
となく安定的に接続されている。なお、導線１５〜１８
はクランク状導体層６〜９の一端と他端の２箇所にボン
ディングされているので、安定性が極めて高くなってお
り、被覆絶縁体１９を金型を使用した流動樹脂の注入で
形成する際に切断すること等の問題が発生しない。As shown in FIG. 2, the first composite circuit component 1 includes a composite circuit element 3 and a heat dissipation support plate 4 made of a metal plate.
And the first, second, third and fourth conductor layers 6, 7, 8, 9
And a first, second, third, fourth and fifth outer leads 10, 11, 12, 1 having a relay substrate 5 having on one main surface thereof.
3, 14 and the first, second, third and fourth conductors 15, 1
6, 17, 18 and a covering insulator 19 surrounded by a dotted line. The back surface of the composite circuit element 3 is a collector electrode and is fixed to the support plate 4 by soldering. A base electrode 20, a diode extraction electrode 21, an emitter electrode 22, and a resistance extraction electrode 23 are provided on the upper surface of the composite circuit element 3, and these are provided as first to fourth conducting wires 15 to 18.
Are connected to the first to fourth conductor layers 6 to 9 and the first to fourth external leads 10 to 13 on the ceramic relay substrate 5 by the wire bonding method. The four electrodes 20, 21, 22, 23 of the small-sized composite circuit element 3 are not directly connected to the external leads 10 to 13 by the lead wires 15 to 18, but are connected by relaying the conductor layers 6 to 9 of the crank pattern. Therefore, the conducting wires 15 to 18 are stably connected without contacting each other. In addition, the lead wires 15-18
Is bonded to the crank-shaped conductor layers 6 to 9 at two positions, one end and the other end, so that the stability is extremely high, and when the covering insulator 19 is formed by pouring a fluid resin using a mold. No problems such as disconnecting.
【００１５】図３、図４及び図５は複合回路素子３を概
略的に示す。この複合回路素子３の上面には前述したベ
ース電極２０、ダイオード取り出し電極２１、エミッタ
電極２２、抵抗取り出し電極２３の他に、ダイオード相
互接続電極２４及びトランジスタ相互接続電極２５が設
けられている。FIG. 3, FIG. 4 and FIG. 5 schematically show the composite circuit element 3. On the upper surface of the composite circuit element 3, a diode interconnection electrode 24 and a transistor interconnection electrode 25 are provided in addition to the base electrode 20, the diode extraction electrode 21, the emitter electrode 22, and the resistance extraction electrode 23 described above.
【００１６】図４は図３のＡ−Ａ断面を示し、図５は図
３のＢ−Ｂ断面及びＣ−Ｃ断面を示す。複合回路素子３
は、同一のシリコン半導体基板２６内にＮ型コレクタ領
域（基体半導体領域）２７ａと、これよりも不純物濃度
の高いＮ＋ 型コレクタ領域２７ｂと、第１のトランジ
スタＱ1 のための第１のＰ型ベース領域２８と、第１の
Ｎ＋ 型エミッタ領域２９と、第２のトランジスタＱ2
のための第２のＰ型ベース領域３０と、第２のＮ型エミ
ッタ領域３１と、第１及び第２のダイオードＤ1 、Ｄ2
のための第１及び第２のＰ型半導体領域３２、３３と、
Ｎ型半導体領域３４、３５と、Ｎ＋ 型ガードリング領
域３６と、ベースのワイヤボンディング対応Ｐ型半導体
領域３７とを有する。各Ｐ型ベース領域２８、３０、ダ
イオード用Ｐ型半導体領域３２、３３及びベースのワイ
ヤボンディング対応Ｐ型領域３７は基板２６の表面側を
除いてＮ型コレクタ領域２７ａにそれぞれ隣接してい
る。各Ｎ型エミッタ領域２９、３１及びダイオード用Ｎ
型半導体領域３４、３５は基板の表面側をのぞいてＰ型
ベース領域２８、３０及びダイオード用Ｐ型半導体領域
３２、３３にそれぞれ隣接している。FIG. 4 shows an AA cross section of FIG. 3, and FIG. 5 shows a BB cross section and a CC cross section of FIG. Composite circuit element 3
Is an N type collector region (base semiconductor region) 27a in the same silicon semiconductor substrate 26, an N + type collector region 27b having an impurity concentration higher than that, and a first P type base for the first transistor Q1. Region 28, first N + type emitter region 29, and second transistor Q2
A second P-type base region 30, a second N-type emitter region 31, and first and second diodes D1 and D2
First and second P-type semiconductor regions 32, 33 for
It has N-type semiconductor regions 34 and 35, an N + type guard ring region 36, and a P-type semiconductor region 37 corresponding to the base wire bonding. The P-type base regions 28 and 30, the diode P-type semiconductor regions 32 and 33, and the base wire-bonding P-type region 37 are adjacent to the N-type collector region 27 a except for the front surface side of the substrate 26. Each N-type emitter region 29, 31 and N for diode
The type semiconductor regions 34 and 35 are adjacent to the P-type base regions 28 and 30 and the diode P-type semiconductor regions 32 and 33, respectively, except for the surface side of the substrate.
【００１７】基板２６の表面にはＳｉＯ2 （二酸化シリ
コン）から成る絶縁膜３８が設けられ、図４及び図５の
右端近傍に示すように絶縁膜３８の上にポリシリコン
（多結晶シリコン）から成る抵抗膜３９が帯状に形成さ
れている。また、抵抗膜３９の上に帯状にリンドープド
シリケートガラスから成る絶縁性薄膜４０が形成されて
いる。また、抵抗膜３９を形成した領域以外の絶縁膜３
８の上にも絶縁性薄膜４０が形成されている。絶縁膜３
８と絶縁性薄膜４０とから成る二重絶縁層には複数個の
開口が形成され、この開口を介して半導体領域に電極が
接続されている。即ち、第１のＮ＋ 型エミッタ領域２
９にはエミッタ電極２２が接続されている。第１のＰ型
ベース領域２８と第２のＮ＋ 型エミッタ領域３１は相
互接続電極２５によって接続されている。なお、相互接
続電極２５は第１のトランジスタＱ1 のベース電極及び
第２のトランジスタＱ2 のエミッタ電極としても機能し
ている。第２のＰ型ベース領域３０にはベース電極２０
が接続されている。このベース電極２０はボンディング
パッド部を得るために図４に示すＰ型半導体領域３７の
上に延在し且つ第１のダイオードＤ1 のためのＰ型半導
体領域３２に接続されている。従って、ベース電極２０
はダイオードＤ1 のアノード電極としても機能してい
る。第１のダイオード用Ｎ＋ 型半導体領域３４と第２
のダイオード用Ｐ型半導体領域３３は相互接続電極２４
によって接続されている。なお、相互接続電極２４は第
１のダイオードＤ1 のカソード電極及び第２のダイオー
ドＤ2 のアノード電極としても機能している。第２のダ
イオード用Ｎ＋ 型半導体領域３５にはダイオード取り
出し電極即ちカソード電極２１が接続されている。An insulating film 38 made of SiO 2 (silicon dioxide) is provided on the surface of the substrate 26, and polysilicon (polycrystalline silicon) is formed on the insulating film 38 as shown in the vicinity of the right end of FIGS. 4 and 5. The resistance film 39 is formed in a strip shape. In addition, an insulating thin film 40 made of phosphorus-doped silicate glass is formed in a strip shape on the resistance film 39. In addition, the insulating film 3 other than the region where the resistance film 39 is formed
An insulating thin film 40 is also formed on the surface 8. Insulating film 3
8 and the insulating thin film 40 have a plurality of openings formed therein, and electrodes are connected to the semiconductor region through the openings. That is, the first N + type emitter region 2
An emitter electrode 22 is connected to 9. The first P-type base region 28 and the second N + -type emitter region 31 are connected by the interconnection electrode 25. The interconnection electrode 25 also functions as the base electrode of the first transistor Q1 and the emitter electrode of the second transistor Q2. The base electrode 20 is provided in the second P-type base region 30.
Is connected. The base electrode 20 extends over the P-type semiconductor region 37 shown in FIG. 4 to obtain the bonding pad portion and is connected to the P-type semiconductor region 32 for the first diode D1. Therefore, the base electrode 20
Also functions as the anode electrode of the diode D1. The first diode N + type semiconductor region 34 and the second
The P-type semiconductor region 33 for a diode of the interconnect electrode 24
Connected by The interconnection electrode 24 also functions as the cathode electrode of the first diode D1 and the anode electrode of the second diode D2. A diode extraction electrode, that is, a cathode electrode 21 is connected to the second diode N + type semiconductor region 35.
【００１８】第１のトランジスタＱ1 のエミッタ電極２
２は帯状抵抗膜３９の幅方向の一端部の上に延在し、更
に絶縁性薄膜４０の上に延在し、一方の抵抗端子として
の機能も有している。抵抗取り出し電極２３は抵抗膜３
９の幅方向の他端部の上に形成されていると共に絶縁性
薄膜４０の上にも延在している。エミッタ電極２２と抵
抗取り出し電極２３との間はギャップによって分離され
ているが、これ等の間の抵抗値はギャップに依存しない
で、帯状の絶縁性薄膜４０の幅に依存して決定されてい
る。絶縁性薄膜４０はＡｌ（アルミニウム）金属層から
成るエミッタ電極２２及び抵抗取り出し電極２３よりも
薄く形成されている。従って、絶縁性薄膜４０のエッチ
ングによるパターンの寸法誤差は電極２２、２３のそれ
よりも小さい。従って、電極２２、２３間の抵抗値の精
度を高めることができる。また、電極２２、２３の厚さ
が抵抗値の精度に無関係になるので、電極２２、２３の
厚さを厚くしてこの電流容量を高めることができる。Emitter electrode 2 of the first transistor Q1
2 extends on one end of the strip resistance film 39 in the width direction and further extends on the insulating thin film 40, and also has a function as one resistance terminal. The resistance extraction electrode 23 is the resistance film 3
It is formed on the other end portion in the width direction of 9 and also extends on the insulating thin film 40. The emitter electrode 22 and the resistance extraction electrode 23 are separated by a gap, but the resistance value between them is determined not by the gap but by the width of the strip-shaped insulating thin film 40. . The insulating thin film 40 is formed thinner than the emitter electrode 22 and the resistance extraction electrode 23 which are made of an Al (aluminum) metal layer. Therefore, the dimensional error of the pattern due to the etching of the insulating thin film 40 is smaller than that of the electrodes 22 and 23. Therefore, the accuracy of the resistance value between the electrodes 22 and 23 can be improved. Further, since the thickness of the electrodes 22 and 23 has nothing to do with the accuracy of the resistance value, it is possible to increase the current capacity by increasing the thickness of the electrodes 22 and 23.
【００１９】ガードリングとしてのＮ＋ 型半導体領域
３６の上には金属電極４１が設けられている。この金属
電極４１は等電位リングとして働く。A metal electrode 41 is provided on the N + type semiconductor region 36 as a guard ring. This metal electrode 41 acts as an equipotential ring.
【００２０】抵抗膜３８は図６に示すように帯状に形成
され、絶縁性薄膜４０は凹部即ち屈曲部４０ａを有する
パターンに形成されている。屈曲部４０ａを設けると抵
抗膜３９の幅方向の一端部と他端部の絶縁性薄膜４０を
介した対向面の長さが長くなり、抵抗値を小さくするこ
とができる。The resistance film 38 is formed in a band shape as shown in FIG. 6, and the insulating thin film 40 is formed in a pattern having a concave portion, that is, a bent portion 40a. When the bent portion 40a is provided, the length of the opposing surface of the resistance film 39 at one end and the other end in the width direction with the insulating thin film 40 interposed therebetween is increased, and the resistance value can be reduced.
【００２１】上述から明らかなように、本実施例によれ
ば抵抗Ｒ1 をシリコン半導体基板２６上のポリシリコン
から成る抵抗膜３９によって得るので、信頼性が高く且
つ特性の優れたエミッタ抵抗Ｒ1 を得ることができる。
即ち、ポリシリコンは基板２６のシリコンに近い熱膨張
係数を有するので、安定性及び信頼性の高い抵抗Ｒ1を
提供することができる。As is apparent from the above, according to the present embodiment, the resistance R1 is obtained by the resistance film 39 made of polysilicon on the silicon semiconductor substrate 26, so that the emitter resistance R1 having high reliability and excellent characteristics can be obtained. be able to.
That is, since polysilicon has a coefficient of thermal expansion close to that of the silicon of the substrate 26, it is possible to provide a stable and reliable resistance R1.
【００２２】なお、第２の複合回路部品２は、ショット
キバリアダイオードＳＤ1 、ＳＤ2、ＳＤ3 を含む構成
になっている。即ち、ＰＮ接合ダイオードＤ1 、Ｄ2 を
含む第１の複合回路部品１とショットキバリアダイオー
ドＳＤ1 、ＳＤ2 、ＳＤ3 を含む第２の複合回路部品２
との組合せによってＳＥＰＰ回路を形成している。図１
のＢ級プッシュプル回路では、ひずみをなくすためにベ
ース・エミッタ間にあらかじめカットオフ点までのバイ
アスを加えておく必要がある。このためには、Ｄ1 、Ｄ
2 、ＳＤ1 、ＳＤ2 、ＳＤ3 の順方向電圧及び抵抗Ｒ3
での電圧降下の和Ｖ1 をＱ1 〜Ｑ4 のベース・エミッタ
間順方向電圧の和Ｖ2 とほぼ等しくする必要がある。ま
た、温度上昇によるトランジスタの電流増加を抑制する
ためには、温度上昇によるトランジスタＱ1 〜Ｑ4 の順
方向電圧降下の総和がＤ1 、Ｄ2 、ＳＤ1 、ＳＤ2 、Ｓ
Ｄ3 の温度上昇による順方向電圧降下の総和よりも小さ
いことが望まれる。このことを満足するために、全ての
温度補償ダイオードをＰＮ接合ダイオードで構成する
と、温度補償ダイオードに流れる電流はトランジスタＱ
1 〜Ｑ2 のベース・エミッタ間電流の約ｈFE倍であるか
ら、上記の様にＶ1 とＶ2 とをほぼ等しくするためには
温度補償ダイオードの面積をトランジスタのベース・エ
ミッタ間ＰＮ接合面積の約ｈFE倍としなければならず現
実的ではない。ところが、本実施例では、ＰＮ接合ダイ
オードによる順方向電圧の増大をショットキバリアダイ
オードで制限しつつトランジスタの温度上昇による電流
増加も抑制している。即ち、ＰＮ接合ダイオードの順方
向電圧ＶF は約０．６Ｖであり、ショットキバリアダイ
オードの順方向電圧ＶF は約０．３Ｖである。従って、
ショットキバリアダイオードの順方向電流を増大させて
もＰＮ接合ダイオードに比べてショットキバリアダイオ
−ドの順方向電圧を低く保つことができる。このため、
ショットキバリアダイオード１個あたりが占めるチップ
上の面積は、ＰＮ接合のそれに比べて十分小さい。本実
施例では、第１の複合回路部品１中のＰＮ接合ダイオー
ドの面積は第２の複合回路部品２中のショットキバリア
ダイオードが占める面積と同程度としている。このた
め、ＰＮ接合ダイオード２つ分の順方向電圧はトランジ
スタＱ1 、Ｑ2 のベース・エミッタ間順方向電圧和より
も大きくなっている。しかしながら、第２の複合回路部
品２中のショットキバリアダイオードＳＤ1〜ＳＤ3 の
順方向電圧はＰＮ接合ダイオードの順方向電圧よりも小
さいので、ショットキバリアダイオードを３個入れて温
度補償機能を十分に発揮させてトータルの温度補償ダイ
オードＤ1 、Ｄ2 、ＳＢＤ1 、ＳＢＤ2 、ＳＢＤ3 の順
方向電圧和Ｖ1 をＱ1 〜Ｑ4 のベース・エミッタ間順方
向電圧和Ｖ2 とほぼ一致させている。結果として第１と
第２の複合回路部品１、２を小さいサイズでほぼ同一の
大きさとして歪み防止と温度補償が良好に達成でき且つ
放熱性のバランスを良くし且つコスト低減を図れる。The second composite circuit component 2 has a structure including Schottky barrier diodes SD1, SD2 and SD3. That is, the first composite circuit component 1 including the PN junction diodes D1 and D2 and the second composite circuit component 2 including the Schottky barrier diodes SD1, SD2 and SD3.
To form a SEPP circuit. FIG.
In the class B push-pull circuit, the bias up to the cutoff point must be applied in advance between the base and emitter to eliminate distortion. To do this, D1, D
2, SD1, SD2, SD3 forward voltage and resistance R3
It is necessary to make the sum V1 of the voltage drops at V2 substantially equal to the sum V2 of the base-emitter forward voltage of Q1 to Q4. Further, in order to suppress the increase in current of the transistor due to the temperature rise, the sum of the forward voltage drops of the transistors Q1 to Q4 due to the temperature rise is D1, D2, SD1, SD2, S
It is desired to be smaller than the total forward voltage drop due to the temperature rise of D3. In order to satisfy this, if all the temperature compensating diodes are composed of PN junction diodes, the current flowing through the temperature compensating diodes is the transistor Q.
Since it is about h FE times the base-emitter current of 1 to Q2, in order to make V1 and V2 almost equal to each other as described above, the area of the temperature compensating diode is about the PN junction area of the base-emitter of the transistor. h It must be FE times, which is not realistic. However, in this embodiment, the Schottky barrier diode limits the increase in the forward voltage due to the PN junction diode, while suppressing the increase in current due to the temperature rise of the transistor. That is, the forward voltage VF of the PN junction diode is about 0.6V, and the forward voltage VF of the Schottky barrier diode is about 0.3V. Therefore,
Even if the forward current of the Schottky barrier diode is increased, the forward voltage of the Schottky barrier diode can be kept lower than that of the PN junction diode. For this reason,
The area on the chip occupied by each Schottky barrier diode is sufficiently smaller than that of the PN junction. In this embodiment, the area of the PN junction diode in the first composite circuit component 1 is about the same as the area occupied by the Schottky barrier diode in the second composite circuit component 2. Therefore, the forward voltage for two PN junction diodes is larger than the sum of the forward voltage between the base and emitter of the transistors Q1 and Q2. However, the forward voltage of the Schottky barrier diodes SD1 to SD3 in the second composite circuit component 2 is smaller than the forward voltage of the PN junction diode, so that three Schottky barrier diodes should be inserted to fully exert the temperature compensation function. As a result, the total forward voltage sum V1 of the temperature compensating diodes D1, D2, SBD1, SBD2 and SBD3 is made substantially equal to the total base-emitter forward voltage sum V2 of Q1 to Q4. As a result, the first and second composite circuit components 1 and 2 can be made small in size and substantially the same size, distortion prevention and temperature compensation can be satisfactorily achieved, the heat dissipation property can be well balanced, and the cost can be reduced.
【００２３】[0023]
【変形例】本発明は上述の実施例に限定されるものでな
く、例えば次の変形が可能なものである。 （１） トランジスタＱ2 、Ｑ4 を省いた構成とするこ
とができる。 （２） 電流容量を大きくするために導線１５〜１８を
それぞれ複数本とすることができる。[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The transistors Q2 and Q4 can be omitted. (2) A plurality of conductors 15 to 18 can be used to increase the current capacity.
【図１】実施例に係わるＳＥＰＰ回路装置を示す回路図
である。FIG. 1 is a circuit diagram showing a SEPP circuit device according to an embodiment.
【図２】図１の回路装置における第１の複合回路部品を
示す平面図である。FIG. 2 is a plan view showing a first composite circuit component in the circuit device of FIG.
【図３】図２の複合回路素子を示す平面図である。FIG. 3 is a plan view showing the composite circuit element of FIG.
【図４】図２のＡ−Ａ断面によって複合回路素子を示す
図である。FIG. 4 is a diagram showing a composite circuit element taken along the line AA in FIG.
【図５】図２のＢ−Ｂ断面、Ｃ−Ｃ断面によって複合回
路素子を示す図である。5 is a diagram showing a composite circuit element by a BB cross section and a CC cross section of FIG. 2;
【図６】図４及び図５の抵抗膜及び絶縁性薄膜を示す平
面図である。FIG. 6 is a plan view showing the resistance film and the insulating thin film of FIGS. 4 and 5;
１、２ 第１及び第２の複合回路部品 Ｄ1 、Ｄ2 ＰＮ接合ダイオード Ｑ1 、Ｑ2 トランジスタ ３９ 抵抗膜 ４０ 絶縁性薄膜 1, 2 First and second composite circuit components D1, D2 PN junction diode Q1, Q2 transistor 39 resistance film 40 insulating thin film
Claims (6)
域とを含むシリコン半導体基板と、 前記半導体基板の一方の主面に選択的に形成された絶縁
膜と、 前記半導体基板の前記一方の主面側に配置され且つ前記
エミッタ領域に接続されたエミッタ電極と、 前記半導体基板の前記一方の主面側に配置され且つ前記
ベース領域に接続されたベース電極と、 前記半導体基板の他方の主面側に配置され且つ前記コレ
クタ領域に接続されたコレクタ電極と、 前記半導体基板の前記一方の主面の前記絶縁膜の上に配
置され且つその一端部が前記エミッタ電極に接続され且
つポリシリコンから成る抵抗膜と、 前記抵抗膜の他端部に接続された抵抗取り出し電極とを
備えた複合回路部品。1. A silicon semiconductor substrate including an emitter region, a base region, and a collector region, an insulating film selectively formed on one main surface of the semiconductor substrate, and one main surface side of the semiconductor substrate. And an emitter electrode connected to the emitter region, a base electrode disposed on the one main surface side of the semiconductor substrate and connected to the base region, and another main surface side of the semiconductor substrate. A collector electrode arranged and connected to the collector region, and a resistance film made of polysilicon and arranged on the insulating film on the one main surface of the semiconductor substrate and having one end connected to the emitter electrode. And a resistance extraction electrode connected to the other end of the resistance film.
成され、 前記絶縁性薄膜は前記エミッタ電極及び前記抵抗取り出
し電極よりも薄く形成され、 前記エミッタ電極は前記絶縁性薄膜の上に延在し、 前記抵抗取り出し電極は前記絶縁性薄膜の上に延在し、 前記エミッタ電極と前記抵抗取り出し電極との間の抵抗
値が前記絶縁性薄膜の幅に基づいて決定されていること
を特徴とする請求項１記載の複合回路部品。2. A strip-shaped insulating thin film is formed on the resistance film, the insulating thin film is formed thinner than the emitter electrode and the resistance extraction electrode, and the emitter electrode is formed on the insulating thin film. Extending, the resistance extraction electrode extends on the insulating thin film, and the resistance value between the emitter electrode and the resistance extraction electrode is determined based on the width of the insulating thin film. The composite circuit component according to claim 1, which is characterized in that.
部を有するパターンに形成されていることを特徴とする
請求項１又は２記載の複合回路部品。3. The composite circuit component according to claim 1, wherein the insulating thin film is formed in a pattern having a bent portion on the resistance film.
ための第１及び第２のダイオード用半導体領域を含み、
前記第１のダイオード用半導体領域は前記ベース電極に
接続され、前記第２のダイオード用半導体領域にダイオ
ード取り出し電極が接続されていることを特徴とする請
求項１又は２又は３記載の複合回路部品。4. The semiconductor substrate includes first and second diode semiconductor regions for forming a diode,
4. The composite circuit component according to claim 1, wherein the first diode semiconductor region is connected to the base electrode, and the second diode semiconductor region is connected to a diode extraction electrode. .
記ベース領域と前記コレクタ領域の代わりにダーリント
ントランジスタを形成する前段トランジスタと後段トラ
ンジスタを含み、前記後段トランジスタは後段トランジ
スタ用エミッタ領域と後段トランジスタ用ベース領域と
後段トランジスタ用コレクタ領域を有し、前記前段トラ
ンジスタは前段トランジスタ用エミッタ領域と前段トラ
ンジスタ用ベース領域と前段トランジスタ用コレクタ領
域を有し、 前記前段トランジスタ用エミッタ領域は前記後段トラン
ジスタ用ベース領域に接続され、 前記エミッタ電極は前記後段トランジスタ用エミッタ領
域に接続され、 前記ベース電極は前記前段トランジスタ用ベース領域に
接続され、 前記コレクタ電極は前記前段トランジスタ用コレクタ領
域及び前記後段トランジスタ用コレクタ領域に接続され
ていることを特徴とする請求項１又は２又は３又は４記
載の複合回路部品。5. The semiconductor substrate includes a front stage transistor and a rear stage transistor forming a Darlington transistor instead of the emitter region, the base region and the collector region, and the rear stage transistor includes a rear stage transistor emitter region and a rear stage transistor base. And a collector region for a rear transistor, the front transistor has a front transistor emitter region, a front transistor base region, and a front transistor collector region, and the front transistor emitter region is a rear transistor base region. Connected, the emitter electrode is connected to the emitter region for the rear transistor, the base electrode is connected to the base region for the front transistor, and the collector electrode is the collector region for the front transistor. And composite circuit component according to claim 1 or 2 or 3 or 4, wherein it is connected to the rear stage transistor collector region.
第２、第３及び第４の中継接続導体層を有する絶縁基板
と、第１、第２、第３、第４及び第５の外部リードとを
有し、 前記半導体基板は前記支持板の上に配置され、 前記半導体基板の前記他方の主面の前記コレクタ電極は
前記支持板に接続され、 前記絶縁基板は前記支持板の上に固着され且つ平面的に
見て前記半導体基板と前記第１〜第５の外部リードとの
間に配置され、 前記ベース電極と前記第１の中継接続導体層と前記第１
の外部リードとを接続する第１の導線と、前記ダイオー
ド取り出し電極と前記第２の中継接続導体層と前記第２
の外部リードを接続する第２の導線と、前記エミッタ電
極と前記第３の中継接続導体層と前記第３の外部リード
とを接続する第３の導線と、前記抵抗取り出し電極と前
記第４の中継接続導体層と前記第４の外部リードとを接
続する第４の導線とを有し、 前記第５の外部リードは前記支持板に接続されているこ
とを特徴とする請求項４又は５記載の複合回路部品。6. A support plate having heat dissipation properties, a first plate,
The semiconductor substrate has an insulating substrate having second, third and fourth relay connection conductor layers and first, second, third, fourth and fifth external leads, and the semiconductor substrate is on the support plate. And the collector electrode on the other main surface of the semiconductor substrate is connected to the support plate, the insulating substrate is fixed on the support plate, and the semiconductor substrate and the first substrate are planarly viewed. To the fifth external lead, the base electrode, the first relay connection conductor layer, and the first
First lead wire for connecting to an external lead of the diode, the diode lead electrode, the second relay connection conductor layer, and the second lead wire.
Second lead wire for connecting the external lead, the third lead wire for connecting the emitter electrode, the third relay connection conductor layer, and the third outer lead, the resistance extraction electrode, and the fourth lead wire. 6. A relay connection conductor layer and a fourth conductor wire connecting the fourth outer lead, the fifth outer lead being connected to the support plate. Composite circuit components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25017795A JP3483174B2 (en) | 1995-09-04 | 1995-09-04 | Composite circuit components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25017795A JP3483174B2 (en) | 1995-09-04 | 1995-09-04 | Composite circuit components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0974140A true JPH0974140A (en) | 1997-03-18 |
| JP3483174B2 JP3483174B2 (en) | 2004-01-06 |
Family
ID=17203970
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25017795A Expired - Fee Related JP3483174B2 (en) | 1995-09-04 | 1995-09-04 | Composite circuit components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3483174B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5116899A (en) * | 1986-12-15 | 1992-05-26 | Chisso Corporation | Resin composition for electric insulation materials for vehicles |
| US6852580B2 (en) | 1999-11-19 | 2005-02-08 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating semiconductor device |
| JP2009207060A (en) * | 2008-02-29 | 2009-09-10 | Mitsubishi Electric Corp | High-frequency semiconductor amplifier |
-
1995
- 1995-09-04 JP JP25017795A patent/JP3483174B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5116899A (en) * | 1986-12-15 | 1992-05-26 | Chisso Corporation | Resin composition for electric insulation materials for vehicles |
| US6852580B2 (en) | 1999-11-19 | 2005-02-08 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating semiconductor device |
| JP2009207060A (en) * | 2008-02-29 | 2009-09-10 | Mitsubishi Electric Corp | High-frequency semiconductor amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3483174B2 (en) | 2004-01-06 |
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