JPH0973747A - Disk contact detection circuit for mr head - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely detect a disturbance signal showing disk contact of a head by comparing an MR head read-out signal with a threshold value and limiting its pulse width to a prescribed value. SOLUTION: An inversion signal RDY in a noise data signal when an MR head is in contact with the disk is compared with the threshold value Vth by a comparator 3 in a disturbance signal detection circuit 88, and a high part is outputted as a digital signal (e) of logic H. A pulse limit circuit 5 is started at the rise of the signal (e), and the signal (f) is outputted to a D-FF 6 as it is when the pulse width of the signal (e) is narrow, and is outputted to the D-FF 6 after limiting to a width X1 when the pulse width is the prescribed width X1 or above. Then, at the part where the pulse width of the signal (e) is the prescribed width X1 or above an FF 6 output waveform (g) becomes L at the rise of the signal (f). On the other hand, the rise of the signal (f) is delayed in a phase from the fall of the signal (e), and the signal (e) becomes the L, and the FF6 output isn't changed, and the output (g) becomes the L in the part subtracting the circuit 5 output signal pulse width X1 from the disturbance signal pulse width of the head, and since all others become H, the disturbance signal of the disk contact is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hard disk drive, and in particular, it is mainly used in a read amplifier for driving a head (hereinafter referred to as an MR head) whose head is composed of a magnetoresistive effect element and has a simple circuit structure. MR
The present invention relates to a disk contact detection circuit of an MR head that detects that the head has contacted the disk.

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing a general block configuration of a hard disk drive. In FIG. 7, the data recorded on the disk 58 is read by the MR head 62. The signal read by the MR head 62 passes through a read / write (R / W) amplifier 56 and a read channel 54, a hard disk controller (HD
C) It is sent to the personal computer 50 via 52 and processed.
On the other hand, the position control of the MR head 62 is performed by the read channel 5
4 through the CPU 72, the VCM driver 68, and the VCM motor 66. The rotation control of the disk 58 is performed from the read channel 54 via the CPU 72, the SPM driver 70, and the SPM motor 64. The recording of data on the disk 58 is performed by the HDC 52, the read channel 54 and the R / R based on an instruction from the personal computer 50.
A data signal is sent to the write head 60 via the W amplifier 56, and the write head 60 writes the data to the disk 58.

FIG. 8 shows the read / write (R) shown in FIG.
/ W) is a diagram showing a conventional example of an amplifier 56. In FIG. 8, the signal read from the disk 58 by the MR head 62 is amplified by the first amplifier 80 and the second amplifier and output to the output terminal 200.

On the other hand, when the signal amplified by the first amplifier 80 includes a disturbance due to the MR head 62, in order to detect the disturbance, the output of the first amplifier 80 is compared with a threshold value V _th to obtain a threshold value. A disturbance signal whose amplitude is larger than V _th is extracted. The extracted disturbance signal is (1) R
It is used to perform processing such as cutting the output of the / W amplifier 56, (2) outputting a signal to the outside of the IC, and reading the reproduced signal again on the hard disk device side.

Normally, the MR head 62 is used in a state of floating above the disk 58 surface of a hard disk drive. FIG. 9 is a diagram showing signals of respective parts of the conventional R / W amplifier 56. In a normal state, the MR head 6
The signal read from No. 2 has the same small amplitude waveform as shown in FIG. MR head 6
When 2 comes into contact with the surface of the disk 58, the MR head 62 instantly becomes hot and the resistance value of the MR head 62 increases.
In most cases, the contact is instantaneous and the MR head 62 is immediately separated from the surface of the disk 58. However, the heat generated by the MR head 62 is slowly radiated, and as a result, a disturbance having a long cycle as shown in FIG. 9B is generated. A signal is generated. The disturbance signal (b) and the data signal read from the disk 58 shown in FIG. 9A are superimposed, and the combined data signal shown in FIG. 9C is output from the MR head 62. ,
It is input to the R / W amplifier 56. The phenomenon in which the disturbance signal generated due to the high heat of the MR head 62 and the increase in its resistance value is superimposed on the data signal is called thermal asperity.

[0006]

However, when noise is added to the reproduced signal in addition to the disturbance signal as shown in FIG. 9 (u), only the disturbance signal as shown in FIG. 9 (x) is generated. Not even noise was detected. For this reason, the noise detection signal is erroneously used as the disturbance detection signal,
There has been a problem that reading of the reproduction signal is cut by noise. 9 (u), (v),
In (w), the data signal waveform is actually superimposed as in (t), but the data signal waveform is omitted for simplification of the drawing.

The present invention has been made in view of the above points, and an object thereof is to obtain a disk contact detection circuit of an MR head which has a simple circuit configuration and which appropriately detects a disturbance signal without the influence of noise. It is what

[0008]

The present invention has been made to solve the above problems. Specifically, the invention described in claim 1 is a signal read by an MR head. and a comparator for comparing the threshold value V _th, of the pulses included in the output signal of the comparator, a pulse width limiting circuit for limiting the width of the pulse having a predetermined pulse width x ₁ or more pulse width x to x ₁ And a D flip-flop circuit that inputs the output signal of the comparator to the D terminal and the R terminal, inputs the output of the pulse width limiting circuit to the T terminal, and obtains the output from the inverting output terminal (QC).

Further, the invention according to claim 2 is a comparator for comparing a signal read by the MR head with a threshold value V _th, and a first predetermined value among pulses included in an output signal of the comparator. limit the first pulse width limiting circuit for limiting the width of the pulse in x ₁ having a pulse width x ₁ or more pulse width, the output signal of the comparator is input to the D terminal and the R terminal, the first pulse width The output of the circuit is input to the T terminal, and the inverted output terminal (Q
C) a D flip-flop circuit, a second pulse width limiting circuit for inputting an output signal of the D flip-flop circuit and generating a pulse having a _second predetermined pulse width x 2, It is composed of a NAND gate which receives the output signal of the pulse width limiting circuit and the output signal of the D flip-flop circuit and obtains a signal having a pulse width close to the disturbance signal of the MR head.

Furthermore, the invention according to claim 3 is configured such that the first predetermined pulse width x ₁ and the second predetermined pulse width x ₂ are equal.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a diagram showing a circuit configuration for detecting a disk contact of an MR head according to an embodiment of the present invention. In FIG. 1, 100 is an MR head 62.
Is an input terminal of the R / W amplifier 56 to which a data signal read from the disk 58 is input. When the MR head 62 momentarily contacts the disk 58, a data signal accompanied by noise shown in FIG. 4A is input to the input terminal 100. In addition, (a) -of FIG.
In FIG. 9D, the data signal waveform is actually superimposed as in FIG. 9T, but the data signal waveform is omitted for simplification of the drawing. 80 is the first amplifier,
Reference numeral 82 is a second amplifier. Reference numeral 83 is a disturbance signal suppression circuit. Reference numeral 200 is an output terminal for a data signal. 88 is
A disturbance signal detection circuit for detecting the disk contact of the MR head according to the present invention, and 400 is an output terminal for outputting the disturbance signal detected by the disturbance signal detection circuit 88.

Next, FIG. 1 will be described. Input terminal 1
Assuming that a disturbance signal and a data signal accompanied by noise as shown in FIG. 4A are input to 00, the outputs of the first amplifier 80 have RDX signals (((b in FIG. 4B )) And the RDY signal (((c) in FIG. 4) are output. The second amplifier 82 amplifies the RDX signal and then suppresses the disturbance signal and the noise signal by the disturbance signal suppressing circuit 83 to the output terminal 200. On the other hand, the disturbance signal detection circuit 88 compares the RDY signal with the threshold value V _th , extracts the portion of the disturbance signal whose level is higher than the threshold value V _th, and outputs it to the output terminal 400. Is used to perform processing such as (1) cutting the output of the R / W amplifier 56, (2) outputting a signal to the outside of the IC and reading the data reproduction signal again on the hard disk device side, as described above. It

Next, the structure of the disturbance signal detection circuit 88 will be described. FIG. 2 is a diagram showing an embodiment of the disturbance signal detection circuit 88. In FIG. 2, 3 is a comparator (COM
P), 5 is a pulse width limiting circuit, and 6 is a D flip-flop circuit.

Next, the operation of the disturbance signal detection circuit 88 will be described. The RDY signal which is the inverted signal obtained as the output of the amplifier 80 is applied to the comparator 3 of the disturbance signal detection circuit 88. As shown in (c) of FIG. 4, the RDY signal is compared with the threshold value V _th, and only a portion having a higher level than the threshold value V _th is output as a digital signal whose logic is “H” ((of FIG. 4). e)). In this case, the pulse width of the disturbance signal of the MR head is x and the pulse width of the noise signal is y.
Becomes The pulse width limiting circuit 5 is activated at the rising edge of the output signal of the comparator 3 ((e) in FIG. 4).

Although the details of the configuration and operation of the pulse width limiting circuit 5 will be described later, when the pulse width of the output signal from the comparator 3 is narrow, the pulse width limiting circuit 5 allows the pulse width of the output signal to pass as it is, and the pulse width is predetermined. Is a circuit that limits the width to a predetermined width when the width is wider than the width (for example, x ₁ ). Generally, the width of the noise signal is often very narrow, and the width of the disturbance signal of the MR head is very wide. Therefore, when a signal as shown in FIG. 4E is input to the pulse width limiting circuit 5, the noise signal is output as it is, and the disturbance signal of the MR head is output with the pulse width limited to a predetermined width x _1. ((F) of FIG. 4).

The D flip-flop circuit 6 is a flip-flop that holds the signal input to the D terminal when the signal applied to the T terminal rises. Furthermore, this D flip-flop circuit 6 has a reset terminal R, and this reset terminal sets the logic of the Q terminal of the D flip-flop 6 to "L" when the signal applied to the reset terminal becomes "H", and QC It has a function of setting the logic of the terminal to “H”. Therefore, if the signal waveform (e) is "H" at the rising of the signal (f), the output waveform (g) of the QC of the D flip-flop circuit 6 is "L". That is, the portion of the waveform (e) where the pulse width is x ₁ or more becomes “L”. On the other hand, in a waveform with a narrow width (<x ₁ ) such as noise, the rising edge of (f) is slightly behind the falling edge of (e), so at the rising edge of (f), (e) Signal waveform becomes "L", and the output of the D flip-flop circuit 6 does not change. Therefore, the output of the D flip-flop circuit 6 is, as shown in (g), from the pulse width x of the disturbance signal of the MR head to the pulse width x of the output signal of the pulse width limiting circuit 5.
Only the part where ₁ is subtracted is "L", and the other parts are all "H".

Embodiment 2. FIG. 3 is a diagram showing a circuit to which the pulse width limiting circuit 7 according to the second embodiment of the present invention is added. Since the width of the waveform (g) in the first embodiment is narrow,
The second embodiment shows an example in which the pulse width limiting circuit 7 is added when a wide pulse is required. Since FIG. 3 is the same as FIG. 2 until the output signal (g) of the D flip-flop circuit 6 is obtained, its description is omitted. By inputting the output waveform (g) of the D flip-flop circuit 6 to the pulse width limiting circuit 7, the pulse width x at the rising time of the waveform (g).
_It operates as a circuit that outputs ₂ pulses. By inputting the output (g) of the D flip-flop circuit 6 and the output (h) of the pulse width limiting circuit 7 to the NAND gate 8, a pulse having a pulse width x ₃ can be obtained. This x ₃
The pulse width of is adjusted by adjusting the pulse width x ₂ .
The pulse width x of the disturbance signal of the MR head ((e) in FIG. 4) can be made the same. By thus forming the pulse width x ₃ which is the same as the pulse width (e) of the disturbance signal of the MR head, it is used as a control signal for re-reading only the data in that period in an external circuit (disk drive or the like). can do.

Embodiment 3. FIG. 5 shows a pulse width limiting circuit 5
FIG. 3 is a diagram showing a detailed structure of the first embodiment. FIG. 6 is a diagram showing a timing chart for explaining the operation of the pulse width limiting circuit 5. In FIG. 5, 10 is an input terminal, 11 is a power supply,
12, 16, 17 are inverters, 13 are transistors,
Reference numeral 15 is a constant current source, 14 is a capacitor, 18 is a NAND gate, and 19 is an output terminal. In the pulse width limiting circuit 5, when the input signal waveform becomes "H", the transistor 13 is turned off, the capacitor 14 is charged, and the emitter voltage of the transistor 13 decreases as shown in (n) of FIG. . The reduction characteristic of the voltage of the emitter of the transistor 13 is adjusted by setting the capacitor 14 and the constant current source 15. When the voltage becomes lower than the threshold value V _th1 , the output levels of the inverters 16 and 17 are inverted and the output levels of FIG.
Changes as shown in (o) and (p). (E) of FIG.
In the case of a signal waveform such as that shown in FIG.
Can't go down to _th1 . Therefore, the polarities of the inverters 16 and 17 do not change. For this, NAN
The output (f) of the D gate 18 has the same width as the input signal (e) for the noise signal y, and a signal with only the polarity inverted is output.

On the other hand, in the case of the disturbance signal of the MR head,
The pulse width of the input signal is x. The time x ₁ until the voltage of the capacitor 14 becomes lower than the threshold value V _th1 is set shorter than the pulse width x. In this case, when the voltage of the capacitor 14 becomes lower than the threshold value V _th1 , the polarities of the inverters 16 and 17 are inverted as shown in (o) and (p) of FIG. Therefore, the signal waveform of (p) and the signal waveform of (e) are input to the input terminal of the NAND gate 18, and the output thereof is a signal having a pulse width x ₁ as shown in (f). As described above, in the pulse width limiting circuit 5,
Even if a signal having a long pulse width such as a disturbance signal of the MR head is input, the pulse width limiting circuit 5 outputs a predetermined pulse width (in this case, x ₁ ). Since the above-described operation is the same in the pulse width limiting circuit 7, the operation description in the pulse width limiting circuit 7 will be omitted.

[0020]

According to the first aspect of the present invention, the present invention provides a comparator for comparing the signal read by the MR head with the threshold value V _th, and a pulse included in the output signal of the comparator. , A pulse width limiting circuit for limiting the width of a pulse having a pulse width x greater than or equal to a predetermined pulse width x ₁ to x ₁ , and the output signal of the comparator is input to the D terminal and the R terminal to output the pulse width limiting circuit. Is input to the T terminal and a D flip-flop circuit that obtains an output from the inverting output terminal (QC) is used. Therefore, even when the read signal includes noise,
The disturbance signal indicating the disk contact of the MR head can be reliably detected without being affected by the noise.

According to the invention of claim 2, the present invention provides
Of the pulse included in the output signal of the comparator and the comparator that compares the signal read by the MR head with the threshold value V _th ,
A first pulse width limiting circuit for limiting the width of a pulse having a pulse width equal to or larger than a _first predetermined pulse width x ₁ to x ₁ , and an output signal of a comparator is input to a D terminal and an R terminal, A D flip-flop circuit for inputting the output of the pulse width limiting circuit of 1 to the T terminal and obtaining an output from the inverting output terminal (QC);
A second pulse width limiting circuit for receiving an output signal of the D flip-flop circuit and generating a pulse having a _second predetermined pulse width x ₂ , an output signal of the second pulse width limiting circuit and the D flip-flop circuit Input the output signal of
NAND that obtains a pulse width signal close to the disturbance signal of the head
Since it is composed of the gate, even if the read signal contains noise, the disturbance signal indicating the disk contact of the MR head can be reliably detected without being affected by the noise, and the disturbance signal of the MR head can be detected. It is possible to obtain a detection signal having a pulse width similar to that of.

According to the invention of claim 3, the present invention provides:
Since the first predetermined pulse width x ₁ and the second predetermined pulse width x ₂ are configured to be equal, a detection signal having a pulse width equal to the disturbance signal of the MR head can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a read / write (R / W) amplifier according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a disturbance signal detection circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a disturbance signal detection circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a timing chart for explaining the operation of the disturbance signal detection circuit of the present invention.

FIG. 5 is a diagram showing a configuration of a pulse width limiting circuit of the present invention.

FIG. 6 is a diagram showing a timing chart for explaining the operation of the pulse width limiting circuit of the present invention.

FIG. 7 is a diagram showing a general block configuration of a conventional hard disk drive.

FIG. 8 is a diagram showing a block configuration of a conventional read / write (R / W) amplifier.

FIG. 9 is a diagram showing signals of respective parts of a conventional R / W amplifier.

[Explanation of symbols]

 3 Comparator Circuit (COMP) 5, 7 Pulse Width Limiting Circuit 6 Flip-Flop Circuit 8 NAND Gate 10 Input Terminal 11 Power Supply 12, 16, 17 Inverter 13 Transistor 14 Capacitor 15 Constant Current Source 18 NAND Gate 19 Output Terminal 56 R / W Amplifier 80 First Amplifier 82 Second Amplifier 88 Disturbance Signal Detection Circuit 100 Input Terminal 200 Output Terminal 400 Output Terminal for Outputting Disturbance Signal

Claims (3)

[Claims] 1. A signal read by an MR head and a threshold value V
a comparator for comparing the _th, among the pulses included in the output signal of the comparator, x ₁ the width of the pulse having a predetermined pulse width x ₁ or more pulse width x
And a pulse width limiting circuit for limiting the output signal of the comparator to the D terminal and the R terminal,
And a D flip-flop circuit for inputting the output of the pulse width limiting circuit to a T terminal and obtaining an output from an inverting output terminal (QC), wherein the MR head selects the disk surface from the signals read by the MR head. A disk contact detection circuit for an MR head, characterized in that it detects a disturbance waveform generated upon contact. 2. A signal read by an MR head and a threshold value V
a comparator for comparing the _th, among the pulses included in the output signal of the comparator, a first pulse which limits the width of pulses having a first predetermined pulse width x ₁ or more pulse width x ₁ Inputting the output signal of the width limiting circuit and the comparator to the D terminal and the R terminal,
The output of the first pulse width limiting circuit is input to the T terminal,
A D flip-flop circuit that obtains an output from an inverting output terminal (QC); and an output signal of the D flip-flop circuit,
A _second pulse for generating a pulse having a predetermined pulse width x ₂ of
And a NAND gate that receives the output signal of the second pulse width limiting circuit and the output signal of the D flip-flop circuit to obtain a signal having a pulse width close to the disturbance signal of the MR head. A disk contact detection circuit for an MR head, which detects a disturbance waveform generated when the MR head comes into contact with the disk surface from the signals read by the MR head. 3. The disk contact detection circuit for an MR head according to claim 2, wherein the first predetermined pulse width x ₁ and the second predetermined pulse width x _1
2. A disk contact detection circuit for an MR head, characterized in that the predetermined pulse width x ₂ is set to be equal.