JPH097367A - Apparatus and method for refreshing dram - Google Patents

Abstract

PURPOSE: To decrease the amount of power dissipation and to shorten the time required for mode transition from an auto-refresh mode to a self-refresh mode in DRAM. CONSTITUTION: A mode switching signal for an auto-refresh mode and self- refresh mode is inputted from a signal line 10. When the signal is the auto-mode, an access-settling-timing forming circuit 3 outputs RAS and CAS and instructs the refreshment to DRAM. At this timer the number of refreshments is counted in a concentrated refresh counter 6. When the above described signal becomes the self-mode, the counted value A of the concentrated refresh counter 6 is compared with the stored value B of a concentrated refresh-number register 7. When the counted value A is smaller than the snored value B, RAS and CAS are outputted from a concentrated refresh-timing circuit 5 so that the refreshment is performed at a short interval. When the counted value A becomes larger than one stored value B, the DRAM is set an the selt-refresh mode.

Description

Detailed Description of the Invention

[0001]

This invention relates to a DRAM (dynamic ra
DR for refreshing ndom access memory)
The present invention relates to an AM refresh device and a DRAM refresh method.

[0002]

2. Description of the Related Art A DRAM has a capacitor in a memory cell, and stores data in the state of electric charge charged therein. The electric charge charged in this capacitor is gradually discharged by the leak current, and finally the data disappears. Therefore, it is necessary to rewrite (refresh) every certain time. In addition, at the time of refreshing, it is possible to control the DRAM from the CPU by software by a program to perform the refreshing. However, in order to retain the contents of the memory even when an abnormality occurs in the CPU, the refreshing is performed by a hardware. It is necessary to provide a refresh circuit for controlling the above.

In a DRAM, the address of a memory cell is shown by rows × columns, and when an address is specified via an address bus, the address signal is The address of the row is divided into the address of the column and the address of the column without sending them at a time. At this time, the control signal when passing the bit of the address of the row to the DRAM via the address bus is RAS (row ad
dress select) and DRA the bid of the column address
The control signal when passing to M is CAS (column address sel
ect). Then, normally, in a state where RAS is output corresponding to the output of the row address, CAS is output corresponding to the output of the column address.

At the time of refreshing, for example,
By outputting RAS while outputting CAS to the DRAM, the memory cells in the specified row are refreshed. Every time CAS and RAS are input at the above timing, Rows are sequentially moved to refresh the memory cells in order.

Further, the DRAM has a refresh address counter for designating a row to be refreshed, and when the control signal as described above is input from the outside, the DRAM is designated as the refresh address counter. The memory cell at the specified address is refreshed.

For refreshing, when the DRAM is accessed by a processor (CPU) or the like, C is used.
An auto refresh mode (auto mode) in which refresh is performed by arbitrating the timing of access of PU or the like and refresh, and DRAM without access from the CPU
There is a self-refresh mode (self-mode) when is in a sleep state.

Further, at the time of transition from the auto mode to the self mode, at least DR
Self refresh is performed at the stage where all the memory cells of AM are refreshed once, that is, at the stage where refresh for one cycle is executed.

Therefore, in the refresh circuit, when the control signal for instructing the transition to the self mode is input from the CPU during the auto mode, if the refreshing of all the memory cells is in the middle, the remaining memory cells are left. The DRAM cannot be put into the self mode until the refresh of the memory is completed.

In the above method, when switching from the auto mode to the self mode, if the refresh in the auto mode is just started, the mode transition takes a long time.

Therefore, in the refresh circuit, when the control signal instructing the transition to the self mode is input, the refresh in the auto mode is interrupted, and the refresh for one cycle is performed in an extremely short refresh time (from refresh to next refresh). There is a method of switching to a centralized refresh mode (centralized mode) that is performed at intervals until refreshing, terminating refreshing for one cycle in a short time, and then switching to a self mode.

That is, in the method of shifting from the auto mode to the self mode, when a control signal for instructing the shift to the self mode is input, the refresh is continued for a relatively long refresh time in the auto mode and the remaining Refresh memory cells and then shift to self mode, and when a control signal that directs the shift to self mode is input, the auto mode with a relatively long refresh time changes to the concentrated mode with an extremely short refresh time. There is a method of switching to the self-mode after switching for 1 cycle in the concentrated mode and then shifting to the self mode. In the latter method, the time required for mode transition can be shortened.

[0012]

By the way, in the former refresh method, since the mode transition has a long time and the response is bad as described above, for example, a quick OFF process such as an emergency OFF process in the case of a power failure such as a power failure. Not suitable for processing.

Further, the refresh in the auto mode consumes more power than the refresh in the self mode. In the latter refresh method, the time required for the mode transition can be shortened as described above, but At the time of the transition, the number of refreshes in the auto mode, that is, one cycle of the refresh in the concentrated mode is performed regardless of the elapsed time in the auto mode, so the number of refreshes increases compared to the former refresh method. , The power consumption of the DRAM will increase.

Therefore, when the latter refresh method is used in a portable information device driven by a battery, the operating time is shortened due to an increase in the power consumption of the DRAM. An object of the present invention is to shorten the time required for the transition from the auto mode to the self mode and reduce the power consumption.

[0015]

A DRAM refresh device according to claim 1 of the present invention has an auto-refresh mode in which a refresh is performed based on a signal from the outside when there is an access from the outside, and an access from the outside. For a DRAM having a self-refresh mode in which refresh is performed by internal control when it is suspended,
A DRAM refresh device for instructing a refresh timing in the auto-refresh mode, which arbitrates access to the DRAM from the outside and a refresh timing corresponding to a predetermined refresh interval, and also arbitrates the refresh timing. First control signal output means for outputting a refresh control signal for instructing the DRAM, and the DRAM with a refresh interval shorter than the predetermined refresh interval.
In the second control signal output means for outputting the refresh control signal for instructing the refresh timing so that the refresh is intensively performed, and the refresh timing in the refresh control signals output from the first and second control signal output means. Correspondingly, a refresh counter that counts the number of refreshes and, when shifting from the auto-refresh mode to the self-refresh mode, suspend the output of the refresh control signal by the first control signal output means, and Signal output control means for outputting a refresh control signal by the second control signal output means until the count value of the refresh counter reaches a predetermined count value when the count value is equal to or less than a preset predetermined count value. And characterized by being provided.

According to a second aspect of the present invention, there is provided a refresh method for a DRAM in which an auto-refresh mode in which a refresh is performed based on a refresh control signal from the outside when there is an access from the outside and an access from the outside is suspended. A method of refreshing a DRAM for outputting the refresh control signal in the auto-refresh mode to a DRAM having a self-refresh mode in which a refresh is performed by internal control in the case of the auto-refresh mode.
When a refresh control signal for instructing a refresh timing in which access to the DRAM from the outside and a predetermined refresh interval are arbitrated is output and the number of refresh times is counted, and then the transition from the auto refresh mode to the self refresh mode is performed, The output of the refresh control signal corresponding to the predetermined refresh interval is interrupted, and it is determined whether or not the number of refreshes in the auto refresh mode has reached a preset number of times, and the number of refreshes has not reached the predetermined number of times. In this case, if the refresh interval is shorter than the predetermined refresh interval, the refresh control signal for instructing the refresh timing is concentrated so that the remaining refreshes that are insufficient for the predetermined number are concentrated. And outputs to reach.

[0017]

According to the structure described in claim 1, in the auto refresh mode, the first control signal output means outputs the refresh control signal at substantially predetermined refresh intervals while arbitrating and accessing from the outside. To be done.

When shifting from the auto-refresh mode to the self-refresh mode, the signal output control means interrupts the refresh control signal from the first control signal output means, and the value of the refresh number counter is preset. When the set predetermined count value, that is, the number of refreshes for one cycle has not been reached, the second control signal output means outputs an extremely short refresh until the count value of the refresh counter reaches the number of refreshes for one cycle. A refresh control signal corresponding to the interval is output.

Therefore, when the auto mode is changed to the self mode, if the one cycle portion has already been refreshed, the self mode is directly changed. If one cycle of refresh is not yet completed when shifting from the auto mode to the self mode, until one cycle of refresh is performed,
Refreshing in the centralized mode is performed only for the rest of one cycle.

Therefore, like the former refresh method in the related art, in the auto mode, when the mode is changed to the self mode before the completion of the refresh of one cycle, the refresh of the one cycle is performed. It is possible to shift from the auto mode to the self mode in a shorter time than when the refresh is performed for a relatively long refresh time in the auto mode and then to the self mode until the rest of the refresh is performed.

Further, in the present embodiment, as compared with the latter refresh method of the above-mentioned conventional case, when the concentrated refresh is performed for one cycle with an extremely short refresh time when shifting from the auto mode to the self mode. Since the mode is shifted to the self mode with less intensive refresh than one cycle, the time required for mode transition can be further shortened and the number of refreshes at the time of mode transition can be reduced to reduce the power consumption of DRAM. The consumption can be reduced.

According to the second aspect of the present invention,
Similar to the configuration described in claim 1, when the automatic mode is switched to the self mode, a predetermined number of times, that is,
If one cycle of refresh has been performed, the mode directly shifts to the self mode, and if one cycle of refresh is not yet completed, the rest of the one cycle of refresh is performed until one cycle of refresh is performed. Only the refresh of will be performed in the intensive mode. Therefore, in a shorter time than before, and
It is possible to reduce the power consumption and shift from the auto mode to the self mode.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A DRAM refresh device and a DRAM refresh method according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the basic configuration of the DRAM refresh device (refresh circuit) of this embodiment.

As shown in FIG. 1, the DRAM of this embodiment
The refresh device is based on the refresh clock generator 1 that outputs a clock signal for synchronizing the refresh timing in the auto mode, the timing of access to the DRAM 2 from a CPU (not shown), and the clock signal of the refresh clock generator 1. An access arbitration timing generation circuit 3 that arbitrates the refresh timing and outputs RAS and CAS corresponding to the arbitrated timing; and a refresh clock generator 4 that outputs a clock signal for adjusting the refresh timing in the centralized mode. A centralized refresh timing circuit 5 for outputting RAS and CAS for instructing a DRAM to refresh in response to a clock signal of the refresh clock generator 4, The centralized refresh counter 6 that counts the clock signals from the refresh clock generator 1 and the centralized refresh clock generator 4, the centralized refresh count register 7 in which the refresh count for one cycle is stored as a specified number, and the centralized refresh counter 6 described above. The count value A and the value B stored in the centralized refresh frequency register 7 are compared, and A ≧ B
In this case, it has a comparator 8 that outputs a signal and a latch 9 that holds an output signal from the comparator 8.

Further, the DRAM refresh device receives a mode switching control signal for controlling switching between the auto mode and the self mode from the signal line 10, and the mode switching control signal is , The control signal is 1 when the auto mode is ON (1)
(High), and the control signal becomes 0 (Low) when the self mode is ON (1).

In addition, the mode refreshing control signal from the signal line 10 is inverted and input to the DRAM refresh device, and the output signal from the latch 9 is inverted and input to the centralized refresh enable (centralized refresh enable). AND gate 11 for outputting a control signal for permitting refresh in the mode to the centralized refresh clock generator 4, and the mode switching control signal from the signal line 10 is inverted and input, and latch 9
AND gate 12 to which an output signal from the CPU is input and an inverted self-enable (control signal for enabling the self mode) signal is output, the refresh clock generator 1, and the centralized refresh clock generator 4
OR gate 13 to which a signal from is input, OR gate 14 to which RAS as a control signal output from access arbitration timing generation circuit 3 and centralized refresh timing circuit 5 is input, access arbitration timing generation circuit 3 and centralized The OR gate 14 to which CAS as a control signal output from the refresh timing circuit 5 and the RAS as a control signal to be output from the OR gate 14 are input, and the AND gate 12
The inverted self-enable signal from A is input
The ND gate 16 and CAS as a control signal output from the OR gate 15 are input, and AND
AND gate 17 to which the inverted self-enable signal from gate 12 is input.

Next, each part of the DRAM refresh device will be described in detail based on the mode switching control signal inputted from the signal line 10. The refresh clock generator 1 is well known and outputs a clock signal corresponding to a refresh cycle in the auto mode.

The refresh clock generator 1 is connected to the signal line 10, and when the mode switching control signal from the signal line 10 is 1 indicating the auto mode, the output of the clock signal is turned on and the mode switching control signal is turned on. Is 0 indicating the self mode, the output of the clock signal is turned off.

The clock signal output from the refresh clock generator 1 is a CP signal as described later.
It outputs a clock signal for adjusting the refresh timing when there is access from U to DRAM2, and the refresh time from refresh to next refresh is relatively long so as not to disturb access from CPU to DRAM2. It outputs the set clock signal.

Access arbitration timing generation circuit 1
Is supplied with a clock signal corresponding to a refresh cycle in the auto mode from the refresh clock generator 1 and a control signal indicating access to the DRAM from a CPU (not shown) via a signal line 18. Therefore, the refresh timing and the access timing from the CPU are arbitrated to output the well-known RAS and CAS control signals to the DRAM 2.

That is, the access arbitration timing generation circuit 1 arbitrates so that the access from the CPU and the refresh from the refresh device do not collide with each other.
In the case of access from the CPU, the RAS is output first, and the CAS is output so as to overlap a part of the RAS to control the input of the row address and the column address from the address bus to the DRAM. At the same time, when refreshing, CAS is output first, and RAS is output so as to overlap with a part of CAS to instruct the DRAM 2 to refresh.

The output of the RAS and CAS at a predetermined timing is a control signal for instructing the DRAM 2 to refresh. The centralized refresh clock generator 4 is well known and is adapted to output a clock signal corresponding to a refresh cycle in the centralized mode.

The centralized refresh clock generator 4 is connected to the signal line 10 and the latch 9 via the AND gate 11, and the mode switching control signal from the signal line 10 indicates the self mode (0). , And the signal from the latch 9 is 0, the AND gate 1
The centralized refresh enable signal (1) is output from 1 and the output of the clock signal from the centralized refresh clock generator 4 is turned on.

In the centralized refresh clock generator 4, the clock signal is output after the mode switching control signal from the signal line 10 is switched to the self mode (0), and CPU access and timing are adjusted. There is no need to do so, and a clock signal corresponding to an extremely short refresh time is output.

Centralized refresh timing circuit 5
Is supplied with a clock signal corresponding to the refresh cycle in the centralized mode from the centralized refresh clock generator 4, and based on the clock signal, DR
CAS and R to instruct AM2 to refresh
It is designed to output AS.

That is, the centralized refresh timing circuit 5 outputs a control signal for instructing refresh to the DRAM 2 in a refresh time extremely shorter than that of the access arbitration timing generation circuit 3. The centralized refresh counter 6 is connected to the refresh clock generator 1 and the centralized refresh clock generator 4 via an OR gate 13,
The clock signals output from these can be counted.

That is, both the number of refreshes in the auto mode performed based on the clock signal from the refresh clock generator 1 and the number of refreshes in the centralized mode performed based on the clock signal from the centralized refresh clock generator 4 can be counted. It is like this.

The centralized refresh frequency register 7 stores the refresh frequency necessary for refreshing all the memory cells of the DRAM 2 once, as a prescribed number. The comparator 8 compares the count value A output from the centralized refresh counter 6 with the stored value B output from the centralized refresh count register 7, and outputs a signal to the latch 9 when A ≧ B. It has become.

The latch 9 holds the signal when the signal is output from the comparator 8 and outputs it to the AND gate 11 and the AND gate 12, and is connected to the signal line 10 to connect to the signal line 10. When the mode switching control signal from 1 becomes 1 indicating the auto mode, it is cleared.

Next, D of this embodiment will be described based on the operation of each part in the DRAM refresh device having the above configuration.
A RAM refresh method will be described with reference to FIG.
First, turn on the information device having the DRAM 2 described above,
When the CPU accesses the DRAM 2, the mode switching control signal from the signal line 10 becomes 0 to 1.

At this time, the output of the clock signal from the refresh clock generator 1 connected to the signal line 10 is turned on, and the clock signal is output to the access arbitration timing circuit 3.

Then, in the access arbitration timing circuit 3, based on the control signal indicating the access from the CPU via the signal line 18 and the clock signal, the CPU
Access and refresh are arbitrated and RAS and CAS are output to the AND gate 16 and the AND gate 17 via the OR gate 14 and the OR gate 15, respectively.

Further, the latch 9 is cleared by the signal indicating the auto mode (1) from the signal line 10, and the output signal from the latch 9 to the AND gate 11 and the AND gate 12 becomes zero.

In the AND gate 12, the signal from the signal line 10 becomes 1 and the output from the latch 9 becomes 0.
Therefore, the output to the AND gate 16 and the AND gate 17 becomes 1, and in the AND gate 16 and the AND gate 17, the RAS input from the access arbitration timing generation circuit 3 via the OR gate 14 and the OR gate 15, respectively. And CAS control signal is DR as it is
It is output to AM2. That is, the refresh in the auto mode is executed (step S1).
In the D gate 11, since the signal from the signal line 10 becomes 1 and the signal from the latch 9 becomes 0, the output signal to the centralized refresh clock generator 4 becomes 0 and the clock signal from the centralized refresh clock generator 4 becomes. It will not be output. Therefore, the centralized refresh timing circuit 5 is in a state in which the RAS and CAS control signals are not output.

As described above, the clock signal output from the refresh clock generator 1 is also input to the centralized refresh counter 6 via the OR gate 13, and the centralized refresh counter 6 outputs the clock signal of 1. Then, the number of refreshes in the auto mode is counted (step S2).

When the mode switching control signal from the signal line 10 remains in the auto mode (1), that is, CP
Set self mode to O so that the mode changes from U to self mode.
When the command to set N (1) is not output (step S
3), DR from the access arbitration timing generation circuit 3
RAS and CAS are sequentially output at the timing of instructing AM2 to refresh, and the number of refreshes is counted by the centralized refresh counter 6.

The count value A of the centralized refresh counter 6 is the stored value B of the centralized refresh frequency register 7.
In the case of the above, the latch 9 from the comparator 8
The output signal to the latch 9 becomes 1, but when the mode switching control signal from the signal line 10 is the auto mode (1), the latch 9
Is cleared, the output signal from the latch 9 to the AND gates 11 and 12 remains 0.

On the other hand, when the CPU outputs an instruction to set the self mode to 1 so as to transit to the self mode (step S3), the mode switching control signal from the signal line 10 becomes 0. At this time, the output of the clock signal from the refresh clock generator 1 is turned off, and the outputs of RAS and CAS from the access arbitration timing generation circuit 3 are turned off.

Further, the control signal from the signal line 10 to the latch 9 becomes the self mode (0), and the clear to the latch 9 is released. Therefore, in the comparator 8, when the count value A of the centralized refresh counter 6 is equal to or larger than the stored value B of the centralized refresh frequency register 7, the latch 9 to the AND gates 11 and 12 are used.
If the count value A of the centralized refresh counter 6 is still equal to or smaller than the stored value B of the centralized refresh frequency register 7 in the comparator 8, the output from the latch 9 to the AND gates 11 and 12 is 0. Will remain.

That is, the comparison result of the count value A and the stored value B by the comparator 8 is output only when the latch 9 is cleared, and the count value A of the centralized refresh counter 6 is the number of centralized refresh times. It is determined whether or not the value stored in the register 7 is equal to or more than the stored value B (specified number) (step S4).

Here, if the count value A is already equal to or greater than the stored value B, the output from the comparator 8 to the latch 9 changes from 0 to 1, and the output from the latch 9 to the AND gates 11 and 12. Goes from 0 to 1.

Therefore, in the AND gate 11, the input from the latch 9 becomes 1 while the mode switching control signal via the signal line 10 is in the self mode (0), so that the output becomes 0 and concentrated. Refresh generator 4
The output of the clock signal from the CPU remains OFF, and the outputs of the RAS and CAS from the centralized refresh timing circuit 5 remain OFF.

Further, in the AND gate 12, the input from the latch 9 becomes 1 while the mode switching control signal via the signal line 10 is in the self mode (0), so that the output is 0, that is, In the AND gate 16 and the AND gate 17 which are in the self-enable state and the output of 0 from the AND gate is input, the OR gate 1
4 and the output from RAS and CAS from the accelerator arbitration timing circuit 3 or the centralized refresh timing circuit 5 via the OR gate 15 are cut off.

Then, the DRAM 2 is self-enabled, and the process proceeds to step S8 for performing refresh in the self-refresh mode.
Further, at this time, the output of 0 from the AND gate 12 is inverted and input to the reset signal terminal of the centralized refresh counter 6, and the centralized refresh counter 6 is reset.

On the other hand, if the count value A is not equal to or greater than the stored value B, as described above, the latch 9 AND
The output to the gate 11 becomes 0, the output from the signal line 8 to the AND gate 11 becomes the self mode (0), and the AND
The output from the gate 11 becomes 1.

Therefore, the output of the clock signal from the centralized refresh generator 4 connected to the AND gate 11 is turned on, and the centralized refresh timing circuit 5 to which this clock signal is input refreshes the DRAM 2 in the refresh cycle in the centralized mode. RAS and CAS are output to instruct.

The centralized refresh timing circuit 5
The RAS and CAS output from the AND gate 16 and the AND gate 16 are connected via the OR gate 14 and the OR gate 15.
It is input to the gate 17.

In the AND gate 12, since the input signal from the latch 9 is 0 and the control signal input from the signal line 10 is in the self mode (0), AND
The output to the gate 16 and the AND gate 17 becomes 1,
In the AND gate 16 and the AND gate 17, the RAS and CAS control signals input from the centralized refresh timing circuit 5 via the OR gate 14 and the OR gate 15, respectively, are directly output to the DRAM 2. That is, the refresh in the concentrated mode is executed (step S5).

The clock signal output from the centralized refresh clock generator 1 as described above is O
It is also input to the centralized refresh counter 6 via the R gate 13, and the number of times the clock signal becomes 1 in the centralized refresh counter 6, that is, the number of refreshes in the centralized mode is counted (step S6).

Therefore, the centralized refresh counter 6 counts the number of refreshes during the auto mode, and when the mode switching control signal from the auto mode to the self mode is input, the count value A of the centralized refresh counter 6 is counted. Is not more than the stored value B of the concentrated refresh frequency register 7, the refresh frequency in the concentrated mode is continuously counted.

Then, the comparator 8 compares the count value A with the stored value B (specified number) as described above, and outputs a signal indicating whether or not the count value A becomes the stored value B or more. Therefore, when the value of the centralized refresh counter 6 is counted up and the count value A is still smaller than the stored value B (step S7), the output from the comparator 8 to the latch 9 remains 0, The output from 9 to the AND gates 11 and 12 also remains 0. Then, the refresh in the concentrated mode is continued as it is.

If the count value A becomes greater than or equal to the stored value B when the value of the centralized refresh counter 6 is counted up (step S7), the comparator 8
The output from the latch 9 to the latch 9 becomes 0 to 1, and the output from the latch 9 to the AND gates 11 and 12 becomes 0 to 1.

Therefore, in the AND gate 11, since the input from the latch 9 is 1 in the state where the mode switching control signal via the signal line 10 is in the self mode (0), the output becomes 0 and the concentrated refresh is performed. Generator 4
The output of the clock signal from the CPU is turned off, and the RAS and CA from the centralized refresh timing circuit 5 are output.
The output of S turns off.

In the AND gate 12, since the input from the latch 9 is 1 in the state where the mode switching control signal via the signal line 10 is in the self mode (0), the output is 0, that is, self. AN in the enabled state, to which the output of 0 from the AND gate 12 is input
In the D gate 16 and the AND gate 17, the accelerator arbitration timing circuit 3 or the centralized refresh timing circuit 5 via the OR gate 14 and the OR gate 15
The output of RAS and CAS from is cut off.

Then, the DRAM 2 is self-enabled and refresh in the self-refresh mode is executed (step S8). Further, at this time, the output of 0 from the AND gate 12 is inverted and input to the reset signal terminal of the centralized refresh counter 6, and the centralized refresh counter 6 is reset.

In the self mode, when the mode switching control signal from the signal line 10 becomes the auto mode (1), the mode is returned to the auto mode and the refresh generator 1 outputs the clock signal as described above.
Access arbitration timing generation circuit 3 to RAS and CA
S is output, and the refresh in the auto mode is performed.

FIG. 3 (A) shows that when the mode switching control signal is switched from the auto mode to the self mode, in the auto mode, more than all the memory cells of the DRAM 2 are refreshed, that is, It shows the refresh timing when the count value A of the centralized refresh counter 6 is equal to or larger than the stored value B of the centralized refresh count register when the mode switching control signal is switched to the self mode.

As shown in FIG. 3A, if the count value A is equal to or greater than the stored value B when the mode switching control signal is in the self mode, the DRAM 2 directly shifts to the self mode. . Further, FIG. 3B shows that, when the mode switching control signal is switched from the auto mode to the self mode, in the auto mode, refreshing for refreshing all the memory cells of the DRAM 2 is not performed, that is, It shows the refresh timing when the count value A of the centralized refresh counter 6 is smaller than the stored value B of the centralized refresh frequency register when the mode switching control signal is switched to the self mode.

As shown in FIG. 3B, when the count value A is smaller than the stored value B when the mode switching control signal is in the self mode, the DRAM 2 is directly transferred to the self mode. The refresh in the concentrated mode is performed until the count value A matches the stored value B, that is, until the remaining memory cells that have not been refreshed in the auto mode are refreshed.

As described above, according to the DRAM refresh device and the DRAM refresh method of this embodiment,
In the mode transition from the auto mode to the self mode, when all the memory cells of the DRAM 2 are refreshed once or more by the auto mode, that is, when the refresh for one cycle or more is completed, The count value A of the centralized refresh counter 6 becomes equal to or larger than the value B stored in the centralized refresh count register 7, and the mode directly shifts to the self mode.

Further, in the mode transition from the auto mode to the self mode, if all the memory cells of the DRAM 2 have not been refreshed by the auto mode, that is, if the refresh for one cycle has not been finished, the above concentration is caused. Refresh counter 6
Is smaller than the value B stored in the centralized refresh frequency register 7, the quick refreshing in the centralized mode is started, and the count value A of the centralized refresh counter 6 is further incremented so that the count value A becomes When the stored value B is equal to or more than the stored value B, the mode transitions to the self mode. That is, in the concentrated mode, only the remaining memory cells that were not refreshed by the auto mode are refreshed.

Therefore, in this embodiment, when there is a remaining memory cell that has not been refreshed in the auto mode at the time of the mode transition from the auto mode to the self mode as in the former refresh method of the related art, the auto mode remains unchanged. Is extended, and the mode transition from the auto mode to the self mode can be performed in a short time as compared with the case where the remaining memory cells are refreshed over a relatively long refresh time.

When the memory mode is changed from the auto mode to the self mode and all the memory cells are refreshed from the beginning with an extremely short refresh time in the concentrated mode as in the latter conventional refresh method. Even in comparison, in this embodiment, since only the remaining memory cells are refreshed in the concentrated mode, the mode transition from the auto mode to the self mode can be achieved in a short time.

Further, in the latter method of the related art, when the mode transitions from the auto mode to the self mode, all the memory cells are refreshed from the beginning by shifting to the concentrated mode, whereas in this embodiment, in the auto mode. , When all the memory cells of the DRAM 2 are refreshed once, as shown in FIG. 3A, the memory cell shifts to the self mode without performing the refresh in the concentrated mode, and at the time of mode transition, the memory cell is set in the auto mode. When there is a remaining memory cell that has not been refreshed for the second time, as shown in FIG. 3B, only the remaining memory cell is refreshed in the concentrated mode. Since the number of times can be minimized, reduce the time required for mode transition. It is possible, by preventing the unnecessary refresh, it is possible to reduce the consumption of power by the DRAM.

Therefore, the time required for the mode transition from the auto mode to the self mode can be shortened, and the mode transition can be performed in a short time even when an emergency process such as a power failure is required. The power consumption can be reduced. Further, by reducing the power consumption of the DRAM, it is possible to extend the usage time in a portable information device which is supplied with power by a battery.

The circuit of the DRAM refresh device shown in FIG. 1 of the above embodiment is an example, and basically, when the mode switching control signal is in the auto mode, the access arbitration timing generation circuit 3 outputs the auto mode. RA corresponding to
When S and CAS are output to the DRAM, the number of refreshes is counted by the centralized refresh counter 6, and when the mode switching control signal is switched from the auto mode to the self mode, the count value A of the centralized refresh counter 6 is 1 cycle. If the count value A of the centralized refresh counter is smaller than the refresh count for one cycle, the centralized refresh is performed until the count value A reaches the refresh count for one cycle. It is sufficient that the timing circuit 6 outputs RAS and CAS corresponding to the centralized mode to the DRAM.

In the above embodiment, the DRAM refresh device having the structure shown in FIG. 1, that is, the interface device between the CPU and the DRAM is used to instruct the DRAM of the refresh timing. It is also possible to execute the above-described processing as a program by a possible device and to instruct the refresh timing for the DRAM by software.

[0078]

According to the DRAM refresh device of the first aspect, the time required for the mode transition from the auto mode to the self mode can be shortened and the power consumption can be reduced. It is possible to improve it to make it a stable circuit that can respond to emergency processing such as power outages, etc., and reduce the electric power consumption to reduce the electrical life of portable information devices etc. that are powered by batteries. Can be long.

According to the DRAM refreshing method of the second aspect, the same excellent effect as that of the configuration of the first aspect can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a basic configuration of a DRAM refresh device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation flow of a DRAM refreshing device for explaining a DRAM refreshing method of the above embodiment.

FIG. 3 is a time chart for explaining refresh in the auto refresh mode.

[Explanation of symbols]

1 Refresh Clock Generator (First Control Signal Output Means) 2 DRAM 3 Access Arbitration Timing Generation Circuit (First Control Signal Output Means) 4 Centralized Refresh Clock Generator (Second Control Signal Output Means) 5 Centralized Refresh Timing Circuit (Second Control) Signal output means) 6 Centralized refresh counter (refresh count counter) 7 Centralized refresh count register (signal output control means) 8 Comparator (signal output control means) 9 Latch (signal output control means) 10 Signal line (for mode switching control signal) 11 AND Gate (Signal Output Control Means) 12 AND Gate (Signal Output Control Means) 13 OR Gate 14 OR Gate 15 OR Gate 16 AND Gate (Signal Output Control Means) 17 AND Gate (Signal Output Control Means) 18 Signal Line (External) For access control to the DRAM from)

Claims (2)

[Claims] 1. An auto-refresh mode in which a refresh is performed based on a signal from the outside when there is an access from the outside, and a self-refresh mode in which refresh is performed by internal control when the access from the outside is suspended. A DRAM refreshing device for instructing a DRAM having the refreshing timing in the auto-refresh mode, which arbitrates access to the DRAM from the outside and refreshing timing corresponding to a predetermined refreshing interval. First control signal output means for outputting a refresh control signal for instructing the DRAM of the refresh timing to be refreshed, and intensive refresh in the DRAM by a refresh interval shorter than the predetermined refresh interval. The second control signal output means for outputting the refresh control signal for instructing the refresh timing as described above, and the number of refresh times corresponding to the refresh timing in the refresh control signals output from the first and second control signal output means. The refresh counter that counts and, when shifting from the auto-refresh mode to the self-refresh mode, suspends the output of the refresh control signal by the first control signal output means, and sets the count value of the refresh counter in advance. And a signal output control means for causing the second control signal output means to output a refresh control signal until the count value of the refresh counter reaches a predetermined count value. Characterizing DRAM refresh device. 2. An auto-refresh mode in which a refresh is performed based on a refresh control signal from the outside when there is an access from the outside, and a self-refresh mode in which a refresh is performed by an internal control when the access from the outside is suspended. A method of refreshing a DRAM for outputting the refresh control signal in an auto refresh mode to a DRAM having:
A refresh control signal for instructing a refresh timing in which access to the RAM and a predetermined refresh interval are arbitrated is output, and the number of refresh times is counted. Then, when the auto refresh mode is changed to the self refresh mode, the predetermined refresh is performed. The output of the refresh control signal corresponding to the interval is interrupted, and it is determined whether the number of refreshes in the auto refresh mode has reached a preset number of times.If the number of refreshes has not reached the predetermined number of times, With a refresh interval shorter than the predetermined refresh interval, a refresh control signal for instructing the timing of refresh so that the remaining refreshes that are insufficient for the predetermined number of times are concentrated is performed. DRAM refresh method characterized by in output.