JPH0973400A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor circuit which can prevent its internal circuit from malfunctioning by providing a noise detecting circuit which detects external noise entering the power line for a data input/output part from the data input/output part and generates an interruption signal and a means which performs specific interruption processing. SOLUTION: At the terminal side of the power line 102 for the data input/ output part which branches off from the power line 7 supplying electric power to a central processor and a storage circuit 9 arranged at the periphery on a semiconductor integrated circuit chip 1 and supplies the electric power to the data input/output part 4, the noise detecting circuit 101 detects the external noise entering the power line 102 for the data input/output part from the data input/output part 4. Then the noise detecting circuit 101 when detecting the external noise generates the interruption signal to perform the interruption processing. Consequently, malfunction which may be caused by the noise inputted to the input/output part power line 102 can effectively be prevented. Further, the threshold value for the external noise detected at the terminal side of the data input/output part power line 102 is preferably set higher than the threshold values of other circuit elements of the central processor, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit capable of effectively avoiding malfunction of an internal circuit due to external noise.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a configuration of a conventional one-chip microcomputer which is a semiconductor integrated circuit. FIG. 7 is a circuit diagram showing an output circuit of the interface device of the one-chip microcomputer. FIG.
FIG. 4 is a waveform diagram showing various external noises.

In FIG. 6, 1 is a chip constituting a microcomputer (hereinafter referred to as a microcomputer chip), 3 is an internal system of the microcomputer chip 1 to an external system 2, or an external system 2 is an internal system of the microcomputer chip 1. External terminals 4 for inputting and outputting data signals are interface devices for exchanging data between the microcomputer chip 1 and the external system 2. Reference numeral 5 is a Vcc power supply, 6 is a ground line (hereinafter referred to as GND line), and 7 is a Vcc power supply line (hereinafter,
Vcc line), 8 is a microcomputer chip 1
It is a GND line wired inside. Reference numeral 9 denotes an internal circuit such as a central processing unit and a memory circuit arranged in the central portion inside the microcomputer chip 1. Reference numeral 10 is a first data bus for transmitting a data signal from the external system 2 to the external terminal 3 and also transmitting a data signal from the external terminal 3 to the external system 2, and 11 is a data signal from the external terminal 3 to the interface device 4. A second data bus for transmitting a data signal from the interface device 4 to the external terminal 3, and a second data bus 12 for transmitting a data signal input from the interface device 4 to the internal circuit 9 or the internal circuit 9 Is a third data bus for transmitting a data signal output from the interface device 4 to the interface device 4. Reference numeral 13 represents the wiring capacitance of the Vcc line 7.

In FIG. 7, 20 is an output circuit of the interface device 4, and 21 is an output control signal transmitted from the third data bus 12 when the data signal is sent to the second data bus 11. Output control signal line. 22 is an output circuit 20 via an output control signal line 21.
Is an output buffer that outputs the content of the data signal sent by the third data bus 12 to the second data bus 11 when is in the output state. Reference numeral 23 is a P-channel transistor circuit which is turned on when the output buffer 22 outputs a signal of'H 'level to the second data bus 11. 24 is the output buffer 22 is the second data bus 11
It is an N-channel transistor circuit that is in an ON state while outputting a signal of'L 'level to.

Reference numeral 25 shows an equivalent circuit of a diode formed from a P region and an N region when the output buffer 22 is formed on the chip, 26 is a diode equivalent circuit in the P-channel transistor circuit 23, and 27 is N. The diode equivalent circuit in the channel transistor circuit 24 is shown, and both are represented by a diode circuit.

FIG. 8 is a waveform diagram showing external noise input to the microcomputer chip 1 via the external terminal 3 and the output buffer 22, and FIG.
8 shows the waveforms of various external noises input from
(B) shows the voltage level state of the Vcc line 7 when it is affected by external noise. Reference numeral 32 represents external noise above the Vcc level potential, 33 represents external noise below the Vcc level potential, 34 represents external noise above the GND level potential, and 35 represents external noise below the GND level potential. 36 is the state of the Vcc line 7 when it is affected by the external noise 32, and 37 is the noise 33.
Represents the state of the Vcc line 7 when affected by, and 38 represents the state of the Vcc line 7 when affected by the noise 34.

Next, the external noise that affects the Vcc line 7 wired inside the microcomputer chip 1 will be described. External noise input to the inside of the microcomputer chip 1 via the external terminal 3 and the P-channel transistor 23 is 3 as shown in FIG.
There are four types: 2, 33, 34, and 35. The external noise 32 is an external noise that is input to the inside of the microcomputer chip 1 by exceeding the potential of the Vcc level. When the external noise 32 is input from the external terminal 3, the external noise 3 is input.
When the potential of 2 is a potential at which the diode equivalent circuit of the P-channel transistor 23 is turned “ON”, the external noise 32 is input to the Vcc line 7 via the P-channel transistor 23, and 36 of FIG. As shown in, the potential level state of the Vcc line 7 becomes higher than the original potential of the Vcc level.

If external noise 33, which is below the Vcc level potential and is input into the microcomputer chip 1, is input from the external terminal 3 while the P-channel transistor 23 is in the ON state, the external noise 33 is external. The noise 33 passes through the P-channel transistor 23 and becomes V
It is input to the cc line 7 and, as shown at 37 in FIG.
The potential state of the cc line 7 becomes lower than the potential of the original Vcc level.

When the external noise 34 input to the inside of the microcomputer chip 1 exceeds the GND level potential and is input from the external terminal 3, the potential of the external noise 34 is the diode equivalent circuit of the P-channel transistor 23. When the potential is a level for turning ON "26", the external noise 34 is input to the Vcc line 7 via the P-channel transistor 23, and the potential state of the Vcc line 7 is as shown at 38 in FIG. 8B. It becomes higher than the original Vcc level potential.

Further, when the external noise 35 input to the inside of the microcomputer chip 1 below the GND level potential is input from the external terminal 3, the potential of the external noise 35 is the diode equivalent circuit 27 of the N-channel transistor 24. When the potential is at a level for turning on "ON", the external noise 35 is generated by the N-channel transistor 24.
Is input to the GND line 6 via the external noise 35
Is below the GND level potential, the diode equivalent circuit 26 is not turned on, and the external noise 35 is P
It is not input to the Vcc line 7 via the channel transistor 23 and does not affect the Vcc line 7.

[0011]

Since the conventional semiconductor integrated circuit is configured as described above, it may be affected by external noise input to the Vcc line 7 via the external terminal 3 and the P-channel transistor 23. There is a high possibility that the power supply voltage level is affected and the internal circuit malfunctions. Especially, in the case of a semiconductor integrated circuit that performs a program operation such as a one-chip microcomputer, a counter, a register,
Furthermore, if the data in the memory is destroyed, there is the problem of a runaway.

The present invention has been made to solve the above-mentioned problems, and external noises that enter the power supply line for the data input / output unit that supplies power to the data input / output unit, especially the power supply for the data input / output unit, are provided. An object of the present invention is to obtain a semiconductor integrated circuit capable of effectively preventing malfunction of an internal circuit which may occur due to noise such as pulling down the power supply voltage of a line to the ground side.

[0013]

A semiconductor integrated circuit according to the present invention is arranged on the periphery of a semiconductor integrated circuit chip and supplies power to a central processing unit and a memory circuit of the semiconductor integrated circuit chip. A power line for the data input / output unit that branches from the line and supplies power to the data input / output unit,
A noise detection circuit that detects an external noise that enters from the data input / output unit to the data input / output unit power supply line on the terminal side of the data input / output unit power supply line and generates an interrupt signal; and the noise detection circuit, An interrupt processing unit that performs a predetermined interrupt process based on the generated interrupt signal is provided.

In the semiconductor integrated circuit according to the second aspect of the present invention, the external noise that enters from the data input / output unit to the data input / output unit power supply line is processed by the central processing unit at the end side of the data input / output unit power supply line. , A noise detection circuit for detecting with a threshold value set higher than threshold values of other circuit elements in an internal circuit such as a memory circuit.

According to a third aspect of the present invention, there is provided a semiconductor integrated circuit having a noise suppressing means for suppressing an external noise that intrudes from a data input / output section, or an arrangement configuration having improved noise resistance against the intrusion of the external noise. The power line is used to supply power to the noise detection circuit.

According to another aspect of the semiconductor integrated circuit of the present invention, the width of the external noise entering from the data input / output section to the data input / output section power supply line is identified on the terminal side of the data input / output section power supply line. A noise width determination circuit that outputs an external noise input signal indicating that the external noise is input to the noise detection circuit only for the input of the external noise that exceeds a predetermined width is provided.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below. Embodiment 1. FIG. 1 is a block diagram showing the configuration of the semiconductor integrated circuit according to the first embodiment. In FIG. 1, parts that are the same as or correspond to those in FIG. 6 are given the same reference numerals and description thereof is omitted. In the figure, 101 is V from the external terminal 3
It is a noise detection circuit for detecting the external noise 33 shown in FIG. 8 among the external noises input to the cc line. 1
Reference numeral 02 denotes a data input / output unit power supply line, which is a Vcc line 7 for supplying electric power to an internal circuit 9 such as a central processing unit or a storage circuit.
Branching off from the peripheral part on the chip of the microcomputer chip 1 as a power supply line of the interface device 4.
It is routed around. The layout configuration of the power supply line 102 for the data input / output unit on the microcomputer chip 1 has a characteristic that the interface device 4 exchanges data with the outside.
Since a plurality of peripheral circuits 9 are arranged in the upper peripheral portion so as to surround the peripheral circuit 9, they are routed so as to make one round around the periphery of the microcomputer chip 1. Further, the internal circuit 9 and the noise detection circuit 101 are arranged and wired so as not to pass around the microcomputer chip 1 within the Vcc power supply supplied to the inside of the microcomputer chip 1, and directly from a stable Vcc power supply which is not easily affected by noise. Power is supplied. Reference numeral 103 denotes a noise detection end (data input / output section) in which a data input / output section power supply line 102 wired around the microcomputer chip 1 makes one round around the microcomputer chip 1 and is input to the noise detection circuit 101. The end of the power supply line for use is shown, and the power supply line is close to the power supply position of the interface device 4.

FIG. 2 is a circuit diagram showing the configuration of the noise detection circuit. In the figure, reference numeral 120 denotes a NAND circuit that monitors the state of the data input / output unit power supply line 102. External noise 33 is input from the data input / output unit power supply line 102 via the noise detection terminal 103, and data input / output When the potential of the power supply line 102 for the parts becomes lower than the original Vcc voltage level, an'H 'level interrupt start signal is output. The NA that monitors the power supply line 102 for the data input / output unit
The input threshold level of the ND circuit 120 is set higher than the threshold levels of the circuit elements that form the internal circuit 9 so that it is possible to quickly detect that the potential of the data input / output unit power supply line 102 has dropped. 121 is a NAND circuit 120
Represents a signal line from which a signal c is output. Reference numeral 122 denotes the NAND circuit 12 only when the noise detection reset signal for initializing the noise detection circuit 101 is at the “H” level.
N for accepting and inverting the signal c output from 0
It is an AND circuit. Reference numeral 123 represents a signal line from which the signal e is output from the NAND circuit 122. NAND circuit 1
20 and the NAND circuit 122 form an RS flip-flop circuit, the signal line 131 side is the reset input side, and Vc
The c line 102 side is the set input side, and the signal line 123 side is the invert Q output side.

Reference numeral 124 represents a noise canceller for removing noise generated when the signal e output from the NAND circuit 122 changes. Reference numeral 125 is a signal line for outputting an interrupt start signal for generating an interrupt when the external noise 33 is input. Reference numeral 126 is an interrupt circuit (interrupt processing means), which starts the interrupt processing when the interrupt start signal falls, and outputs an interrupt end signal notifying that the interrupt processing has ended to the signal line 127 when the interrupt processing ends. Circuit.
Reference numeral 128 is an inverter circuit that inverts the interrupt end signal. 129 is a signal f from the inverter circuit 128
Is a signal line from which the output of the inverter circuit 128 is connected to one input terminal of the NOR circuit 130. Reference numeral 132 denotes a reset signal line to which a reset signal for initializing the microcomputer chip 1 is input, which is connected to one input terminal of the NOR circuit 130.

The NOR circuit 130 generates a noise detection reset signal, and when the interrupt processing by the interrupt circuit 126 is completed, the NOR circuit 130 is composed of NAND circuits 120 and 122.
This is a circuit for resetting the S flip-flop circuit. The noise detection reset signal is output to the signal line 131 when the reset signal is input from the reset signal line 132 or when the interrupt end signal is output,
This is a signal that initializes the noise detection circuit.

Next, the operation of the noise detection circuit 101 will be described with reference to the timing chart of FIG. In FIG. 3, a period 140 is a period during which the entire microcomputer chip 1 is initialized. At this time, the noise detection circuit 101 is also initialized. In this state, NAN
The signal e which is the output of the D circuit 122 is at the “H” level, NA
The signal c output from the ND circuit 120 is at the'L 'level. Further, the period 141 is a normal operation mode period of the microcomputer chip 1, and each signal of the noise detection circuit 101 is initialized until the external noise 33 is input to the data input / output unit power supply line 102. Holds the state of. 142 is an input threshold level on the input side connected to the data input / output unit power supply line 102 of the NAND circuit 120, and 143 is the external noise 33 input to the data input / output unit power supply line 102, and the interrupt start signal falls. Represents the interrupt processing period from when the interrupt completion signal of the “L” level is output.

In the initialized state, the external noise 33 is input to the power supply line 102 for the data input / output section provided around the microcomputer chip 1, and the NAND circuit 12 is connected.
Below the input threshold level 142 of 0, the NAND circuit 1
20 and the NAND circuit 122, the RS flip-flop is set, and the NAND circuit 120 outputs the signal line 1
An'H 'level signal c is output to 21. Also, after a little delay from this, the signal line 123 side, that is, the invert Q
An “L” level signal e is output from the output. As a result, the interrupt start signal is input to the interrupt circuit 126, and the interrupt circuit 126 starts interrupt processing.

In this case, it is assumed that the interrupt processing content is set by software, and the interrupt processing program operates during the period 143 to execute the interrupt processing.
When the operation of the interrupt processing is completed, the interrupt circuit 126
Outputs an'L 'level interrupt end signal from the signal line 127 to the NAND circuit 120 and the NAND circuit 12.
The RS flip-flop composed of 2 and 3 is reset again and returns to the initial state.

As described above, in this embodiment, the external noise input to the power supply inside the chip via the external terminal and the data output circuit, especially the external noise that pulls down the Vcc power supply voltage level to the ground side. Detection is performed by the input threshold level of the NAND circuit 120 set higher than the other threshold levels, and when such external noise is input, an interrupt is generated before the microcomputer chip 1 is affected and interrupt processing is performed. By executing this, malfunction of the microcomputer chip 1 is prevented. The Vcc line that supplies power to the noise detection circuit 101 of the microcomputer chip 1 is connected to a power source such as a central processing unit of the internal circuit 9 or a storage circuit, and a relatively large wiring capacitance (noise suppressing means) 13 is added. It is also considered that the external noise 33 that enters the internal circuit 9 of the microcomputer chip 1 and the noise detection circuit 101 via the Vcc line is bypassed to the GND line 6 by the wiring capacitance 13 and is blocked or delayed. On the other hand, since the noise detection end 103 is close to the power supply position of the interface device 4 and the wiring capacitance of the data input / output unit power supply line is small, when such external noise is input. It becomes possible to generate an interrupt before the internal circuit 9 of the microcomputer chip 1 is affected, To prevent malfunction of the internal circuit 9 of the microcomputer chip 1 by executing the interrupt processing.

Embodiment 2 Although the wiring capacitance 13 is inevitably generated in the configuration of the microcomputer chip 1 in the first embodiment, the capacitive element (noise) that is positively added from the viewpoint of the design of the microcomputer chip. Suppression means).

Embodiment 3 FIG. FIG. 4 is a circuit diagram showing configurations of the noise detection circuit and the noise width determination circuit of the semiconductor integrated circuit according to the third embodiment. In FIG. 4, FIG.
The same or corresponding parts are designated by the same reference numerals and the description thereof will be omitted. The configuration of the semiconductor integrated circuit shown in FIG. 1 is also applied to this embodiment. In FIG. 4, 2
A noise width determination circuit 00 detects the width of the external noise 33 input to the data input / output unit power supply line 102. Two
Reference numeral 01 is a delay circuit for delaying external noise 33 entering from the data input / output unit power supply line 102, and 202 is a delay circuit 20.
A signal line from which the signal g of 1 to'L 'level is output, 20
3 is “H” during the period when the external noise 33 input from the data input / output power supply line 102 and the signal g are both present.
It is a NOR circuit that outputs a level signal h. Reference numeral 204 is a signal line through which the signal h is output from the NOR circuit 203, and 20
Reference numeral 5 is an inverter circuit that inverts the signal h, and 206 is a signal line that supplies the signal output from the inverter circuit 205 to one input terminal of the NAND circuit 120 included in the noise detection circuit 101.

FIG. 5 shows a timing chart of signal waveforms of respective parts in the noise width determination circuit. In the figure,
33a is a wide external noise, and 33b is a narrow external noise. 222 represents an input threshold level of the delay circuit 201 and the NOR circuit 203. t1 represents the delay time of the delay circuit 201.

Next, the operation will be described with reference to the timing chart of FIG. The operations of the noise detection circuit 101, when an interrupt is generated, when an interrupt is processed, when an interrupt is completed, and when the microcomputer chip 1 is initialized are the same as those in the first embodiment, and the description thereof is omitted.

First, the case where a wide external noise 33a is input to the data input / output unit power supply line 102 will be described. When the external noise 33a that is lower than the input threshold level of the delay circuit 201 and the input threshold level of the NOR circuit 203 is input to the power supply line 102 for the data input / output unit wired around the microcomputer chip 1, the data of the NOR circuit 203 is input. The external noise 33a is detected on the input side to which the input / output power supply line 102 is directly connected. Since the signal g output from the delay circuit 201 is still in the “H” level state at this time, the signal h output from the NOR circuit 203 maintains the “L” level. The delay circuit 201 outputs a signal “L” level g after the delay time t1 elapses. At this time, the state of the data input / output power supply line 102 falls below the input threshold level of the NOR circuit 203 due to the external noise 33a. Then, the signal h which is the output of the NOR circuit 203 becomes the “H” level, and the inverter circuit 20
The signal h is inverted by 5 and input to the NAND circuit 120 as an'L 'level signal. As a result, the noise detection circuit 101 outputs an “L” level interrupt start signal to the interrupt circuit 126 and the interrupt circuit 126.
Starts interrupt processing. The operation from the start of the interrupt processing to the end of the interrupt processing is the same as in the first embodiment.

Next, the case where a narrow external noise 33b is input will be described. Power supply line 102 for data input / output section, which is provided around the microcomputer chip 1.
The input threshold level of the delay circuit 201 and the NOR circuit 203
When the noise 33b lower than the input threshold level of is input, first, the power supply line 1 for the data input / output unit of the NOR circuit 203 is input.
The input side connected to 02 detects this external noise 33b. On the other hand, the output of the delay circuit 201 maintains the'H 'level at this time. Therefore, the output of the NOR circuit 203 is at the “L” level. The delay circuit 201 outputs the signal g at the'L 'level after the delay time t1, but when the width of the external noise 33b is narrow, the external noise 33b disappears before the signal g becomes the'L' level. And the signal h is'L '
Since the level remains unchanged and the input of the NAND circuit 120 does not change, no interrupt occurs.

Therefore, in this embodiment, of the external noise input to the power supply line 102 for the data input / output section in the microcomputer chip 1 via the external terminal and the data output circuit, the width is narrow and the internal noise is small. An interrupt is not generated for external noise that has a small effect on the circuit, and an interrupt is generated for external noise that is wide and has a large effect on the internal circuit, and an interrupt is generated according to the size of the external noise. Flexible processing is performed according to the size of the width of external noise, such as processing or not performing interrupt processing.

Embodiment 4 FIG. In the embodiment described above, the NAND circuit 1 set higher than the other threshold level (Vcc / 2) in the noise detection circuit 101.
According to the input threshold level of 20, the external noise 33 that pulls the Vcc power supply voltage level to the ground side is detected before other circuits are affected.
By setting the input threshold level of the D circuit 120 to be slightly higher than the Vcc voltage level, the input of the external noise 32 shown in FIG. 8A is interrupted before the internal circuit 9 of the microcomputer chip 1 is affected. Is generated and the interrupt process is executed, it is possible to prevent the malfunction of the microcomputer chip 1.

[0033]

As described above, according to the first aspect of the invention, the data input / output unit is branched from the power supply line arranged on the periphery of the semiconductor integrated circuit chip and supplying power to the central processing unit and the memory circuit. On the terminal side of the power supply line for the data input / output unit that supplies power to the power supply line for the data input / output unit, the noise detection circuit detects an external noise that enters the power supply line for the data input / output unit, Since the interrupt signal is generated and the interrupt process is performed when the external noise is detected, it is possible to effectively prevent the malfunction that may be caused by the noise input to the power supply line for the data input / output unit. .

According to the second aspect of the present invention, the external noise that enters from the data input / output unit to the data input / output unit power supply line is
Since the central processing unit, the noise detection circuit for detecting by the threshold value set higher than the threshold value of other circuit elements in the storage circuit, etc., is provided on the terminal side of the power supply line for the data input / output unit, the central processing The noise detection circuit can detect the external noise before the external noise affects the device or the memory circuit, and the malfunction that may be caused by the noise input to the power supply line for the data input / output unit is effective. There is an effect that can be prevented.

According to the third aspect of the present invention, there is provided a power supply line having a noise suppressing means for suppressing an external noise that intrudes from the data input / output unit, or an arrangement configuration in which noise resistance against the intrusion of the external noise is improved. Since it is configured to be used as a power supply line that supplies power to the noise detection circuit,
It is possible to suppress the influence of external noise that intrudes from the data input / output unit with respect to the noise detection circuit, prevent malfunction of the noise detection circuit due to the external noise, and use the noise detection circuit for intrusion of the external noise. There is an effect that noise can be detected with high reliability, and malfunction that may occur due to noise input to the data input / output unit power supply line can be effectively prevented.

According to the fourth aspect of the present invention, the width of the external noise on the terminal side of the power supply line for the data input / output unit is set to the external noise that invades the power supply line for the data input / output unit from the data input / output unit. Since it is configured to include a noise width determination circuit that outputs an external noise input signal indicating that external noise has been input only to the input of the external noise that has been identified and exceeds a predetermined width, The interrupt processing can be selectively activated only when external noise that has a large influence on the central processing unit and the memory circuit is invaded. The probability of occurrence of operation interruption is reduced to prevent a drop in the operating efficiency of the original operation of the semiconductor integrated circuit, and at the same time, it has a large impact on external sources. There is an effect that can be avoided surely malfunction for's.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a noise detection circuit of the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing an operation of the noise detection circuit of the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a noise width determination circuit of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 5 is a timing chart showing the operation of the noise width determination circuit of the semiconductor integrated circuit according to the third embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional semiconductor integrated circuit.

FIG. 7 is a circuit diagram showing a configuration of an output circuit of a conventional interface device for a semiconductor integrated circuit.

FIG. 8 is a waveform diagram showing the influence of various external noises on the Vcc power supply.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 microcomputer chip (chip), 4 interface device (data input / output unit), 13 wiring capacitance (noise suppressing means), 101 noise detection circuit, 102
Data input / output unit power supply line, 103 noise detection end (data input / output unit power supply line end), 126 interrupt circuit (interrupt processing unit), 200 noise width determination circuit.

Claims (4)

[Claims] 1. A central processing unit for performing data processing, a data input / output unit such as an I / O port or an interface unit for exchanging data with an external circuit, and a storage circuit for storing data. In a semiconductor integrated circuit having the central processing unit, the data input / output unit, the storage circuit, etc. on one chip, power is supplied to the central processing unit and the storage circuit arranged around the chip. A power supply line for a data input / output unit that branches from a power supply line and supplies power to the data input / output unit, and a power supply for the data input / output unit from the data input / output unit at the terminal side of the power supply line for the data input / output unit A noise detection circuit that detects external noise that invades the line and outputs an interrupt signal, and a predetermined interrupt by the interrupt signal output from the noise detection circuit A semiconductor integrated circuit comprising: an interrupt processing unit that performs processing. 2. The noise detection circuit prevents external noise from entering the power supply line for the data input / output unit from the data input / output unit on the end side of the power supply line for the data input / output unit by the central processing unit and the central processing unit. 2. The semiconductor integrated circuit according to claim 1, wherein detection is performed by a threshold value set higher than threshold values of other circuit elements in the memory circuit or the like. 3. The power supply line for supplying power to the noise detection circuit has noise suppression means for suppressing external noise that intrudes from the data input / output unit, or improves noise resistance against intrusion of the external noise. 3. The semiconductor integrated circuit according to claim 2, wherein the power supply line has the above-mentioned arrangement configuration. 4. The width of the external noise is discriminated at the terminal side of the power line for the data input / output unit with respect to the external noise penetrating from the data input / output unit to the power line for the data input / output unit, and a predetermined width is determined. The noise width determination circuit for outputting an external noise input signal indicating that the external noise is input to the noise detection circuit only for the input of the external noise exceeding the width is provided. 4. The semiconductor integrated circuit according to claim 3,