JP4259354B2 - Control device with system reset discrimination function - Google Patents

Description

  The present invention relates to a control device equipped with a system reset function, and in particular, determines whether the system reset is caused by a power-on reset or a warm reset, thereby improving the reliability of the device. The present invention relates to a control device with a system reset discrimination function.

  FIG. 4 is a schematic configuration diagram showing a control device with a system reset function. In this device, reference numeral 1 is a power supply monitoring IC (reset IC) composed of CMOS or the like, and this power supply monitoring IC 1 is a control device (control). Equipment).

  A reset switch 2 and a capacitor 3 are connected to the power monitoring IC 1, and a power-on reset signal a (voltage monitoring function when the power is turned on etc.) when the power is turned on or when the reset switch 2 is pushed down (when the switch is closed). Is generated).

  The power-on reset signal a is supplied to one input terminal of the OR circuit 4, and the other input terminal is supplied with a warm reset signal b (soft control / reset generated upon error).

  The warm reset signal b is generally controlled and output from a register or the like created in an FPGA 5 (Field Programmable Gate Array) made of an LSI that can be programmed. As a warm reset factor, a software reset triggered by software, a reset when a watchdog timer monitoring error occurs, or the like can be considered.

The OR circuit 4 logically sums the power-on reset signal a and the warm reset signal b to generate a system reset signal c at the output. This system reset signal c is supplied to the FPGA 5, CPU 6, and various LSIs 7, and is used as a signal for initializing them.
Japanese Patent Laid-Open No. 06-348370 Japanese Patent Laid-Open No. 10-027041 JP 2003-032089 A

  In the above-described control device with a system reset function, when a reset occurs, whether the reset is a power-on reset (power supply itself is turned on / off or restarted by turning on / off the reset switch), or a warm reset is generated (software control) There is no way to determine whether the error occurred or rebooted due to an error. Also, the same reboot may be due to an error or the like, or it may have occurred artificially.

  Since it has not been possible to determine the occurrence of reset as described above, there is a problem in system construction, and the reliability of the system cannot be improved.

  The present invention has been made in view of the above circumstances, and as a reset when an abnormality occurs in the control device or as an abnormality determination standard, it is possible to clearly recognize the reset type at the time of occurrence of the reset and improve the reliability of the system construction. It is an object of the present invention to provide a control device with a system reset discrimination function capable of achieving the above.

In order to achieve the above object, the present invention provides a power monitoring unit that generates a power-on reset signal when power is turned on or a reset switch is turned on, and a power-on output from the power monitoring unit. A reset discrimination function having a logical sum of a reset signal and a warm reset signal output from a programmable integrated circuit device, generating a system reset signal at the output, and initializing a CPU and various integrated circuit devices The power-on reset signal output from the power supply monitoring means is supplied, the power-on reset signal is sampled by a clock signal , and a status latch signal is obtained at the output, and the sampling means is latched by the status latch signal output, the Tsu power-on reset signal to an output terminal of said power supply monitoring means by Chi operation recognizes that it has generated, the output if the power-on reset signal to "1", and a logic means for outputting an output "0" if a warm reset signal It is characterized by.

  The second invention is characterized in that a delay generation circuit means for obtaining a status latch signal from a power-on reset signal is provided in place of the sampling means.

  As described above, according to the present invention, when a reset occurs, it is possible to determine whether a power-on reset or a warm reset has occurred. As a criterion for judgment, there is an advantage that a reset system when a reset occurs can be clearly recognized and a highly reliable system can be constructed.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram showing a first embodiment of the present invention. The same parts as those in FIG. 4 are denoted by the same reference numerals.

  In FIG. 1, reference numeral 11 denotes a crystal oscillator, and a clock signal d transmitted from the crystal oscillator 11 is supplied from two flip-flops FF1 and FF2 to a clock terminal CLK of a two-stage sampling circuit 12 constituting sampling means. .

  The two-stage sampling circuit 12 is configured so that the power-on reset signal a output from the power supply monitoring IC 1 constituting the power supply monitoring means is supplied to the input terminal D of the first-stage flip-flop FF1. The reset signal a is sampled by the clock signal d from the crystal oscillator 11.

  The two-stage sampling circuit 12 is configured so that the output terminal Q of the first-stage flip-flop FF1 and the input terminal D of the second-stage flip-flop FF2 are connected.

  The sampling circuit 12 is configured to perform sampling at two or more stages in order to prevent chattering, and the signal delayed by clock sampling from the normal power-on reset signal a is the second stage of the two-stage sampling circuit 12. Is generated at the output terminal Q of the flip-flop FF2.

  This generated signal is a status latch signal f, and this status latch signal f is supplied from the flip-flop FF3 to the clock terminal CLK of the power-on reset status register 13 constituting the logic means.

  14 is an OR circuit. A power-on reset signal a is supplied to one input terminal of the OR circuit 14, and a power-on reset status clear signal e which can be controlled by an internal register of the FPGA 5 is supplied to the other terminal. Is done.

  The output signal of the OR circuit 14 is supplied to the reset terminal R of the power-on reset status register 13.

  The power-on reset status register 13 is latched by a status latch signal f which is an output signal of the two-stage sampling circuit 12, and this latching operation indicates that the power-on reset signal a is generated at the output terminal of the power supply monitoring IC 1. Be recognized.

  The power-on reset status register (hereinafter referred to as FF3) 13 is cleared during the period when the power-on reset signal a is generated and by the power-on reset status clear signal e.

  Here, “1” and “0” of FF3 will be described. When FF3 = 1, reset indicates “power-on reset”, and when FF3 = 0, reset indicates “warm reset”.

  The subsequent operation at power-on reset is as follows. During the power-on reset, FF3 is forcibly set to “0” by the power-on reset signal a.

  After the power-on reset (power-on reset signal a = 1), the status latch signal f changes from “0” to “1” after two clock signals, and FF3 = 1 at this timing. Thereafter, unless a power-on reset occurs again, FF3 = 1 in terms of circuit.

  During the operation as described above, the CPU 6 receives the system reset signal c, and after resetting the system, captures the state of FF3 in order to determine whether it is a power-on reset or a warm reset. If the value is “0”, it is determined as a warm reset, and if the value is “1”, it is determined as a power-on reset.

  If the value of FF3 is “1”, the CPU 6 determines that the power-on reset signal a of the FPGA 5 is valid (set to L level) and forcibly sets the value of FF3 to “0”. To do. Once FF3 is set to “0”, it holds “0” (as long as there is no power-on reset).

  By configuring as in the first embodiment, it is possible to determine whether a power-on reset signal or a warm reset signal has occurred when a reset occurs. Such a determination becomes possible, and as a reset or abnormality determination standard when an abnormality occurs in the control device, in the first embodiment, the reset type when the reset occurs can be clearly recognized, and a highly reliable system is provided. It can be constructed.

  FIG. 2 is an operation time chart of the two-stage sampling circuit 12 of the first embodiment.

  In the first embodiment, the two-stage sampling circuit 12 and the power-on reset status register 13 have been described as external circuits. However, both circuits may be configured to be realized inside a programmable device such as the FPGA 5. .

  FIG. 3 is a schematic configuration diagram showing a second embodiment of the present invention. A configuration point different from the first embodiment is configured by a delay generation circuit 21 including a delay line / multi-stage buffer instead of the two-stage sampling circuit 12. That is.

  In FIG. 3, the delay generation circuit means 21 delays the power-on reset signal a by inserting a delay line or a multistage buffer, and generates a status latch signal f at the output.

  By this status latch signal f, the power-on reset status register 13 is latched, so that it can be confirmed that the power-on reset signal a is generated.

  As in the first embodiment, the power-on reset status register 13 can be cleared during the period when the power-on reset signal a is generated and by the power-on reset status clear signal e. Since other operations and effects are the same as those of the first embodiment, description thereof is omitted.

BRIEF DESCRIPTION OF THE DRAWINGS The schematic block diagram which shows 1st Embodiment of this invention. The time chart of operation | movement of the two-stage sampling circuit of a 1st form. The schematic block diagram which shows 2nd Embodiment of this invention. The schematic block diagram which shows the conventional circuit.

Explanation of symbols

1 ... Voltage monitoring IC
2 ... Reset switch 3 ... Capacitor 4, 14 ... OR circuit 5 ... FPGA
6 ... CPU
7 ... Various LSI
DESCRIPTION OF SYMBOLS 11 ... Crystal oscillator 12 ... Two-stage sampling circuit 13 ... Power-on reset status register 21 ... Delay generation circuit means

Claims (2)

Power monitoring means for generating a power-on reset signal when the power is turned on or the reset switch is turned on;
A system reset signal is generated from the logical sum of the power-on reset signal output from the power supply monitoring means and the warm reset signal output from the programmable integrated circuit device, and the CPU and various integrated circuit devices are initialized. In a control device having a reset discrimination function including an OR circuit,
The power-on reset signal output from the power supply monitoring means is supplied, the power-on reset signal is sampled by a clock signal , and sampling means for obtaining a status latch signal at the output;
It is latched by the status latch signal output from the sampling means, and it recognizes that a power-on reset signal is generated at the output terminal of the power supply monitoring means by this latching operation. A control device with a system reset discriminating function, comprising a logic means for outputting an output "0" if it is a reset signal . 2. The control device with a system reset discrimination function according to claim 1, wherein a delay generation circuit means for obtaining a status latch signal from a power-on reset signal is provided in place of the sampling means.

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