JPH0969756A - Filter operation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the filter operation of data different of the number of samples in one frame without changing the control systems of other digital signal processors by changing only the address control of a filter operation part. SOLUTION: When data from a frame memory 106 is stored in a buffer 101 having the area of m+(i-j) words where (m) is the number of taps of the filter and (i-j) is the difference of the number of samples with respect to data where the number of samples in one frame is different and is (i) or (j) (i>j), the address is returned by (i-j) at each time of the frame change for the purpose of supplying a lack of (i-j) data from data in the preceding frame, and the address is skipped by (i-j)+1 to remove (i-j) data unnecessary for filter operation, and (m) data from this position are successively outputted to a filter operation circuit 102, and product sum operation between data and the coefficient from a filter coefficient memory 104 is repeated (i) times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a filter arithmetic unit for performing a filter arithmetic operation on data having a different number of samples in one frame in digital signal processing.

[0002]

2. Description of the Related Art F which is often used in digital signal processing
In the IR (Finite Impulse Response) filter calculation, the audio data after AD (analog-digital) conversion stored in the frame memory is read into the FIR buffer one sample at a time, and the FIR buffer and the memory storing the filter coefficient are read from the memory. The data necessary for the calculation and the filter coefficient are read, and the filter calculation is performed by repeating the product-sum calculation.

The calculation result is written in the frame memory. Normally, an FIR buffer area is formed on the frame memory. In order to efficiently perform the FIR filter operation, an area for the number of taps of the FIR filter is secured as an FIR buffer in the frame memory, and the newest audio data is overwritten on the oldest data in the area.
By cyclically addressing the inside of the IR buffer, a ring buffer is formed so as to transfer data to the FIR filter arithmetic circuit.

A non-volatile memory or the like is used as the frame memory. Since the unit of erasure of non-volatile memory is block by block, it is necessary to set the frame length so that the area in the erase block can be used efficiently so that one frame of data is not stored beyond the erase block. There is a nature.

An example of the conventional FIR filter calculation and cyclic addressing of the FIR buffer will be described below with reference to the drawings.

FIG. 6 is a schematic diagram of the FIR filter operation unit in the digital signal processing device. In FIG.
Reference numeral 601 denotes an FIR buffer that stores audio data for FIR filter calculation. In the FIR buffer 601, data is sequentially read from a frame memory in which voice data obtained by AD conversion for each frame is stored.
It is cyclically addressed by the address generation circuit 602 so that the latest data is overwritten on the oldest data. Reference numeral 603 denotes an FIR filter arithmetic circuit which receives as input the data read from the FIR buffer 601 and the filter coefficient read from the memory storing the filter coefficient. The number of taps of the FIR filter circuit 603 is m
Then, the FIR buffer 601 has a storage area of m words.

The operation of the FIR filter operation unit in the digital signal processing device configured as described above will be described below.

FIG. 7 shows the flow of data updating by cyclic addressing of the FIR buffer during FIR filter calculation. For the sake of explanation, here, the number of taps of the FIR filter is 12, and the area of the FIR buffer is 12
It is a word.

FIG. 7A shows a part of the data on the frame memory. The data of each sample read from the frame memory is cyclically addressed by the address generation circuit for the FIR buffer so that the oldest data on the FIR buffer is overwritten.
It is stored in sequence. Assuming that the data in the FIR buffer at time tn is (b) in FIG. 7, the data tn + 1 next to tn on the frame memory is read into the FIR buffer at the next time tn + 1 and is the oldest on the FIR buffer. The data tn-11 is overwritten and the result becomes as shown in FIG.
Thereafter, similarly, cyclic addressing is performed so that new data read from the frame memory is overwritten on the oldest data in the FIR buffer.

The FIR filter operation at time tn is
The data on the FIR buffer is in the order of oldness (tn-11, tn-10, ...,
tn-1, tn) or the new order (tn, tn-1, ..., tn-
10, tn-11) are sequentially output, and the coefficient output from the memory in which the filter coefficient is stored is repeatedly executed 12 times by the FIR filter operation circuit to execute it.

As an example of the FIR filter calculation, the case of continuous processing of data in which the number of samples in one frame is i is shown. Here, it is assumed that the first frame processes data of i samples from D0 to Di-1, and the next frame processes data of i samples from S0 to Si-1. The number of taps of the FIR filter is m, and the FIR buffer is m words.
The transition of data in the FIR buffer is shown in FIG. FIR
The filter coefficients are sequentially set to a0, a from the coefficient of the new data.
If 1, ..., Am-2, am-1, the FIR filter calculation result is as shown in FIG.

[0012]

However, in the FIR filter arithmetic processing in the digital signal processing as described above, the number of samples in one frame is constant, and control for signal processing is performed according to the number of samples to be processed. Is fixed.

In a non-volatile memory or the like used as a frame memory, the erase unit is block by block.
There is a need to make the frame length so that the area in the erase block can be used efficiently so that one frame of data is not stored beyond the erase block. When the non-volatile memory used as the frame memory is changed, in order to use the area in the erase block of the non-volatile memory efficiently, according to the non-volatile memory, etc.,
It is necessary to change the frame length. However, FIR
Since the filter arithmetic processing requires continuous time-series data, when the FIR filter arithmetic processing is performed on data having different sample numbers in one frame, all control systems of the digital signal processing device are changed. It had a problem that it had to be done.

In view of the above problems, the present invention merely controls the address control of the FIR filter arithmetic unit for data having different numbers of samples in one frame in digital signal processing, and controls other digital signal processing devices. It is an object of the present invention to provide a filter calculation device that enables FIR filter calculation processing without changing.

[0015]

In order to solve the above-mentioned problems, the present invention provides a frame memory for storing data in units of one frame, an address generating circuit for the frame memory, and data in the frame memory. FIR buffer for reading out each sample and temporarily storing it, and the FIR
An address generation circuit capable of cyclic addressing and interlace addressing in a buffer, a memory storing filter coefficients, an address generation circuit for the filter coefficient memory, data from the FIR buffer and the filter coefficient memory It is composed of an FIR filter arithmetic circuit which inputs a filter coefficient, and changes control of other digital signal processing devices only by changing addressing control of the FIR buffer with respect to data having different number of samples in one frame. Without FI
It is characterized in that R filter calculation processing is executed.

[0016]

In performing the FIR filter calculation process, one frame of data is converted from the number of i samples to the number of j samples (i>
j), and when the effective data decreases, i
-J (i> j) The address of the FIR buffer is returned (i-j) every time the frame is changed so that the data of the sample number is replenished from the data of the previous frame, and from that position, the same as when the sample number is i By performing the FIR filter arithmetic processing by executing the cyclic addressing, 1 frame is processed as in the case of processing the data of i samples.
Since the frame can process data of the number of j samples, it is not necessary to change the control of the digital signal processing device other than the FIR filter arithmetic control according to the number of samples, and the FIR filter arithmetic control to be changed is also the FIR filter arithmetic control.
Since only the addressing control of the buffer is changed,
The control change of the digital signal processing device due to the change in the number of samples is simplified.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A filter arithmetic device for realizing an FIR filter arithmetic operation on data having a different number of samples per frame according to the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of the FIR filter operation section of the digital signal processing apparatus according to the first embodiment of the present invention. In FIG. 1, reference numeral 106 denotes a frame memory 110 for storing data in 1-frame units.
Address generation circuit 1 of No. 07 addresses. Reference numeral 101 is an FIR buffer for reading out data from the frame memory 106 one by one and storing it, and is cyclically and skip-addressed by the address generation circuit 2 of 103. Reference numeral 104 is a filter coefficient memory in which filter coefficients are stored, and is addressed by the address generating circuit 3 of 105 so that appropriate coefficients are output. Reference numeral 102 denotes a product-sum operation circuit for performing an FIR filter operation using the data from the FIR buffer 101 and the filter coefficient from the filter coefficient memory 104 as inputs. The filter calculation unit 109 is controlled by the filter calculation control unit 108.

The operation of the FIR filter operation unit configured as described above will be described below with reference to FIGS. 1, 2, 3 and 4.

2, 3 and 4 show the processing of FIG. 1 in the first embodiment. First, in FIG. 2, time t
3 shows the flow of FIR buffer data and cyclic addressing at n. FIR buffer 201
Has an area of m + (i−j) words so that the data of which the number of samples in one frame is i and j (i> j) can be executed by the FIR filter operation circuit 203 of m taps.
At the time tn, when the latest data tn is stored in the FIR buffer and the data of i samples is processed, the data (i-j) unnecessary for the m-tap FIR filter operation is excluded. Thus, addressing is performed so that the address is skipped by (i-j) +1 and m pieces of data are sequentially output from that position. FI at the next time tn + 1
Addressing is performed so that new data is overwritten on tn- (m + (ij) -1), which is the oldest data in the R buffer, and again removes (i-j) data unnecessary for FIR filter operation. The address is addressed such that the address is skipped by (i-j) +1 and m pieces of data are sequentially output from that position. After that, in the same manner, the address is generated by the address generation circuit 202 so that the FIR buffer is cyclically addressed, and the FIR filter operation is repeated i times.

When performing the FIR filter operation on the data of the number of j samples, the operation is realized by the same control as the case of performing the FIR filter operation on the data of continuous time samples of the number of i samples every time the frame changes. First, the address is returned by (i-j) so that the (i-j) number of missing data is replenished from the previous frame, and after the data is stored, the (i-j) +1 address is skipped, and from that position m
Addressing is performed so that each piece of data is sequentially output.
After that, in the same manner as when the data of the number of i samples is calculated, after the data is stored, the (i−j) +1 address is skipped and the address generation circuit of 202 outputs m data sequentially from that position. Generate an address.

At this time, the data in the frame memory is updated so that the last (i-j) pieces of data of the previous frame are read into the FIR buffer at the beginning of the next frame.
That is, the data of j samples per frame is FIR
When the filter operation is performed, the same (i-j) pieces of data in the FIR buffer to be updated are overwritten with the same data stored in the address. One frame has i samples (D0, D1, ..., Di-2, Di-1) and j samples
FIG. 3 shows the transition of the data in the FIR buffer when the data of (S0, S1, ..., Sj-2, Sj-1) are continuously calculated. The FIR filter calculation result at this time is shown in FIG.

As described above, data having different numbers of samples in one frame can be subjected to the filter operation only by changing the address control of the filter operation unit without changing the control system of other digital signal processing devices. be able to.

In this embodiment, the data transfer from the FIR buffer to the filter arithmetic circuit is performed sequentially from the oldest data, but the addressing of the FIR buffer and the arrangement of the coefficients on the memory in which the coefficients are stored or By changing the addressing, the data can be sequentially transferred from the new data to the filter calculation circuit, and the data of different sample numbers can be filtered.

[0025]

As described above, according to the present invention, the difference (i−j) between the filter tap number m and the sample number is set for different data in which the number of samples in one frame is i, j (i> j). )
When a buffer having an area of m + (i−j) words that is the sum of
When the data from the frame memory is stored, in order to replenish the deficient (i-j) data from the last (i-j) data of the previous frame, the address is changed by (i -J) return, and thereafter, as in the case of performing the filter operation on the data of i samples, the address is set to (i
-J) +1 interlacing, and the address generating circuit performs cyclic and interlaced addressing so that data corresponding to the number of filter taps m is sequentially output to the filter arithmetic circuit from that position.

In the filter operation circuit, the data from the buffer and the coefficient from the filter coefficient memory are input, and the sum of products operation is repeated i times in the same manner as when the data of i samples in one frame is calculated. It is possible to realize a filter operation of data whose frame is j samples.

Further, only by changing the address control of the filter calculation unit, it is possible to perform the filter calculation of the data in which the number of samples of one frame is different, without changing the control system of the other digital signal device. Even if the frame length of one frame, that is, the number of samples is changed due to the change of the non-volatile memory or the like used as, the control of the digital signal processing device can be easily changed.

[Brief description of drawings]

FIG. 1 is a block diagram of a configuration of a filter calculation device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating cyclic addressing in an FIR buffer according to the same embodiment.

FIG. 3 is a schematic diagram of data transition in the FIR buffer when the number of samples in one frame is different in the embodiment of the present invention.

FIG. 4 is a diagram showing a result of FIR filter calculation of data having different number of samples of one frame in the embodiment of the present invention.

FIG. 5 is a block diagram of an address generation circuit of the present invention.

FIG. 6 is a diagram for explaining cyclic addressing in a conventional FIR buffer.

FIG. 7 is a diagram illustrating data transfer from a conventional frame memory to an FIR buffer.

FIG. 8 is a schematic diagram of data transition in the FIR buffer in the conventional method.

FIG. 9: FIR data with the same number of samples in one frame
Figure showing the result of filter operation

[Explanation of symbols]

101, 201, 601 FIR buffer 102, 203, 603 FIR filter arithmetic circuit 103, 202, 602 FIR buffer address generation circuit 104 Filter coefficient memory 105 Filter coefficient memory address generation circuit 106 Frame memory 107 Frame memory address generation circuit 108 Filter operation control unit 109 Filter operation unit 110 Data for each frame 501 Start address setting circuit 502 Address movement width setting circuit 503 Adders 504 and 507 Selector circuit 505 Address register 506 Pointer address holding circuit

Claims (4)

[Claims] 1. A frame memory that stores data in units of one frame, a first address generation circuit that arbitrarily generates an address for the frame memory and outputs the address to the frame memory, and a data from the frame memory. A buffer for inputting and temporarily storing, a second address generating circuit for generating an address so as to perform addressing and skipping addressing in the buffer and outputting the address to the buffer, and a buffer for storing a filter coefficient A filter coefficient memory and an address for the filter coefficient memory are arbitrarily generated,
A third address generating circuit for outputting to the filter coefficient memory, a filter arithmetic circuit for inputting the data output from the buffer and the filter coefficient output from the filter coefficient memory, performing a sum of products operation, and outputting the result. A filter operation device comprising: 2. The number of samples in one frame for which arithmetic processing is performed is i and j (i> j), and the number of taps of the filter is m.
2. The filter operation device according to claim 1, wherein the buffer area is m + (i-j) words. 3. In the writing and reading position designation processing of the data storage device, a repetitive calculation is performed according to a start address setting input which is the first input data and an address movement value setting input which is the second input data. Is an address generating circuit for generating an arbitrary address on a data storage device by executing a start address setting for arbitrarily outputting a start address N0 according to a start address control signal as the first input data. Section, an address movement value setting section for arbitrarily outputting an address movement value M including a negative number as the second input data according to an address movement value control signal, and the first input data N0 as an initial value. , The second input data M is repeatedly added, and the operation result Nn + 1 = Nn
An adder for updating the address by outputting + M, a first selector for selecting the output from the start address setting unit and the adder according to a first selector control signal, and a pointer address By providing a plurality of registers for holding according to the control signal, a pointer address holding unit for storing and holding as a pointer address, and according to a second selector control signal, the pointer address holding unit and the first A second selector that selects an output from the selector; and an address register that stores and holds the output selected by the second selector circuit and outputs the address as the address of the data storage device and the input Nn of the adder. An address generation circuit characterized by being provided. 4. In the writing and reading position designation processing of the data storage device, according to the address movement value control signal,
Address movement value setting unit that arbitrarily outputs the y-bit address movement value, y-bit input adder that updates the address by executing repeated operations, and reset that stores and holds the output of the adder An address extension unit having a plurality of registers having inputs, arbitrarily setting an upper address value for address extension, and outputting as an x + y-bit address, an address register for storing and holding an x + y-bit address, x + y An address generation circuit comprising: a branch unit for outputting only the lower y bits of a bit address as an input of the adder, and updating a plurality of addresses in one operation.