JPH0969688A - Multilayered circuit board - Google Patents
Multilayered circuit boardInfo
- Publication number
- JPH0969688A JPH0969688A JP22412795A JP22412795A JPH0969688A JP H0969688 A JPH0969688 A JP H0969688A JP 22412795 A JP22412795 A JP 22412795A JP 22412795 A JP22412795 A JP 22412795A JP H0969688 A JPH0969688 A JP H0969688A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- via hole
- group
- insulating film
- interconnections
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、複数の配線群を絶
縁膜を介して積層させて成る多層配線基板の改良に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a multilayer wiring board in which a plurality of wiring groups are laminated with an insulating film interposed therebetween.
【0002】[0002]
【従来の技術】従来の多層配線基板は、例えば、図3
(a)(b)に示す如く、ガラスやセラミック等から成
る基板21上に、複数の配線22から成る第1配線群と
複数の配線24から成る第2配線群とを絶縁膜23を介
して被着させるとともに、前記絶縁膜23の所定位置、
厚み方向に径0.1mm 〜0.25mmのビアホール23aを設
け、このビアホール23aを介して前記配線22及び配
線24を電気的に接続させた構造を有している。2. Description of the Related Art A conventional multilayer wiring board is shown in FIG.
As shown in (a) and (b), a first wiring group composed of a plurality of wirings 22 and a second wiring group composed of a plurality of wirings 24 are provided on a substrate 21 made of glass, ceramics or the like with an insulating film 23 interposed therebetween. While being deposited, a predetermined position of the insulating film 23,
A via hole 23a having a diameter of 0.1 mm to 0.25 mm is provided in the thickness direction, and the wiring 22 and the wiring 24 are electrically connected through the via hole 23a.
【0003】尚、前記絶縁膜23の材料としては、例え
ば、感光性エポキシ樹脂等の感光性樹脂等が知られてお
り、この感光性エポキシ樹脂を用いる場合は、最初に配
線22が被着された基板21上に、有機溶剤等を添加混
合して液状になした感光性エポキシ樹脂をスピンコート
法やロールコータ法等によって所定厚みに塗布し、次に
前記液状の感光性エポキシ樹脂に対して露光用のマスク
を通して紫外線を照射し、該照射した部分を光硬化させ
るとともに、光硬化されなかった部分をアルカリ系の現
像液で除去することによりビアホール23aを有した絶
縁膜23が形成される。この場合、絶縁膜23上に別
途、ビアホール23aを形成するためのフォトレジスト
を被着させたり、或いは、ドリル等を用いて絶縁膜23
に孔開け加工を施したりする必要がないことから、多層
配線基板の製造工程が簡略化される利点がある。As a material of the insulating film 23, for example, a photosensitive resin such as a photosensitive epoxy resin is known, and when the photosensitive epoxy resin is used, the wiring 22 is first deposited. A photosensitive epoxy resin which has been liquefied by adding and mixing an organic solvent or the like is applied to a predetermined thickness on the substrate 21 by a spin coating method or a roll coater method, and then the liquid photosensitive epoxy resin is applied. The insulating film 23 having the via holes 23a is formed by irradiating ultraviolet rays through the exposure mask, photo-curing the irradiated portion, and removing the non-photo-cured portion with an alkaline developing solution. In this case, a photoresist for separately forming the via hole 23a is deposited on the insulating film 23, or the insulating film 23 is formed by using a drill or the like.
Since it is not necessary to perforate the holes, there is an advantage that the manufacturing process of the multilayer wiring board is simplified.
【0004】また前記配線22、24は、ビアホール2
3aが設けられている箇所に該ビアホール23aよりも
ひと回り大きなランド22a、24aを有しており、配
線24のランド24aの一部をビアホール23a内で配
線22のランド22aの上面に直に被着させることによ
って両者を電気的に接続している。Further, the wirings 22 and 24 are the via holes 2
Lands 22a and 24a, which are slightly larger than the via holes 23a, are provided at the locations where the via holes 3a are provided. By doing so, they are electrically connected.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、この従
来の多層配線基板においては、絶縁膜23を感光性エポ
キシ樹脂等によって形成した場合、感光性エポキシ樹脂
中に含まれている有機溶剤23bがビアホール23aの
内周から染み出し、ビアホール23aの底面を成すラン
ド22aの上面に付着する。このため、後の工程におい
て、ビアホール23a内の配線22(ランド22a)上
に配線24を被着させようとしても、配線22及び24
間の大部分の箇所に有機溶剤23bが介在され、両者の
被着面積が小さなものとなってしまう。この結果、配線
22及び配線24を確実に接続させておくことが不可と
なる欠点を有している。However, in this conventional multilayer wiring board, when the insulating film 23 is formed of a photosensitive epoxy resin or the like, the organic solvent 23b contained in the photosensitive epoxy resin is replaced by the via hole 23a. Permeates from the inner periphery of the via hole 23a and adheres to the upper surface of the land 22a forming the bottom surface of the via hole 23a. Therefore, even if an attempt is made to deposit the wiring 24 on the wiring 22 (land 22a) in the via hole 23a in a later step, the wirings 22 and 24
The organic solvent 23b intervenes in most of the spaces between them, and the area where they are adhered becomes small. As a result, there is a drawback that the wiring 22 and the wiring 24 cannot be reliably connected.
【0006】[0006]
【課題を解決するための手段】本発明は上記欠点に鑑み
案出されたもので、基板上に、複数の配線から成る第1
配線群、絶縁膜及び複数の配線から成る第2配線群を順
次被着させるとともに、前記第1配線群の各配線と第2
配線群の各配線とを前記絶縁膜の所定位置に設けたビア
ホールの内部に充填されるビアホール導体を介して電気
的に接続して成る多層配線基板であって、前記絶縁膜に
設けたビアホールの直下に位置する第1配線群の配線幅
をビアホールの径よりも狭くしてビアホールの内壁と第
1配線群の配線の端部との間に間隙を設けたことを特徴
とする。SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks. The first invention is composed of a plurality of wirings on a substrate.
A second wiring group consisting of a wiring group, an insulating film, and a plurality of wirings is sequentially deposited, and each wiring of the first wiring group and the second wiring group are deposited.
A multilayer wiring board electrically connected to each wiring of a wiring group via a via-hole conductor filled inside a via hole provided at a predetermined position of the insulating film, wherein the via hole provided in the insulating film is It is characterized in that the wiring width of the first wiring group located immediately below is narrower than the diameter of the via hole, and a gap is provided between the inner wall of the via hole and the end of the wiring of the first wiring group.
【0007】[0007]
【発明の実施の形態】以下、本発明を添付図面に基づい
て詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
【0008】図1は本発明の多層配線基板をLEDヘッ
ドに適用した実施例を示す回路図であり、かかるLED
ヘッドは、ガラス、セラミック等から成る基板1上に、
各々に64個のLED素子を実装して成るLEDアレイL1
〜L40 と、プリンタ本体からの画像信号をLEDヘッド
内でシリアル転送するためのシフトレジスタ5と、該シ
フトレジスタ5に格納された画像信号を所定の期間だけ
保持するためのラッチ6と、ストローブ信号が供給され
ている間、ラッチ6の画像信号に応じて所定の出力を発
するゲートA1〜A64 と、このゲートA1〜A64 の出力に応
じてLEDアレイL1〜L40 の各LED素子に所定の電力
を供給する定電流回路B1〜B64 と、プリンタ本体からの
選択信号に応じてLEDアレイL1〜L40 に流れる電流の
オン・オフを制御するスイッチングトラジスタT1〜T40
とを配置した構造を有している。またかかるLEDヘッ
ドは、駆動回路(シフトレジスタ5、ラッチ6、ゲート
A1〜A64 、定電流回路B1〜B64 )の集積化とデータの供
給に用いるバスラインの単純化のために、LED素子を
アレイ単位にブロック化し、時分割駆動するようにして
おり、このため各定電流回路B1〜B64 に接続される第1
配線群Xの配線2とLEDアレイL1〜L40 の各LED素
子に接続される第2配線群Y1〜Y40 の配線4とを多層配
線し、これらを所定位置で厚み方向に導通させることに
よって所望の配線同士を電気的に接続させている。尚、
同図に示すLEDヘッドの場合、上述のような接続箇所
は全部で2560カ所にも及ぶ。FIG. 1 is a circuit diagram showing an embodiment in which the multilayer wiring board of the present invention is applied to an LED head.
The head is on a substrate 1 made of glass, ceramic, etc.
LED array L1 consisting of 64 LED elements mounted on each
~ L40, a shift register 5 for serially transferring the image signal from the printer body in the LED head, a latch 6 for holding the image signal stored in the shift register 5 for a predetermined period, and a strobe signal Is supplied, a predetermined power is supplied to the gates A1 to A64 which generate a predetermined output according to the image signal of the latch 6 and the respective LED elements of the LED arrays L1 to L40 according to the outputs of the gates A1 to A64. Constant current circuits B1 to B64 to be supplied, and switching transistors T1 to T40 for controlling on / off of currents flowing through the LED arrays L1 to L40 according to a selection signal from the printer body.
It has a structure in which and are arranged. Further, such an LED head includes a drive circuit (shift register 5, latch 6, gate
In order to integrate A1 to A64 and constant current circuits B1 to B64) and to simplify the bus line used for supplying data, LED elements are blocked in array units and time-division driven. First connected to constant current circuits B1 to B64
The wiring 2 of the wiring group X and the wiring 4 of the second wiring group Y1 to Y40 connected to the LED elements of the LED arrays L1 to L40 are multi-layered, and these are electrically connected to each other at a predetermined position in the thickness direction to obtain a desired shape. The wires are electrically connected. still,
In the case of the LED head shown in the figure, the above-mentioned connection points reach a total of 2560 points.
【0009】次に上述した第1配線群Xと第2配線群Y1
〜Y40 との接続構造について図2を参照しながら説明す
る。Next, the above-mentioned first wiring group X and second wiring group Y1
The connection structure with Y40 will be described with reference to FIG.
【0010】図2(a)は図1のZ部拡大平面図、図2
(b)は図2(a)のA’−A’線断面図であり、1は
基板、2は第1配線群Xの配線、3は絶縁膜、3aはビ
アホール、4は第2配線群Y1〜Y40 の配線である。FIG. 2A is an enlarged plan view of the Z portion of FIG.
2B is a sectional view taken along the line A′-A ′ of FIG. 2A, in which 1 is a substrate, 2 is wiring of the first wiring group X, 3 is an insulating film, 3a is a via hole, and 4 is a second wiring group. Wiring for Y1 to Y40.
【0011】前記基板1上には、配線2、絶縁膜3及び
配線4が順次被着されており、配線2と配線4とを絶縁
膜3の所定位置に設けたビアホール3aの内部に充填さ
れるビアホール導体(配線4の一部)を介して電気的に
接続している。A wiring 2, an insulating film 3 and a wiring 4 are sequentially deposited on the substrate 1, and the wiring 2 and the wiring 4 are filled in a via hole 3a provided at a predetermined position of the insulating film 3. They are electrically connected via a via hole conductor (a part of the wiring 4).
【0012】前記配線2及び配線4は互いに直交する方
向に配置されており、配線2は一定の幅(50μm)に形
成されている。The wiring 2 and the wiring 4 are arranged in directions orthogonal to each other, and the wiring 2 is formed to have a constant width (50 μm).
【0013】尚、これらの配線2、4は、いずれも、従
来周知のメッキ法やスクリーン印刷等の厚膜手法を採用
し、金属材料を所定の厚み(配線2の厚み:1〜4μ
m、配線4の厚み:1〜4μm)に被着させることによ
って形成される。Each of the wirings 2 and 4 adopts a thick film method such as a well-known plating method or screen printing, and is made of a metal material with a predetermined thickness (the thickness of the wiring 2 is 1 to 4 μm).
m, the thickness of the wiring 4 is 1 to 4 μm).
【0014】一方、前記2つの配線2、4間に介在され
る絶縁膜3には、配線2及び4の交差位置に配線2の幅
w1よりも大きな径φ(0.4mm )をもったビアホール3
aが設けられ、このビアホール3aを介して配線2及び
配線4を電気的に接続している。On the other hand, the insulating film 3 interposed between the two wirings 2 and 4 has a via hole 3 having a diameter φ (0.4 mm) larger than the width w1 of the wiring 2 at the intersection of the wirings 2 and 4.
a is provided, and the wiring 2 and the wiring 4 are electrically connected through the via hole 3a.
【0015】また前記絶縁膜3としては、感光性エポキ
シ樹脂等の感光性樹脂、或いは、このような樹脂をシー
ト状に加工したもの等が用いられ、例えば、感光性エポ
キシ樹脂を用いる場合、まず配線2が被着された基板1
の上面に、有機溶剤等を添加混合して液状になした感光
性エポキシ樹脂をスピンコート法やロールコータ法等に
よって所定厚み(50μm)に塗布し、次に前記液状の感
光性エポキシ樹脂に対して露光用のマスクを通して紫外
線を照射させ、該照射した部分を光硬化させるととも
に、光硬化されなかった部分をアルカリ系の現像液で除
去しビアホール3aを形成することによって得られる。Further, as the insulating film 3, a photosensitive resin such as a photosensitive epoxy resin, or a sheet processed from such a resin is used. For example, when the photosensitive epoxy resin is used, Substrate 1 to which wiring 2 is attached
A photosensitive epoxy resin, which has been liquefied by adding and mixing an organic solvent or the like, is applied to the upper surface of the coating to a predetermined thickness (50 μm) by a spin coat method or a roll coater method, and then the liquid photosensitive epoxy resin is applied. By irradiating ultraviolet rays through an exposure mask to photo-cure the irradiated portion and removing the non-photo-cured portion with an alkaline developing solution to form a via hole 3a.
【0016】このとき、ビアホール3aの直下に位置す
る配線2の幅w1はビアホール3aの径φよりも狭くなっ
ており、ビアホール3aの内壁と配線2の端部との間に
間隙が設けられることから、ビアホール3aの底には基
板1の上面とビアホール3aの周面と配線2の側面とで
囲まれた窪みが形成され、このため、感光性エポキシ樹
脂中に含まれている有機溶剤3bがビアホール3aの内
周から染み出しても、これらの有機溶剤3bは前述した
窪みの中に溜まり、配線2の上面に付着するのが有効に
防止される。この結果、後の工程において、ビアホール
3a内の配線2上に配線4を被着させる際、配線2、4
間に有機溶剤3bが介在されることは殆どなく、配線4
を配線2の上面に対して広い面積で良好に被着させるこ
とができるようになる。これにより、配線2及び配線4
をビアホール3aを介して確実かつ良好に電気的接続さ
せることが可能となる。At this time, the width w1 of the wiring 2 located immediately below the via hole 3a is smaller than the diameter φ of the via hole 3a, and a gap is provided between the inner wall of the via hole 3a and the end of the wiring 2. Therefore, a recess surrounded by the upper surface of the substrate 1, the peripheral surface of the via hole 3a, and the side surface of the wiring 2 is formed on the bottom of the via hole 3a, so that the organic solvent 3b contained in the photosensitive epoxy resin is formed. Even if the organic solvent 3b oozes out from the inner circumference of the via hole 3a, these organic solvents 3b are effectively prevented from accumulating in the above-mentioned depression and adhering to the upper surface of the wiring 2. As a result, when the wiring 4 is deposited on the wiring 2 in the via hole 3a in a later step, the wirings 2, 4
Almost no organic solvent 3b is interposed between the wiring 4 and
Can be satisfactorily adhered to the upper surface of the wiring 2 over a wide area. Thereby, the wiring 2 and the wiring 4
Can be reliably and satisfactorily electrically connected via the via hole 3a.
【0017】またこの場合、絶縁膜3上に別途、ビアホ
ール3aを形成するためのフォトレジストを被着させた
り、或いは、ドリル等を用いて絶縁膜3に孔開け加工を
施したりする必要はないことから、多層配線基板の製造
工程を簡略化することもできる。In this case, it is not necessary to separately deposit a photoresist for forming the via hole 3a on the insulating film 3 or to perforate the insulating film 3 with a drill or the like. Therefore, it is possible to simplify the manufacturing process of the multilayer wiring board.
【0018】尚、本発明は、上述したLEDヘッドのよ
うに基板上にビアホールを数多く形成したものほどその
効果は大となるが、このような実施例に限定されるもの
ではなく、本発明の要旨を逸脱しない範囲において種々
の変更、改良等が可能である。The effect of the present invention becomes greater as the number of via holes formed on the substrate, such as the LED head described above, is greater. However, the present invention is not limited to such an embodiment, and the present invention is not limited thereto. Various modifications and improvements can be made without departing from the spirit of the invention.
【0019】また上記実施例においては、2つの配線群
を絶縁膜を介して相互接続させた2層配線の多層配線基
板を例にとって説明したが、3つ以上の配線群間に絶縁
膜を介在させ、これらを相互接続した3層以上の積層構
造をもった多層配線基板にも適用可能である。Further, in the above embodiment, the description has been given by taking the example of the multilayer wiring board having the two-layer wiring in which the two wiring groups are interconnected via the insulating film, but the insulating film is interposed between the three or more wiring groups. It is also applicable to a multilayer wiring board having a laminated structure of three or more layers in which these are interconnected.
【0020】更に上記実施例においては、第1配線群の
配線幅を一定とし、ビアホールの内外でも等しくするよ
うにしたが、ビアホールの直下に位置する第1配線群の
配線幅がビアホールの径よりも狭くなっている限り、ビ
アホールの内と外における第1配線群の配線幅を何ら特
定するものではなく、例えば、第1配線群の配線幅をビ
アホールの外で内よりも広くしても構わない。Further, in the above-mentioned embodiment, the wiring width of the first wiring group is made constant and equalized inside and outside the via hole. However, the wiring width of the first wiring group located immediately below the via hole is smaller than the diameter of the via hole. As long as it is narrower, the wiring width of the first wiring group inside and outside the via hole is not specified at all. For example, the wiring width of the first wiring group may be wider outside the via hole than inside. Absent.
【0021】[0021]
【発明の効果】本発明の多層配線基板によれば、絶縁膜
中に含まれている有機溶剤等がビアホールの内周から染
み出しても、これらがビアホール内の配線に付着するこ
とは殆どなく、複数の配線群を絶縁膜のビアホールを介
して確実かつ良好に電気的接続させることができる。According to the multilayer wiring board of the present invention, even if the organic solvent or the like contained in the insulating film oozes out from the inner periphery of the via hole, these hardly adhere to the wiring in the via hole. The plurality of wiring groups can be reliably and satisfactorily electrically connected through the via holes of the insulating film.
【図1】本発明を適用したLEDヘッドの回路図であ
る。FIG. 1 is a circuit diagram of an LED head to which the present invention is applied.
【図2】(a)は図1のZ部拡大平面図、(b)は
(a)のA’−A’線断面図である。2A is an enlarged plan view of a Z portion of FIG. 1, and FIG. 2B is a sectional view taken along the line A′-A ′ of FIG.
【図3】(a)は従来の多層配線基板の部分拡大平面
図、(b)は(a)のA−A線断面図である。3A is a partially enlarged plan view of a conventional multilayer wiring board, and FIG. 3B is a sectional view taken along line AA of FIG.
1・・・基板 2・・・第1配線群の配線 3・・・絶縁膜 3a・・ビアホール 3b・・有機溶剤 4・・・第2配線群の配線 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Wiring of 1st wiring group 3 ... Insulating film 3a ... Via hole 3b ... Organic solvent 4 ... Wiring of 2nd wiring group
Claims (1)
群、絶縁膜及び複数の配線から成る第2配線群を順次被
着させるとともに、前記第1配線群の各配線と第2配線
群の各配線とを前記絶縁膜の所定位置に設けたビアホー
ルの内部に充填されるビアホール導体を介して電気的に
接続して成る多層配線基板であって、 前記絶縁膜に設けたビアホールの直下に位置する第1配
線群の配線幅をビアホールの径よりも狭くしてビアホー
ルの内壁と第1配線群の配線の端部との間に間隙を設け
たことを特徴とする多層配線基板。1. A first wiring group consisting of a plurality of wirings, a second wiring group consisting of an insulating film and a plurality of wirings are sequentially deposited on a substrate, and each wiring of the first wiring group and a second wiring. A multilayer wiring board electrically connected to each wiring of the group via a via hole conductor filled in a via hole provided at a predetermined position of the insulating film, which is directly below the via hole provided in the insulating film. A multilayer wiring board characterized in that the wiring width of the first wiring group located at is narrower than the diameter of the via hole to provide a gap between the inner wall of the via hole and the end of the wiring of the first wiring group.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22412795A JPH0969688A (en) | 1995-08-31 | 1995-08-31 | Multilayered circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22412795A JPH0969688A (en) | 1995-08-31 | 1995-08-31 | Multilayered circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0969688A true JPH0969688A (en) | 1997-03-11 |
Family
ID=16808971
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22412795A Pending JPH0969688A (en) | 1995-08-31 | 1995-08-31 | Multilayered circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0969688A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009290020A (en) * | 2008-05-29 | 2009-12-10 | Toshiba Corp | Flexible printed wiring board, shielding method of wiring board and electronics |
JP2013514668A (en) * | 2009-12-18 | 2013-04-25 | エーティーアイ・テクノロジーズ・ユーエルシー | Circuit board with via trace connection and manufacturing method thereof |
-
1995
- 1995-08-31 JP JP22412795A patent/JPH0969688A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009290020A (en) * | 2008-05-29 | 2009-12-10 | Toshiba Corp | Flexible printed wiring board, shielding method of wiring board and electronics |
JP2013514668A (en) * | 2009-12-18 | 2013-04-25 | エーティーアイ・テクノロジーズ・ユーエルシー | Circuit board with via trace connection and manufacturing method thereof |
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