JPH0969633A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the structure of a reliable SOI-MOS transistor and its manufacturing method by preventing the breakdown strength between the source and drain of the transistor from decreasing due to a substrate floatation effect. SOLUTION: A semiconductor device has an island-shaped semiconductor layer 2 including a p-type channel region 13 and an n-type source/drain region 4 formed on an insulation film and a p-type polysilicon 3 for fixing channel potential being formed in self-alignment manner similarly through a side-wall insulation film 6 being formed in self-alignment manner by anisotropic etching on the side wall and at the same time a p-type polysilicon 3 for fixing channel potential is connected to a channel region edge at a connection part. Therefore, a positive hole flowing to the channel region is pulled to a p-type polysilicon, thus preventing breakdown strength between source and drain from decreasing and obtaining a high-performance SOI-MOS transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device which prevents a substrate floating effect.
The present invention relates to a structure of an on-insulator-metal oxide semiconductor transistor (hereinafter referred to as an SOI-MOS transistor) and a manufacturing method thereof.

[0002]

2. Description of the Related Art As memory devices become highly integrated, transistors formed therein are required to have high performance and miniaturization. In general, an SOI-MOS transistor is electrically isolated from each other and can be completely isolated including a substrate. Therefore, leakage is small, current driving capability is high, and a short channel effect can be suppressed. it can.

Therefore, it is expected as a basic structure of a transistor of a memory device of the quarter micron order or a logic circuit in the future.

One of the insulation separations for obtaining such characteristics
One is the mesa type separation method. This mesa-type isolation method can be precisely processed according to a resist pattern by using a photolithography technique, and is suitable as an isolation method for future miniaturized SOI-MOS transistors.

However, with the miniaturization, the transistor having such a structure has the following problem of the substrate floating effect.

When the drain voltage is increased, the electric field in the channel direction becomes extremely large near the drain. Therefore, the electrons in the channel region are accelerated by this strong electric field and have a high energy. The electrons in the high energy state collide with the atoms of silicon in the vicinity of the edge of the drain region to generate a large number of electron-hole pairs. Among the electrons and holes generated by this impact ionization (impact ionization), the electrons flow into the drain region by being attracted to the high drain electric field and become part of the drain current. On the other hand, holes are inversely pushed back by the drain electric field to flow into the depletion layer below the channel region or the source region.

In this way, when the holes generated by the collision current flow into the depletion layer below the channel region, the inflow holes increase the potential in the vicinity of the channel region and the source region, and the potential barrier height increases. As a result, the breakdown voltage between the source and the drain is lowered.

The structure of an SOI-MOS transistor for eliminating the decrease in breakdown voltage between the source and drain is disclosed in Japanese Patent Laid-Open No. 4-239177.

Therefore, the structure of the conventional SOI-MOS transistor will be described with reference to FIGS.

In each figure, a semiconductor layer 103 made of p-type single crystal silicon is provided with an insulating layer 102 on a p-type silicon substrate 101, and n-type impurities formed on both sides of a channel region 133 in the semiconductor layer 103. Regions 131 and drain regions 132, a gate electrode 107 formed on the channel region 133 via a gate oxide film 106, a thin sidewall insulating film 104 formed on a sidewall of the semiconductor layer 103, and , This sidewall insulation film 1
04, openings 141 provided on both sides of the gate electrode 107,
142, and a silicon layer 105 which is a p-type impurity region arranged outside the sidewall insulating film 104.

In the SOI-MOS transistor having such a structure, for example, when impact ionization occurs near the end of the drain region 132 due to the generation of a minute leak current, holes diffuse below the channel region 133. . The holes flowing under the channel region 133 are extracted to the silicon layer 105 which is a p-type impurity region having an interface with the vicinity of the end portion of the channel region 133. Therefore, the potential near the end of the source region 131 is also fixed, and
It is also possible to prevent the breakdown voltage between the source / drain from being lowered.

However, in the method of forming the SOI-MOS transistor as described above, the insulating film 10 is provided between the semiconductor layer 103 and the silicon layer 105 to insulate them from each other.
It is necessary to pre-form a thin groove for depositing 4.
The groove width should be as small as possible by the latest technology of microfabrication. Generally, the width of the gate electrode is formed based on the minimum design dimension. Therefore, in order to form a groove narrower than the width of the gate electrode, an additional process for narrowing the groove is essential.

Further, it is necessary to provide the silicon layer 105 for fixing the channel potential so as to surround the semiconductor layer 103, and the chip inevitably becomes large when viewed from the whole device.

Further, the silicon layer 105 for fixing the channel potential is implanted with p-type ions such as boron ions in order to lower its resistance value. Therefore, a photoengraving process of covering the region other than the silicon layer 105 with a resist,
A p-type ion implantation process is required.

[0015]

As described above,
In the SOI-MOS transistor, there is a phenomenon that the breakdown voltage between the source / drain of the transistor is lowered due to the substrate floating effect. This phenomenon occurs when a silicon layer for fixing the channel potential is formed around the semiconductor layer via an insulating layer,
It was possible to eliminate the holes in the channel region through the interface near the end of the channel to the silicon layer.

However, in such a structure, the semiconductor layer and the silicon layer located on the outer periphery of the single crystal silicon layer must be formed through the insulating film formed in the narrow groove. The width of this groove is generally narrower than the width of the gate electrode formed according to the minimum design dimension, and thus an additional process for narrowing the groove width is essential. Further, since the silicon layer has a structure surrounding the semiconductor layer, there is a problem that the element area becomes large.

Furthermore, a p-type ion implantation step for lowering the resistance of the silicon layer for fixing the channel potential and an additional process of photolithography of the resist mask are required. Moreover, the photolithography of the resist mask is performed by superimposing the resist mask on the underlying silicon layer for fixing the channel potential,
It was difficult to control the dimensions of the resist mask.

In the present invention, an insulating film for insulating the semiconductor layer of the SOI-MOS transistor from the conductive layer located around the semiconductor layer can be easily formed, and the conductive film is formed through such an insulating film. It is an object of the present invention to provide a structure of a semiconductor device which does not increase the area of an element even when a layer is deposited, and a manufacturing method capable of forming such a structure by reducing the number of steps.

[0019]

According to a first aspect of the present invention, there is provided a semiconductor device having a first conductivity type island-shaped semiconductor layer having a sidewall and a main surface on an insulating film. And a sidewall insulating film formed along the sidewall,
A first conductive type conductive layer formed on the outside of the conductive type island-shaped semiconductor layer with a sidewall insulating film interposed, and a channel having a predetermined width on the main surface of the first conductive type island-shaped semiconductor layer. A MOS transistor having a region, a pair of second conductivity type source / drain regions formed so as to sandwich the channel region, and a gate electrode formed on the channel region with a gate insulating film interposed therebetween. The first conductive type conductive layer is in contact with the end of the channel region only on a part of the surface of the side wall of the end of the channel region.

With this structure, a minute leak current is generated, which causes impact ionization in the vicinity of the end of the drain region to flow into the bottom of the channel region, and the holes flow into the conductive layer of the first conductivity type in contact with the end of the channel region. Be pulled out.

Therefore, the potential of the channel region and the potential in the vicinity of the source region are fixed, the height of the potential barrier can be maintained, and the breakdown voltage between the source / drain can be prevented from lowering.

Since the first conductive type conductive layer is provided so as to fill the space between the island-shaped semiconductor layers with the sidewall insulating film around the island-shaped semiconductor layers interposed therebetween, the area of the element is not increased. Moreover, the flatness of the element is not impaired. further,
Since the conductive layer is already of the first conductivity type, there is no need to perform ion implantation or photolithography of the resist mask.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of introducing an impurity of a first conductivity type onto an SOI substrate and an island-shaped semiconductor layer having a side wall and a main surface on the SOI substrate. Forming process and SO including the island-shaped semiconductor layer
After depositing the insulating film on the I substrate, the step of forming the sidewall insulating film by leaving the insulating film on the sidewall of the island-shaped semiconductor layer and removing a part of the sidewall insulating film, The step of exposing the portion, and after depositing the first conductive type conductive layer on the SOI substrate including the island-shaped semiconductor layer, the first conductive type conductive layer is left around the sidewall insulating film, and the first conductive type conductive layer is formed. Is connected to the island-shaped semiconductor layer on a part of the surface of the sidewall portion, and the first conductive type conductive layer and the island-shaped semiconductor layer are connected to each other with the gate insulating film interposed on the island-shaped semiconductor layer. The method includes a step of forming a gate electrode so as to cover the portion, and a step of forming a pair of second conductivity type source / drain currents in the island-shaped semiconductor layer with the gate electrode sandwiched therebetween.

According to this manufacturing method, the sidewall insulating film can be formed on the sidewall of the island-shaped semiconductor layer in a self-aligned manner by anisotropic etching. It is possible to form the first conductive type conductive layer for drawing out holes in the channel region by anisotropic etching in a self-aligned manner so as to fill in between the regions of the island-shaped semiconductor layer via the sidewall insulating film. it can.

Further, the connecting portion between the channel region and the first conductive type conductive layer has almost the same size as the width of the gate electrode, and can be easily formed by the usual photoengraving technique and anisotropic etching without additional steps. Can be formed.

Therefore, it is possible to obtain a semiconductor device in which the potential of the channel region and the potential in the vicinity of the source region are fixed, and the reduction in breakdown voltage between the source and drain can be prevented.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION One embodiment of the present invention will be described with reference to the drawings.

1 to 4, the p-type island-shaped semiconductor layer 2 formed on the insulating film 1 and the p-type island-shaped semiconductor layer 2 are
A pair of n-type source / drain regions 4 sandwiching the p-type channel region 13 and a MOS transistor including a gate electrode 7 with a gate oxide film 5 interposed on the p-type channel region 13 are provided to form a p-type island shape. A sidewall insulating film 6 is provided on the sidewall around the semiconductor layer 2 and a p-type conductive layer 3 is provided.

The p-type conductive layer 3 and the channel region 13 are
Connection is made at the connection portion 12 formed at the end of the channel region 13. An interlayer insulating film 9 is interposed on a semiconductor element including a MOS transistor, and an aluminum wiring 11 is provided. The aluminum wiring 11 is connected to a MOS transistor by a contact tungsten plug 10.
It is connected to the type conductive layer 3 by a contact tungsten plug 14 for fixing the channel potential.

2 shows a cross section taken along line BB 'in FIG. 1, and FIG. 3 shows line A- in FIG.
4 shows a cross section taken along line A ', and FIG.
A cross section at C'is shown. In particular, in FIG. 2, in the connection portion 12 at the end of the channel region of the p-type island-shaped semiconductor layer 2,
The channel region 13 and the p-type conductive layer 3 are in contact with each other.

Except for the end of the channel region, the p-type semiconductor layer 2 and the p-type conductive layer 3 are insulated by the sidewall insulating film 6 as shown in FIGS.

Next, the operation will be described. When impact ionization occurs near the end of the n-type drain region 4 due to the generation of the minute leak current, holes diffuse below the channel region 13.

The holes flowing under the channel region 13 are
It flows into the p-type polysilicon 3 for fixing the channel potential through the connecting portion 12 at the end of the channel region 13.

In this way, by extracting the holes in the channel region 13 to the p-type polysilicon 3 for fixing the channel potential, the potential near the end of the n-type source region 4 can be fixed. Therefore, it is possible to prevent the breakdown voltage between the source and the drain from being lowered, and to obtain a stable and highly reliable semiconductor device.

Next, an example of a method of manufacturing a semiconductor device having such a structure will be described with reference to the drawings.

First, the SOI substrate is subjected to the SIMOX method (Separa
motion by Implanted Oxygen). That is, as shown in FIG. 5, oxygen ions are implanted into the substrate 20 at an energy of 190 KeV and a dose amount of 1.8 × 10 ¹⁸ / cm ² . After that, annealing is performed in a nitrogen atmosphere at a temperature of 1320 ° C. for 6 hours to form an insulating film 1 as shown in FIG.

Next, as shown in FIG. 7, boron ions having an energy of 50 KeV and a dose of 1 × 1 are formed on the silicon layer.
Implanting at 0 ¹² / cm ² to make the silicon layer p-type.

Then, as shown in FIG. 8, a resist pattern 21 is formed by performing photolithography for forming the island-shaped semiconductor layer. Next, anisotropic etching is performed using the resist pattern 21 as a mask to form the p-type island-shaped semiconductor layer 2 as shown in FIG. Then, as shown in FIG. 10, low pressure CVD is performed on the insulating film 1 including the p-type island-shaped semiconductor layer 2.
A silicon oxide film (1000 to 2000Å) is deposited by the method. Then, the entire surface is etched back by anisotropic etching to form a sidewall insulating film 6 on the sidewall of the p-type island-shaped semiconductor layer 2 in a self-aligned manner as shown in FIG.

At this stage, FIG. 12 is viewed from above the substrate. The p-type island-shaped semiconductor layer 2 is surrounded by the sidewall insulating film 6.

Next, the connecting portion 1 is formed at the end of the p-type channel region 13.
2, photolithography is performed to form FIG.
A resist pattern 22 is formed as shown in FIG. FIG.
4 shows a cross section taken along the line AA 'in FIG.
Next, anisotropic etching is performed using the resist pattern 22 as a mask to remove the sidewall insulating film 6 and form the connection portion 12 as shown in FIG.

After that, as shown in FIG. 16, p-type polysilicon 3 is deposited on the entire surface of the substrate of about 5000 Å, and then the entire surface is etched back by anisotropic etching. As shown in FIG. The sidewall insulating film 6 is provided outside the layer 2.
The channel potential fixing p-type polysilicon 3 is formed in self-alignment via. In FIG. 17, the p-type polysilicon remains in the entire region outside the sidewall insulating film 6, but in reality, in the region where the island-shaped semiconductor layer 2 is not formed, the p-type polysilicon 3 is formed. May be etched. However, this p-type polysilicon 3
It suffices that the structure is such that it is connected to the tungsten plug 14 for fixing the channel potential (see FIG. 1) formed after this, and for example, it is a dummy from the island-shaped semiconductor layer 2 toward the tungsten plug 14 for fixing the channel potential. The purpose can be achieved by forming a pattern and forming the p-type polysilicon 3 on its sidewall in a self-aligned manner.
Does not change the essence at all. 18 is the same as FIG.
6 is a diagram showing a cross section taken along line BB ′ in FIG.
It contacts the island-shaped semiconductor layer 2. The connecting portion 12 is a portion that will be the end of the channel region in a later step. In addition, FIG.
FIG. 17 shows a cross section taken along line AA '.

P-type polysilicon 3 for fixing channel potential
Are formed in a self-aligned manner as described above, so that each p
It can be easily formed without being restricted by the width W for separating the type semiconductor layer 2. Therefore, the isolation width can be set to the minimum dimension allowable in design, and since the p-type polysilicon layer 3 is formed between them, the area expansion of the semiconductor element can be prevented.

Next, after forming a gate oxide film 5 having an oxide film of 500Å by a thermal oxide film, a polysilicon film having a film thickness of about 4000Å is deposited by a low pressure CVD method, followed by photoengraving and anisotropic etching. As shown in 20, the gate electrode 7 is formed. Next, as shown in FIG. 21, a gate sidewall insulating film 8 is formed on the sidewall of the gate electrode 7 to form an LDD structure (Lightly Doped Drain).

Next, photoengraving for forming the source / drain regions is performed to form a resist pattern 23 as shown in FIGS. FIG. 23 shows a cross section taken along line AA ′ in FIG. The region other than the region of the p-type island-shaped semiconductor layer 2 is covered with the resist. Next, using the resist pattern 23 and the gate electrode 7 as a mask, arsenic ions are energy 50 KeV and the dose is 1 × 10 ¹⁵ / cm 3.
Implantation is performed at ² to form an n-type region while leaving the p-type region under the gate electrode 7. This n-type region becomes the n-type source / drain region 4, and the p-type region between them is the n-type channel region 1.
It becomes 3.

After that, an interlayer insulating film 9 is deposited by 5000 Å by a low pressure CVD method or a normal pressure CVD method, and a contact is formed through photoengraving and anisotropic etching.
Next, after depositing tungsten or the like, a tungsten plug 10 is formed by etching back the entire surface. After that, the aluminum wiring 11 is formed to form a semiconductor device having a sectional structure as shown in FIG.

In the above manufacturing method, an example of an n-channel transistor having a p-type channel region is shown.
A p-channel transistor can be formed similarly.

In this case, the channel region forms n-type by phosphorus implantation, and the source / drain regions have BF.
_A p-type can be formed by ₂ implantation.

Therefore, by using both of them together,
As shown in FIG. 24, an NMOS section 24 having an n-channel transistor and a PM having a p-channel transistor
A CMOS circuit including the OS section 25 can be formed. The polysilicon 26 for fixing the channel potential in the PMOS section 25 is n-type.

As described above, by extracting the holes flowing under the channel region 13 to the p-type polysilicon 3 for fixing the channel potential, it is possible to prevent the breakdown voltage between the source and the drain from being lowered, and to improve the performance. A semiconductor device can be obtained. In addition, the sidewall insulating film 6 for insulating the p-type island-shaped semiconductor layer 2 including the channel region 13 and the channel potential fixing p-type polysilicon 3 from each other is used as the insulating film 1 including the p-type island-shaped semiconductor layer 2. After the silicon oxide film is deposited on the upper surface, the entire surface is etched back by anisotropic etching, so that it can be easily formed in a self-aligned manner. Further, the channel potential fixing p-type polysilicon is formed outside the sidewall insulating film 6 by anisotropic etching after the p-type polysilicon is deposited on the insulating film 1, so that it can be easily formed in a self-aligned manner. it can.

Furthermore, since the polysilicon for fixing the channel potential is formed of p-type polysilicon, it is not necessary to perform p-type ion implantation or photolithography of the resist mask, and the number of steps can be reduced.

It should be understood that the embodiments disclosed this time are illustrative in all points and not restrictive. The scope of the present invention is shown not by the scope described above but by the scope of the claims, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope.

[Brief description of drawings]

FIG. 1 is an SOI-M according to one embodiment of the present invention.
It is a top view which shows an OS transistor.

FIG. 2 is a diagram showing a cross section taken along line BB ′ in FIG.

FIG. 3 is a diagram showing a cross section taken along line AA ′ in FIG.

FIG. 4 is a view showing a cross section at CC ′ in FIG. 1.

FIG. 5 is an SOI-M according to one embodiment of the present invention.
FIG. 7 is a cross-sectional view showing a step of the method for manufacturing the OS transistor.

FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in one embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step performed after the step shown in FIG. 6 in one embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in one embodiment of the present invention.

9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in one embodiment of the present invention. FIG.

FIG. 10 illustrates one embodiment of the present invention, FIG.
FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG.

FIG. 11 illustrates one embodiment of the present invention.
FIG. 7 is a cross-sectional view showing a step performed after the step shown in 0.

FIG. 12 illustrates one embodiment of the present invention.
It is a top view which shows the process shown in FIG.

FIG. 13 illustrates one embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG.

FIG. 14 is a diagram showing a cross section taken along line AA ′ in FIG. 13;

FIG. 15 illustrates one embodiment of the present invention.
6 is a top view showing a step performed after the step shown in FIG.

FIG. 16 illustrates one embodiment of the present invention.
5 is a top view showing a step performed after the step shown in FIG.

FIG. 17 illustrates one embodiment of the present invention.
6 is a top view showing a step performed after the step shown in FIG.

FIG. 18 illustrates one embodiment of the present invention.
7 is a view showing a cross section taken along line BB ′ in FIG. 7. FIG.

FIG. 19 illustrates one embodiment of the present invention.
7 is a view showing a cross section taken along line AA ′ in FIG.

FIG. 20 illustrates one embodiment of the present invention.
FIG. 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9.

FIG. 21 illustrates one embodiment of the present invention, FIG.
FIG. 7 is a cross-sectional view showing a step performed after the step shown in 0.

FIG. 22 illustrates one embodiment of the present invention, FIG.
FIG. 6 is a top view showing a step performed after the step shown in FIG.

FIG. 23, in one embodiment of the invention, FIG.
FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG.

FIG. 24 is an SOI-M according to another embodiment of the present invention.
It is a top view of a semiconductor device including an OS transistor.

FIG. 25 is a top view showing a conventional SOI-MOS transistor.

FIG. 26 is a diagram showing a cross section taken along line I-I in FIG. 25.

FIG. 27 is a view showing a cross section taken along line II-II in FIG. 25.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Insulating film, 2 p-type island-like semiconductor layer, 3 channel potential fixing p-type polysilicon, 4 n-type source / drain region, 5 gate oxide film, 6 sidewall insulating film, 7 gate electrode, 12 connection part, 13 p Type channel region.

Claims (2)

[Claims] 1. An island-shaped semiconductor layer of a first conductivity type having a sidewall portion and a main surface on an insulating film, a sidewall insulation film formed along the sidewall portion, and an island-shaped portion of the first conductivity type. A first conductive type conductive layer formed outside the semiconductor layer with the sidewall insulating film interposed therebetween; a channel region having a predetermined width on a main surface of the first conductive type island-shaped semiconductor layer; A MOS transistor having a pair of second conductivity type source / drain regions formed so as to sandwich the channel region, and a gate electrode formed on the channel region with a gate insulating film interposed therebetween, A semiconductor device in which the first conductive type conductive layer is in contact with the end of the channel region only on a part of the surface of the sidewall portion at the end of the channel region. 2. A step of introducing an impurity of the first conductivity type into an SOI substrate; a step of forming an island-shaped semiconductor layer having a sidewall portion and a main surface on the SOI substrate; and including the island-shaped semiconductor layer. A step of depositing an insulating film on the SOI substrate and then forming a sidewall insulating film while leaving an insulating film on a sidewall portion of the island-shaped semiconductor layer; and removing a part of the sidewall insulating film to form a surface of the sidewall portion. Exposing a part of the first conductive type conductive layer on the SOI substrate including the island-shaped semiconductor layer, leaving the first conductive type conductive layer around the sidewall insulating film, and A step of connecting the first conductive type conductive layer to the island-shaped semiconductor layer at a part of the surface; and a step of connecting the first conductive type conductive layer to the island-shaped semiconductor layer with a gate insulating film interposed therebetween. A gate electrode is formed so as to cover a portion connected to the island-shaped semiconductor layer. Degree and, in the island-shaped semiconductor layer, a method of manufacturing a semiconductor device including the step of forming a second conductivity type source / drain regions of the pair across the gate electrode.