JPH0969541A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize the electrical conduction or sealing performance by employing Au at least on the surface of metal bump of inside electrode and an insulation plate having irregular surface touching the sealing resin of auxiliary wiring plate piece. SOLUTION: An inner electrode 21 comprises a metal 213 filling an inner electrode hole 212 made through an insulation layer 24, and a metal bump 211 formed on the end face of the metal 213. An Au layer is formed at least on the surface of metal bump 231 and bonded to the Al electrode 11 of a semiconductor chip 1. The gap between the semiconductor chip A1 and an auxiliary wiring plate piece 2 is resin sealed and the surface of auxiliary wiring plate piece 2 touching the sealing resin 3 is provided with irregularities of 0.005-0.5μm. Since the electrode 11 of a semiconductor chip 1 and the metal bump 211 of auxiliary wiring plate piece 2 is bonded strongly through intermetallic bonding of Au-At and the bonding strength of adhesion interface between the sealing resin 3 and auxiliary wiring plate piece 2 is enhanced by the irregularities, interfacial stripping can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip scale package (CSP) type semiconductor device.

[0002]

2. Description of the Related Art As a package semiconductor chip,
A semiconductor chip is mounted on a die frame die pad, and the semiconductor chip electrode and the lead frame inner lead are wire-bonded to each other to form the semiconductor chip lead frame.
A structure in which a resin is sealed except for the outer lead is well known. However, in such a package structure,
It is necessary to make the pitch of the outer leads of the lead frame considerably wide in terms of soldering accuracy, which inevitably leads to an increase in the size of the package, which is disadvantageous for increasing the density.

Therefore, as shown in FIG. 7, an inner electrode 21 'connected to the electrode 11' of the semiconductor chip 1 ', an outer electrode 22' connected to the conductor end of the mounted circuit board, and an electrode 22 'between these electrodes. A chip-sized auxiliary wiring board piece 2'provided with a printed wiring pattern composed of an internal lead-out conductor 23 'straddling is applied to the surface of the semiconductor chip 1'on the side of the electrode 11', and the auxiliary wiring board piece 2 ' The inner electrode 21 ′ and the electrode 11 ′ of the semiconductor chip 1 ′ are connected via the metal bump 221 ′, and then the gap between the auxiliary wiring board piece 2 ′ and the semiconductor chip 1 ′ and the semiconductor chip outer surface are covered with the resin 3. It has been proposed to seal it with '(Japanese Patent Laid-Open No. 5-82586, etc.).

[0004]

However, according to the results of studies by the present inventors, in this semiconductor device,
Since the thermal expansion coefficient and Young's modulus of the metal bumps 211 'and the sealing resin 3'are different, a peeling force acts on the interface between the sealing resin and the auxiliary wiring board piece against the temperature rise, and the temperature drop is caused. On the other hand, it was found that the peeling force acted on the bonding interface between the metal bump and the chip electrode, and the stability of electrical conduction against heat stress and the seal stability were insufficient (in 121 ° C saturated steam). When the conduction failure rate was measured 200 hours after the pressure-cooker test, it reached 20 to 75%).

It is an object of the present invention to provide a semiconductor device in which the resin package semiconductor chip with the auxiliary wiring board piece has a stable electrical conduction and a stable sealing property.

[0006]

A semiconductor device according to the present invention includes an insulating plate, an inner electrode connected to an electrode of a semiconductor chip, an outer electrode connected to a conductor end of a mounted circuit board, and an electrode between these electrodes. An internal routing conductor that straddles the inner electrode is formed by a metal filled in a hole reaching the routing conductor from one surface of the insulating plate and a metal bump protruding from the hole, and at least the metal bump The metal bumps of the auxiliary wiring board piece whose surface is made of Au are joined to the Al electrodes of the semiconductor chip, and the semiconductor chip and the auxiliary wiring board piece are sealed with resin to seal the auxiliary wiring board piece. Depth of insulating plate surface in contact with resin is 0.005μm ~
It has a textured surface of 0.5 μm or has a surface tension of 35 mJ / m ² or more on the surface of the insulating plate.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is an explanatory view showing an embodiment of the semiconductor device according to the present invention, and FIG.
Similarly, it is a perspective explanatory view in which a part is cut away, and the routing conductor is routed toward the outside. FIG. 2C is an explanatory view showing another embodiment of the semiconductor device according to the present invention in FIG.
The routing conductor is routed inward. In FIGS. 1A to 1C, 1 is a semiconductor chip. Reference numeral 2 denotes an auxiliary wiring board piece, which is an inner electrode 2 bonded to the electrode 11 of the semiconductor chip 1 at a metal bump 211.
1, an outer electrode 22 located at a position different from the back position of the inner electrode 21, an internal routing conductor 23 extending over these two electrodes 21-22, and insulating layers 24 provided on both surfaces of the routing conductor 23. And 25. The inner electrode 21 is composed of a metal 213 filled in the inner electrode hole 212 formed in the insulating layer 24 and a metal bump 211 formed on the end surface of the filled metal 213.
The outer electrode 22 is composed of the metal 222 filled in the outer electrode hole 221 formed in the insulating layer 25, and the metal bump 223 is formed on the end surface of the filled metal 222. In the inner electrode 21, both the filling metal 213 and the metal bump 211 are made of Au, or the filling metal 213 is made of a metal other than Au (for example, nickel, copper, palladium, silver, etc.) and the metal bump 211 is made of Au. It is said to be made. In addition, the metal bumps 211 of the inner electrode 21
The metal bumps 2 are formed by forming a part other than Au (for example, nickel, copper, palladium, silver, etc.) except the surface thereof.
It is also possible to provide an Au layer on the surface of 11. The metal bumps 211 and 223 may have any shape such as a straight wall bump, a mashroom bump, and a mixed bump.

The surface of the insulating layer 24 of the auxiliary wiring board piece 2 facing the semiconductor chip 1 has a depth of 0.005 μm to 0.
It has an uneven surface of 5 μm or has a surface tension (Zi
critical surface tension obtained from sman plot) 35 m
J / m ² or more, preferably 40 J / m ² or more. The former surface roughening can be carried out by a chemical treatment such as acid treatment, alkali solution treatment, coupling agent treatment, graft treatment or the like, physical treatment such as corona discharge treatment, high frequency plasma treatment or ion etching treatment. Examples of the resin film satisfying the latter surface tension condition include polyimide and polyethylene terephthalate, and even a resin film having a surface tension of 35 mJ / m ² or less,
Surface tension of 35mJ by alkali treatment or plasma treatment
/ M ² or more.

Reference numeral 3 denotes a sealing resin, which is filled between the semiconductor chip 1 and the auxiliary wiring board piece 2 and at the same time the semiconductor chip 1 is filled.
Is coated on the outer surface of. The latter outer surface coating can be omitted.

The size of the auxiliary wiring board piece 2 is equal to the plane dimension of the semiconductor chip 1 (usually 3 mm to 20 mm square), or 200% or less, preferably 130% or less of the plane dimension of the semiconductor chip 1. To be done. The outer electrodes 22, 2
The distance between the two is required to be as wide as possible within the plane dimension of the auxiliary wiring board piece 2 in order to prevent a solder bridge at the time of soldering to the mounted circuit board, and is usually almost equal. It is considered as an interval.

The auxiliary wiring board piece 2 may have a multilayer structure as shown in FIG. In FIG. 2, a pair of the electrode 11 of the semiconductor chip 1 and the conductor end 110 of the mounted circuit board to be electrically connected to the electrode 11 corresponds to the lead conductor 23 of one layer. A hole 212 facing the semiconductor chip electrode 11 is provided in the insulating laminated body a, the hole 212 is filled with a metal 213, and a metal bump 211 is formed on the top surface of the filled metal 213, and the inside of the one leading conductor 23 is formed. The electrode 21 is formed. In addition, a hole 221 facing the one conductor end 110 of the mounted circuit board to be electrically connected to the one semiconductor chip electrode 11 from the one lead conductor 23 is provided in the insulating laminated body a, and the metal 222 is provided in the hole 221. The outer electrode 22 for the one lead-out conductor 23 that is filled is formed, and the top surface of the filled metal 222 is connected to the conductor end of the mounted wiring board via the solder bump 223.

The above semiconductor device can be manufactured by the work procedure shown in FIGS. First,
As shown in FIG. 3A, the conductor 23 is printed and formed on one surface of the insulating support film 24. It is preferable to use a method of chemically etching the metal foil of the metal foil laminated synthetic resin film into a predetermined routing pattern for the print formation of the routing conductor 23. This metal foil laminated synthetic resin film uses a two-layer base material in which copper foil is fused to the synthetic resin film, a three-layer base material in which copper foil is adhered to the synthetic resin film with a thermoplastic or thermosetting adhesive, etc. There is no particular restriction on the material of the synthetic resin film as long as it satisfies the heat resistance when the metal bumps are formed by the wire-bumping method and the chemical resistance when the metal bumps are formed by the plating method. Any suitable material can be used, and for example, a polyimide film, a polyethylene terephthalate film, a polyetherimide film, a polyethersulfone film, a polyphenylene sulfide film, a polyetherketone film or the like can be used. The thickness of this synthetic resin film is usually 10 to 150 μm.

After the lead-out conductor 23 is formed by printing in this way, an inner electrode hole 212 is formed in the insulating support film 24 as shown in FIG. For this perforation, generally, a drilling process, a laser etching process or the like can be used, and particularly in the case of a polyimide film, a wet perforation method such as alkali etching can be used. In the case of a two-layer substrate type polyimide film, a photosensitive polyimide may be used and it may be perforated by exposure.

After forming the inner electrode hole 212, as shown in FIG. 3C, a metal other than gold (silver, silver) is formed in the hole 212 by using the insulating film 24 on the conductor 23 on the bottom surface of the hole 212 as a plating mask. (Nickel, copper, palladium, etc.) 213 is filled by plating, and Au is plated on the filled metal to form gold bumps 211 as shown in FIG. 3D, or a wire bonder is used. The tip of the gold wire is melted, and the inner electrode 21 is formed by filling the hole 212 with metal and forming the metal bump 211 with Au.

After the inner electrode 21 is formed in this manner, as shown in FIG. 3E, the resin 25 is covered on the print forming surface of the lead-out conductor 23, and the resin 25 shown in FIG. F)
As shown in FIG. 3, an outer electrode hole 221 is formed in the cover coat insulating layer 25, and as shown in FIG. 3G, solder 2 or the like is formed in the hole 221 by the wire bonder.
Fill 22 to form the outer electrode. Further, the surface of the insulating film 24 of the auxiliary wiring board piece 2 is subjected to surface roughening treatment, or when the surface tension of the insulating film is 35 mJ / m ² or less, the surface tension of the insulating film 24 is reduced by alkali treatment or plasma treatment.
mJ / m ² or more.

After that, as shown in FIG.
The auxiliary wiring board piece 2 is aligned so that the metal bumps 211 of the inner electrodes 21 are aligned with the electrodes 11 of the semiconductor chip 1, and individual thermocompression bonding is performed by a collective crimp connection such as a hot bar or pulse heat or a single point bonder. By connecting, the Al electrode 11 of the semiconductor chip 1 and the metal bump 211 of the inner electrode 21 of the auxiliary wiring board piece 2 are joined by Au-Al metal bonding, and the semiconductor chip 1 and the auxiliary wiring board piece 2 are electrically and mechanically connected. To join together. When performing individual thermocompression bonding using a single point bonder, it is preferable to use ultrasonic bonding together to lower the thermocompression bonding temperature.

After mounting the semiconductor chip 1 on the auxiliary wiring board piece 2 in this manner, as shown in FIG. 3L, the resin 3 is provided between the semiconductor chip 1 and the auxiliary wiring board piece 2. Seal. Transfer molding, potting, casting or the like can be used for this resin sealing. In this case, the resin 3 may be coated on the outer surface of the semiconductor chip 1. After the resin encapsulation, solder bumps 223 are formed on the end faces of the filled metal of the outer electrode 22 as shown in FIG.
This completes the fabrication of the semiconductor device up to the packaging process.

As a method of aligning the electrode 11 of the semiconductor chip 1 and the metal bump 211 of the inner electrode 21 of the auxiliary wiring board piece 2 at the stage shown in FIG. Then, a method can be used in which an alignment bump 211a is attached to the dummy electrode 11a of the semiconductor chip, an alignment hole 212a is formed in the auxiliary wiring board piece 2, and the hole 212a and the alignment bump 211a are fitted. In this case, the height of the alignment bumps 211a is slightly higher than that of the metal bumps 211 of the inner electrode 21, and the height of the alignment bumps 211a is 50 μm, for example, while the height of the latter 211 is 20 μm. Regarding the material of the alignment bumps 211a, when the bumps 211a are pressed against the electrodes 11 of the semiconductor chip 1 and the inner metal bumps 211 of the auxiliary wiring board piece 2 at the time of bonding, those that soften at the bonding temperature are used. If it is not pressurized, it is not particularly limited.
The hole diameter of the alignment hole 212a is set so that the positional deviation between the electrode 11 of the semiconductor chip 1 and the inner metal bump 211 of the auxiliary wiring board piece 2 is suppressed to 10% or less. It goes without saying that the manufacturing procedure of the semiconductor device described above can be changed as appropriate. For example, after applying the cover coat, before forming the outer electrode, the semiconductor chip is joined to the auxiliary wiring board piece, and the semiconductor chip and the auxiliary wiring board piece are resin-sealed, and then, It is also possible to form the outer electrode on the cover coat.

In the semiconductor device according to the present invention, it is possible to seal only between the semiconductor chip and the auxiliary wiring board piece, but as shown in FIGS. 5 (a) to 5 (d),
It is also possible to seal the entire outer surface including the lateral edge and the back surface of the semiconductor chip. In FIG. 5A, the space between the semiconductor chip 1 and the auxiliary wiring board piece 2 is sealed with an epoxy resin 31, and the lateral edge portion and the back surface of the semiconductor chip 1 are sealed with a silicon resin 32. I am doing it. In FIG. 5B, the space between the semiconductor chip 1 and the auxiliary wiring board piece 2 is sealed with an epoxy-based resin 31, and the lateral edge portion and the back surface of the semiconductor chip 1 are bonded to each other by an adhesive sheet 33 (for example, It is sealed by adhering an adhesive sheet using an epoxy-rubber resin as an adhesive. In FIG. 5C or FIG. 5D, the reinforcing frame 34 (made of synthetic resin or metal) is fixed. In sealing the outer surface of the semiconductor chip, in order to dissipate heat from the semiconductor chip, only the lateral edge portion of the semiconductor chip 1 is sealed with resin 3 and the back surface is exposed, as shown in FIG. You can also let it.

In order to improve the heat dissipation of the semiconductor chip,
As shown in (b) of FIG. 6 or (d) of FIG. 6, a radiation fin or a heat spreader 35 should be attached (in (b) of FIG. 6, the fin 35 is fixed by a heat conductive adhesive 36). 6 (c), the fin 35 is fixed by the sealing resin 3) is effective. Further, as shown in FIG. 6D, an inner metal filling hole 371 that does not come into contact with the electrodes of the semiconductor chip 1 and an inner conductor 372 (not a lead conductor) thermally connected to the filling metal 371.
An outer metal filling hole 373 and a metal bump 374 that are thermally connected to the inner conductor 372 are provided, and heat generated by the semiconductor chip 1 is radiated through these paths, which is indicated by a dotted line in FIG. So that the lead conductor 24
It is also effective to provide a heat radiation dummy such that the conductor (copper foil) 24a is left as much as possible with a predetermined insulating gap and the remaining conductor 24a is used as a heat spreader.

In the above semiconductor device, the coefficient of thermal expansion of the metal bump is α ₁ , the coefficient of thermal expansion of the encapsulating resin is α ₂ , the Young's modulus of the metal bump is E ₁ , the Young's modulus of the encapsulating resin is E ₂ , and the semiconductor is When the plane area of the chip is S, the cross-sectional area of all metal bumps is Sβ ₁ , and the cross-sectional area of the sealing resin is Sβ ₂ , the temperature rises (temperature t ₀
Peeling force that acts on the bonding interface between the metal bump and the chip electrode when the temperature rises (from temperature t to temperature t), or the interface between the auxiliary wiring board piece and the sealing resin when the temperature drops (falls from temperature t to temperature t ₀ ). The peeling force acting on can be grasped by X in the following equation (k is a stress relaxation coefficient due to extension of the auxiliary wiring board piece, and if the auxiliary wiring board piece is a rigid body, k = 1). X = k (α ₁ −α ₂ ) | t−t ₀ | E ₁ · Sβ ₁ / (1 + β ₁ E ₁ / β ₂ E ₂ )

However, in the semiconductor device according to the present invention, the electrodes of the semiconductor chip 1 and the metal bumps 211 of the auxiliary wiring board piece 2 are sufficiently strongly bonded by Au-Al metal bonding, and the semiconductor The adhesive strength of the adhesive interface between the resin between the chip 1 and the auxiliary wiring board piece 2 and the auxiliary wiring board piece 2 has uneven surface processing (uneven surface of 0.005 μm to 0.5 μm) or wettability to resin. Since it is enhanced by increasing the surface tension (surface tension of 35 mJ / m ² or more), interfacial peeling can be well prevented despite the action of the peeling force X, and the routing conductor of the auxiliary wiring board piece 2 can be placed in the insulating plate. Since it is embedded, the insulation between the electrodes of the semiconductor chip 1 can be stably maintained even when exposed to a severe thermal history. This can be confirmed by comparing the following examples and comparative examples with respect to the conductivity failure ratio after 200 hours in the pressure cooker test in the 121 ° C. saturated steam.

[0023]

【Example】

[Examples 1 to 15 and Comparative Examples 1 to 6] Films with surface tension Y shown in Table 1 (in Table 1, PI is polyimide. P
ET is polyethylene terephthalate. PP is polypropylene. Alkali treatment is immersed in 0.1 NKOH aqueous solution for 5 hours. The plasma treatment is a glow discharge treatment for 30 seconds at 100 w and 13.56 MHz in an oxygen gas atmosphere of 0.1 torr. Thickness of all 60 μm)) as a film carrier, and the inner electrode is electrolytically plated (the holes are filled with the metal shown in Table 1 by electrolytic plating, and Au bumps having the height shown in Table 1 are formed by electrolytic plating), Alternatively, the stud bump method (using a wire bonder, the tip of the Au wire is melted, the hole is filled with Au, and the height dimension A shown in Table 1 is used.
The auxiliary wiring board piece (same size as the chip) formed by forming u bumps) has a thickness of 0.375 mm and a side length of 1
300 mm 5.0 mm square semiconductor chips for reliability evaluation
The composition shown in Table 2 is a resin encapsulation having an outer dimension of about 0.550 mm and a side length of 17.0 mm, which is bonded at 0 ° C.
In the above, the epoxy resin 1 is a bisphenol A type epoxy resin having an epoxy equivalent of 180. Epoxy resin 2 is a cresol novolac type epoxy resin having an epoxy equivalent of 195.
Acid-free water is methylhexaphthalephthalic anhydride. PPS is polyphenylene sulfide. The compounding amount was parts by weight). Regarding these examples and comparative examples, the conductivity failure rate after 200 hours in the pressure cooker test at 121 ° C. in saturated steam was measured. The 90 ° peel strength between the sealing resin and the auxiliary wiring board piece is also shown.

[Examples 1'to 20 'and Comparative Example 1'to
9 '] A film having the material and thickness shown in Table 4 is subjected to the surface treatment shown in Table 4 (in Table 4, the ion etching is performed in a nitrogen gas atmosphere at a high frequency of 3x10E-3 torr, 13.56 MHz for 200 w for 5 minutes. The treatment is soaked in hot xylene for 3 hours, the alkali treatment is soaked in 0.1 NKOH aqueous solution for 5 hours, the ultraviolet treatment is 100 w of UV irradiation, and the corona treatment is 1200 MHz, 33 w, 1 minute of low frequency corona irradiation. A film carrier having an uneven surface with the uneven depth shown in Fig. 4 is used, and the inner electrode is electrolytically plated (the holes are filled with the metal shown in Table 4 by electrolytic plating, and the Au bumps of the height shown in Table 4 are electrolytically plated. Formed by the method),
Or stud bump method (using wire bonder
Melt the tip of the u-line, fill the holes with Au, and
Auxiliary wiring board pieces (same size as the chip) formed by forming Au bumps with the height shown in
m, and a square semiconductor chip for reliability evaluation having a side length of 15.0 mm is joined at 300 ° C., and the outer dimension is about 0.
Table 5 shows the resin encapsulation with 550 mm and one side length of 17.0 mm.
(In Table 5, epoxy resin 1 is a bisphenol A type epoxy resin having an epoxy equivalent of 180. Epoxy resin 2 is a cresol novolac type epoxy resin having an epoxy equivalent of 195. Acid-free aqueous solution is methylhexahydrate anhydrous phthalate. Acid, PPS is polyphenylene sulfide, and the compounding amount is parts by weight). With respect to these examples and comparative examples, pressure-cooker test 2 in 121 ° C. saturated steam
When the conductivity failure rate after 00 hours was measured, it was as shown in Table 6. In addition, 9 between the sealing resin and the auxiliary wiring board piece
The 0 ° peel strength is also shown.

[0025]

[Table 1]

[0026]

[Table 2]

[0026]

[Table 3]

[0027]

[Table 4]

[0028]

[Table 5]

[0029]

[Table 6]

[0029]

According to the semiconductor device of the present invention, it is possible to provide a resin package semiconductor chip having a chip size capable of guaranteeing stable electrical conductivity and seal against severe heat stress.

[Brief description of drawings]

FIG. 1 is an explanatory view showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is an explanatory view showing an embodiment of a semiconductor device according to the present invention which is different from the above.

FIG. 3 is an explanatory diagram showing a work procedure of a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is an explanatory view showing another embodiment of the semiconductor device according to the present invention which is different from the above.

FIG. 5 is an explanatory view showing an embodiment of a different semiconductor device according to the present invention which is different from the above.

FIG. 6 is an explanatory view showing an embodiment of a different semiconductor device according to the present invention which is different from the above.

FIG. 7 is an explanatory diagram showing a conventional example.

[Explanation of symbols]

 1 Semiconductor Chip 11 Electrode of Semiconductor Chip 2 Auxiliary Wiring Board Piece 21 Inner Electrode 211 Metal Bump 212 Hole 213 Filling Metal 22 Outer Electrode 221 Hole 222 Filling Metal 223 Metal Bump 23 Internal Routing Conductor 24 Insulating Layer 25 Insulating Layer 3 Sealing Resin

(72) Inventor Nobuhiko Yoshio 1-2-2 Shimohozumi, Ibaraki City, Osaka Prefecture Nitto Denko Corporation (72) Hideyuki Usui 1-2 1-2 Shihohozumi, Ibaraki City, Osaka Nitto Denko Stock In-house (72) Inventor Kuki Ito 1-2 1-2 Shimohozumi, Ibaraki City, Osaka Prefecture Nitto Denko Corporation

Claims (2)

[Claims] 1. An insulating plate is provided with an inner electrode connected to an electrode of a semiconductor chip, an outer electrode connected to a conductor end of a mounted circuit board, and an inner lead conductor extending between these electrodes. The electrode of the auxiliary wiring board is formed by a metal filled in a hole reaching the drawn conductor from one surface of the insulating plate and a metal bump protruding from the hole, and at least the surface of the metal bump is Au. A metal bump is bonded to the Al electrode of the semiconductor chip, a resin is sealed between the semiconductor chip and the auxiliary wiring board piece, and the insulating plate surface of the auxiliary wiring board piece in contact with the sealing resin has a depth of 0. 00
A semiconductor device having an uneven surface of 5 μm to 0.5 μm. 2. An insulating plate is provided with an inner electrode connected to an electrode of a semiconductor chip, an outer electrode connected to a conductor end of a mounted circuit board, and an in-insulating plate leading conductor extending between these electrodes. An auxiliary wiring board piece in which the inner electrode is formed by a metal filled in a hole reaching the drawn conductor from one surface of the insulating plate and a metal bump protruding from the hole, and at least the surface of the metal bump is Au. The metal bumps are bonded to the Al electrodes of the semiconductor chip, the space between the semiconductor chip and the auxiliary wiring board piece is sealed with resin, and the surface tension of the insulating plate surface in contact with the sealing resin of the auxiliary wiring board piece Is 35 mJ / m ² or more.