JPH096816A - Wiring board design device - Google Patents

Abstract

PURPOSE: To provide a wiring board design device which can check a wiring inhibited area set through all the layers of a wiring plate by a manufacture process, a mounting method for electronic components, etc., and data on arranged wires coming into contact with the wiring inhibited area. CONSTITUTION: This device is equipped with an input part 1, a component data storage part 2, a connection information storage part 3, a design condition storage part 4, a wiring process part 5 which outputs arranged wiring data, a check area information storage part 10 which stores information on the wiring inhibited area, a memory expansion process part 6 which expands the arranged wire data and information on the wiring inhibited area on a memory, a three- dimensional data check process part 11 which checks contact between the arranged wiring data expanded on the memory and the wiring inhibited area, an error report display part 8 which displays a wiring decided as an error by the three-dimensional data check process part 11 as a report, and an error two-dimensional display part 9 which displays the wiring decided as the error by the three-dimensional data check process part 11 in two dimensions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board designing device having a contact check function between a wiring prohibited area and placement / wiring data in a multilayer printed wiring board and an MCM board.

[0002]

2. Description of the Related Art A conventional wiring board design device is, for example, a RAC
VISUALAEXPERT3 of AL REDAC.
According to the wiring board designing apparatus of No. 0, it is performed as follows (On-Line Documentation).
Expert 3.0).

FIG. 19 shows an example of a device for designing a printed wiring board (hereinafter referred to as a board) using the conventional layout and wiring design CAD system (hereinafter referred to as CAD). Since there is no function to check the contact between the placement / wiring data through all the layers of the board and the prohibited area (hereinafter, 3D data check), here is the placement / wiring data check (hereinafter, 2D data check) for each layer of the board. ) Explain the function. In the figure, 10
Reference numeral 1 is an input unit for inputting information using a keyboard and mouse, 102 is a component data storage unit for storing component data to be placed on a board stored in CAD, and 103 is a component stored in the component data storage unit 102. A connection information storage unit that stores connection information between the two, a reference condition storage unit 104 that stores design conditions such as a layer configuration of the substrate and a distance between wirings,
Reference numeral 5 denotes a wiring processing unit that performs wiring between components based on information from the input unit 101, the component data storage unit 102, the connection information storage unit 103, and the design condition storage unit 104, and 106 denotes the wiring processing unit 10.
5 is a memory expansion processing unit that expands the layout and wiring data output from the memory board of the computer for each layer of the board, and 107 is a design condition storage unit in the layout and wiring data expanded by the memory expansion processing unit 106 on the memory. A two-dimensional data check processing unit that checks the layout and wiring data that contacts the wiring prohibited area of the substrate stored in 104, and an error report display unit 108 that displays a report of the wiring determined to be an error by the two-dimensional data check processing unit 107 , 109 are error two-dimensional image display units for two-dimensionally displaying the wirings judged to be in error by the two-dimensional data check processing unit 107.

FIG. 20 shows input information of electronic components input to the component data storage unit 102 by the input unit 101. 11
Reference numeral 3 denotes outer shape information of electronic components mounted on the substrate, 114 and 115 horizontal and vertical lengths of input / output terminals (hereinafter, PAD) of electronic components made of a conductor on the substrate, 112.
Is the origin of the electronic component set at the lower left of the component outline, 110 is the distance in the X direction from the origin of the PAD of the electronic component, and 111 is the distance in the Y direction from the origin of the PAD of the electronic component.

FIG. 21 shows a wiring process performed by the wiring processing unit 105. In the figure, 123 is the outline of the board to be designed, 118 is the board origin set at the lower left of the board, and all subsequent design work is done at this board origin 1.
18 is the center of coordinates. Reference numerals 121 and 122 denote electronic components stored in the component data storage unit 102. 116
And 117 are the distances in the X and Y directions from the substrate origin of the electronic components arranged on the substrate, respectively, which are input as two-dimensional coordinate values of (116, 117) from the input unit 101.
Reference numeral 119 is connection information between PADs of electronic components, which is stored in the connection information storage unit 103. Reference numeral 120 denotes a conductor wiring generated as a result of wiring processing of the connection information 119 between PADs by the wiring processing unit 105.

FIG. 22 shows the design conditions of the board which are input to the design condition storage unit 104 by the input unit 101 and used for the two-dimensional data check. Reference numeral 129 is a PAD of an electronic component made of a conductor on the substrate, and 130 is a P of the electronic component.
Wiring of a conductor generated as a result of wiring processing of the connection information 119 between AD 129 by the wiring processing unit 105, 13
Reference numeral 1 is a VIA of a conductor used to connect the layers of the substrate when the connection information 119 between the PADs 129 of the electronic components is wired by the wiring processing unit 105, 124 is a gap between the wiring 130 and the PAD 129 (hereinafter, GAP), 125 is wiring 1
30 is a GAP between the VIA 131, 126 is a GAP between a signal wiring 130 and another signal wiring 120, 127 is a GAP between the VIA 131 and PAD 129, and 128 is a VI.
It is a GAP of A131 and VIA131.

FIG. 23 shows how the layout and wiring data output from the wiring processing unit 105 is expanded on the memory by the memory expansion processing unit 106. FIG. 23A shows the layout and wiring data output from the wiring processing unit 105. A minimum unit length grid (hereinafter, referred to as a grid) 134 is fixed by the board design apparatus. FIG. 23 (B)
Shows the array set on the memory for storing the layout and wiring data. 132 is the length per unit in the row direction of the array (unit length of the row), and 133 is 1 in the column direction
It is the length per unit (hereinafter, the unit length of the column). In the layout and wiring data output from the wiring processing unit 105,
Wiring 130 / PAD129 / VIA131 "1" is assigned to the unit of the array corresponding to the grid 134 having the data.
Is stored in the wiring 130 / PAD129 / VIA131
If there is no data, "0" is stored.

In FIG. 24, the design condition of the board stored in the design condition storage unit 104 and the layout and wiring data expanded on the memory by the memory expansion processing unit 106 are checked and the error result is displayed as a report. Is.

In FIG. 25, the board design conditions stored in the design condition storage unit 104 and the layout and wiring data expanded on the memory by the memory expansion processing unit 106 are checked, and the error result is displayed as a two-dimensional image. It was done.
135 is an error code.

When the two-dimensional data check of the layout and wiring data of the board is performed under the board design condition shown in FIG. 22 by using the designing apparatus as shown in FIG. 19, the procedure will be described below.

Using the input unit 101, the component data storage unit 1
In 02, information of electronic parts used for board design is input.
The input information includes the name of the electronic component, the outer shape 113 of the electronic component, the horizontal size 114 and the vertical size 115 of the PAD 129 created to mount the electronic component on the board, and the PAD 129 of the electronic component from the lower left origin 112 of the outer shape of the electronic component. It is a two-dimensional coordinate position (110, 111).

Using the input unit 101, the connection information storage unit 10
In 3, the information on the connection relationship between the PADs 129 of the electronic components used for the board design is input. The information input to the connection information storage unit 103 is the logic or function of the board to be designed.

Using the input unit 101, the design condition storage unit 10
The board design conditions such as the layer structure of the board to be designed and the wiring intervals of the layers for wiring signals are input. FIG. 22 shows the design condition of the board used for the two-dimensional data check input to the design condition storage unit 104.

The component data of the component data storage unit 105,
Using the board design conditions of the design condition storage unit 104, the two-dimensional coordinate data of the electronic component on the board is input from the input unit 101, and the electronic component is placed on the substrate.

Wiring between the PADs 129 of the electronic components is performed in the wiring processing unit 105 using the arrangement information of the electronic components on the board and the connection relation information between the electronic components in the connection information storage unit 103. The wiring processing performed by the wiring processing unit 105 is shown in FIG.
Shown in

After the wiring processing unit 105 performs the wiring processing of the connection relation information stored in the connection information storage unit 103 between all the electronic components, the memory development processing unit 106 stores the placement and wiring data for each layer on the memory. Expand to. FIG. 23 shows the memory expansion processing performed by the memory expansion processing unit 106. In FIG. 23, the wiring 130 and the VIA 131 are generated as the placement and wiring data output from the wiring processing unit 105. Hereinafter, description will be made with reference to FIG. 23 as an example.

The two-dimensional data check processing unit 107 checks the layout and wiring data output from the memory development processing unit 106 according to the board design conditions stored in the design condition storage unit 104.

The GAP 125 of the wiring 130 and the VIA 131 of the board design condition stored in the design condition storage unit 104.
Wiring 130 in the placement and wiring data of FIG.
When the GAP value between the VIA 131 and the VIA 131 is small, a two-dimensional check error occurs.

When an error is found by the two-dimensional data check processing unit 107, an error display as shown in FIGS. 24 and 25 is displayed.

[0020]

In the conventional wiring board designing apparatus, only the design condition is checked for each layer of the wiring board, and it is set through all layers of the wiring board depending on the manufacturing process and the mounting method of electronic parts. It was not possible to check the wiring prohibited area and the placement and wiring data that touches it.

In addition, in the data format of the placement and routing data, the shape of the placement and routing and the coordinate values that generate it are described separately, and the duplicated description of data is allowed, thereby increasing the amount of data and processing the data. There was a problem such as an increase in time.

Further, since the error display is a text and a two-dimensional image, it is not possible to intuitively grasp the structural defect portion of the wiring board.

In order to solve the above-mentioned problems, the present invention can check the wiring prohibited area set through all layers of the wiring board by the manufacturing process and the mounting method of electronic parts and the placement and wiring data in contact therewith. Therefore, it is an object of the present invention to provide a wiring board designing device that reduces the amount of memory and the amount of data of a computer device used at the time of checking and makes it easy to visually recognize an error.

[0024]

According to a first aspect of the present invention, there is provided a wiring board designing apparatus, wherein a wiring prohibited area is set through all layers of the wiring board by a manufacturing process, a mounting method of electronic components, and the like, and wiring is arranged for each layer of the wiring board. The feature is that the contact between the wiring prohibited area and the wiring data of each layer is detected by expanding the data in the array created in the memory of the computer and taking the sum of the array of the wiring prohibited area and the wiring data of each layer. And

According to a second aspect of the present invention, there is provided a wiring board designing apparatus, wherein a wiring prohibited area is set through all layers of the wiring board according to a manufacturing process, a mounting method of electronic components, etc., and an arrangement for each layer of the wiring board output from the wiring processing section. It is possible to detect the contact between the wiring prohibited area and the wiring data of each layer by expanding the wiring data into the array created in the memory of the computer and taking the sum of the array of the wiring prohibited area and the wiring data of each layer. Characterize.

According to another aspect of the present invention, a wiring board designing apparatus generates placement and wiring data from manufacturing data of a designing apparatus other than this designing apparatus, and detects contact between the wiring prohibited area and the wiring data of each layer similar to the above. It is characterized by being able to do.

According to a fourth aspect of the present invention, a wiring board designing apparatus is capable of converting the layout and wiring data format into a data format which can express the layout and wiring shape and coordinate values together and which does not allow duplication of data. Characterize.

According to a fifth aspect of the present invention, a wiring board designing apparatus is characterized in that the layout and wiring data is subdivided into a matrix and an array capable of storing the subdivided data is created on a memory.

According to a sixth aspect of the present invention, a wiring board designing apparatus is characterized in that the layout and wiring data is subdivided into a raster shape, and an array capable of storing the divided data is created on a memory.

According to a seventh aspect of the present invention, there is provided a wiring board designing apparatus for generating only wiring prohibited area information set from the design condition storage unit through all layers of a wiring board by a manufacturing process, a mounting method of electronic components, or the like. To do.

A wiring board designing apparatus according to an eighth aspect of the present invention is characterized in that the place where the check error occurs is displayed as a three-dimensional image.

[0032]

According to the wiring board designing apparatus of the present invention, the wiring prohibited area set through all layers of the wiring board by the manufacturing process, the mounting method of electronic parts, etc. and the placement and wiring data for each layer of the wiring board are stored in the memory of the computer. The contact between the wiring prohibited area and the wiring data of each layer is detected by developing the created array and summing the arrangement of the wiring prohibited area and the wiring data of each layer.

According to a second aspect of the present invention, there is provided a wiring board design apparatus in which a wiring prohibited area is set through all layers of the wiring board by a manufacturing process, a mounting method of electronic components, etc. The contact between the wiring prohibited area and the wiring data of each layer is detected by expanding the data into an array created on the memory of the computer and taking the sum of the array of the wiring prohibited area and the array of the wiring data of each layer.

A wiring board designing apparatus according to a third aspect of the present invention generates layout wiring data from manufacturing data of a designing apparatus other than this designing apparatus, and detects contact between the wiring prohibited area and the wiring data of each layer similar to the above. To do.

A wiring board designing apparatus according to a fourth aspect of the present invention converts the layout and wiring data format into a data format capable of expressing the layout and wiring shape and coordinate values together and not allowing duplication of data.

In the wiring board designing apparatus of the fifth aspect, the layout and wiring data is subdivided into a matrix, and an array capable of storing the divided data is created on the memory.

According to a sixth aspect of the wiring board designing apparatus, the layout and wiring data is subdivided into a raster shape, and an array capable of storing the divided data is created in the memory.

According to a seventh aspect of the present invention, the wiring board designing apparatus generates only the wiring prohibited area information set from the design condition storage unit through all the layers of the wiring board according to the manufacturing process, the mounting method of electronic components, and the like.

The wiring board designing apparatus according to the present invention displays the location where the check error has occurred in a three-dimensional image.

[0040]

【Example】

Embodiment 1 FIG. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is an example of a board design apparatus described in the first embodiment. In the figure, 1 is an input unit for inputting information using a keyboard and mouse, 2 is a component data storage unit for storing component information arranged on a substrate, and 3 is a component stored in the component data storage unit 2. A connection information storage unit for storing connection information between the four, a design condition storage unit for storing design conditions such as a board layer configuration and a distance between wirings, and an input unit 1, a component data storage unit 2, a connection information storage unit. The wiring processing unit 10 for wiring between parts based on the information of the unit 3 and the design condition storage unit 4 is a PA.
D, a check area information storage unit that stores information about the increase in the prohibited area for each wiring layer for each VIA of the conductor used to connect the layers of the wiring and the substrate, and 6 is an arrangement output from the wiring processing unit 5. The wiring and the memory expansion processing unit that expands the prohibited area increase information stored in the check area information storage unit 10 on the memory of the computer, respectively 11 checks the data output from the memory expansion processing unit 6 3 Dimensional data check processing unit, 8 is an error report display unit that displays a report of wiring determined to be an error by the three-dimensional data check processing unit 11, and 9 is an error display of wiring that is determined to be an error by the three-dimensional data check processing unit 11. This is an error two-dimensional image display unit.

FIG. 2 shows a VI used for connection between GND wiring layers.
The example of the structure of A is shown. In FIG. 2, 17 is CO
MP layer, 18 is S1 layer, 19 is S2 layer, 20 is VCC
The layer 21, 21 is a GND layer, and the COMP layer 17, the S1 layer 18, and the S2 layer 19 are layers for signal wiring, and the VCC layer 20.
Is a power supply layer for + 5V power supply, and the GND layer 21 is a power supply layer for 0V power supply. 22 is a VI used for interlayer connection
A, 23 is PAD, 24 is between VIA 22 or VI
It is a wiring that connects A22 and PAD23.

FIG. 3 is a top view of FIG. Corresponding parts in FIG. 3 and FIG. 2 are designated by the same reference numerals. In FIG. 3, 25 is an increase in the prohibited area for the VIA 22, and 25 is an increase in the prohibited area for the VIA 22.
Is stored in the check area information storage unit, 26 is an increase amount of the prohibited area generated for the PAD 23, and 27 is an increase amount of the prohibited area generated for the wiring 24.

FIG. 4 shows the layout and wiring data obtained by adding the prohibited area increase information stored in the check area information storage unit 10 to the GND layout and wiring data output from the wiring processing unit 5 in the memory expansion processing unit 6. An example of expansion to memory is shown. Reference numeral 31 is a GND output from the wiring processing unit 5.
Placement / wiring data obtained by adding the prohibited area increase information stored in the check area information storage unit 10 to the placement / wiring data, 30 is a grid, and 32 is an array set on the memory for storing the placement / wiring data (hereinafter, Array), 28 is the unit length of the row, and 29 is the unit length of the column.

FIG. 5 shows that in the memory expansion processing section 6, the GND placement and wiring data is deleted from the result of the wiring processing section 5,
9 shows an example of expansion of placement and routing data, which is separated for each wiring layer, into a memory. In FIG. 5, reference numeral 33 denotes placement and routing data obtained by deleting the placement and routing data of GND from the result of the wiring processing unit 5 and separating the wiring layers.

FIG. 6 shows the result of summing the check area information and the layout and wiring data developed into the array created on the memory by the memory development processing unit 6 in FIGS. 4 and 5.

FIG. 7 shows an output example of the error report display section 8.

FIG. 8 shows an output example of the error two-dimensional image display section. In FIG. 8, 34 is a three-dimensional data check error location.

When a three-dimensional data check is performed using the design apparatus as shown in FIG. 1 for the wiring prohibited area generated by the GND wiring and wiring and the wiring and wiring data for other signals (general signals). The procedure will be described below with reference to FIGS. 1, 2, 3, 4, 5, 6, 7, and 8.

The input unit 1, the component data storage unit 2, the connection information storage unit 3, the design condition storage unit 4, and the wiring processing unit 5 in FIG.
The description is omitted because it is similar to that of the conventional device.

The wiring data output from the wiring processing unit 5 is the COMP layer 17, S1 layer 18, and S2 layer 1 shown in FIG.
9 and the VCC layer 20 and the GND layer 21.

The input area 1 causes the check area information storage section 10 to increase the prohibited area increase 2 for the VIA 22.
5 and the prohibited area increase 26 generated for the PAD 23 and the prohibited area increase 27 generated for the wiring 24 are stored.

By the memory expansion processing unit 6, the wiring processing unit 5
An array capable of storing the layout and wiring data output by is created in the memory, and the wiring prohibited area increase information stored in the check area information storage unit 10 is added to the layout and wiring data output by the wiring processing unit 5, Save to array.
Specifically, each grid 30 has placement / wiring data 31 obtained by adding placement / wiring data of the GND signal output from the wiring processing unit 5 to the prohibited area increase information stored in the check area information storage unit 10. If so, "1" is stored in the unit of the array 32 corresponding to that grid, and if it does not exist, "0" is stored. FIG. 4 shows the results.

The layout / wiring data of the GND signal is deleted from the layout / wiring data output from the wiring processing unit 5, the layout / wiring data is divided for each layer, and the memory expansion processing unit 6 creates an array corresponding to each.

The layout / wiring data divided for each layer is expanded by the memory expansion processor 6 into an array created on the memory by the same means as described above. Results are shown in FIG.

The array for storing the layout and wiring data for each layer output from the memory expansion processing section 6 and the array for storing the wiring prohibited area information are input to the three-dimensional data check processing section 11.

FIG. 6 shows the result of summing the input arrays in the three-dimensional data checking unit 11. In FIG. 6, the unit whose stored value is “2” indicates the position of the wiring data included in the wiring prohibited area, that is, the error portion.

The error report display unit 8 receives the result of the three-dimensional data check processing unit 11 as an input and displays an error report as shown in FIG.

The error two-dimensional image display section 9 receives the result of the three-dimensional data check processing section 11 as an input and displays the three-dimensional data check error location 34 by a two-dimensional image as shown in FIG.

According to this embodiment, the wiring prohibited area set through all the layers of the wiring board by the manufacturing process and the mounting method of the electronic parts and the placement and wiring data for each layer of the wiring board are created in the memory of the computer. The contact between the wiring prohibited area and the wiring data of each layer is detected by expanding the array and the sum of the wiring prohibited area and the wiring data of each layer is detected, and wiring is performed according to the manufacturing process and the mounting method of electronic parts. It is possible to check the contact between the wiring prohibited area set through all the layers of the board and the layout and wiring data of the wiring board.

Example 2. Embodiment 2 of the present invention will be described below with reference to the drawings. Since the portions of the second embodiment that are the same as those of the first embodiment have the same functions, the description thereof will be omitted.

In FIG. 9, reference numeral 12 is an external design data interface for converting the external design data into the same data format as the output data of the wiring processing section 5. With the external design interface 12, it is not necessary to use the component data storage unit 2, the connection information storage unit 3, the design condition storage unit 4, and the wiring processing unit 5 of the first embodiment.

A procedure for performing a three-dimensional data check between the prohibited area generated by the GND layout data and the layout data of other signals will be described below with reference to FIG.

Using the input unit 1, the external design data is connected to GND.
The data obtained by extracting the placement and routing data of No. 2 and the data obtained by removing the placement and routing data of GND from the external design data and separating each wiring layer are input to the external design data interface 12. The external design data interface 12 converts the input data format into the output data format of the wiring processing unit 5 in the first embodiment.

The subsequent processing is the same as in the first embodiment.

According to this embodiment, by supporting a standardized data format such as manufacturing data,
With respect to the layout and wiring data of the wiring board designed by a designing device other than this designing device, it is possible to perform contact check between the wiring prohibited area and the wiring data of each layer as in the first embodiment.

Example 3. The third embodiment of the present invention will be described below with reference to the drawings. Example 1 or Example 2 of Example 3
The description of the same function is omitted because it has the same function.

In FIG. 10, 13 is a wiring processing section 5 or a data structuring processing section for structuring the layout and wiring data output from the external design data interface 12. In FIG. 11, FIG. 11A shows the layout and wiring data as it is, and FIG. 11B shows the layout and wiring data converted into rectangular data. In the figure,
Reference numeral 35 is wiring, 36 is PAD, 37 is VIA, and 38 is line data, and is composed of thickness, starting point coordinates, and ending point coordinates. 3
Reference numeral 9 is rectangular data, which is composed of center coordinates, width, and height.

In the third embodiment, the wiring processing unit 5 in the first embodiment or the data structuring processing unit 13 for structuring the output data of the external design data interface 12 in the second embodiment is added.

Using this designing apparatus, a procedure for performing a three-dimensional data check between the prohibited area generated by the GND layout and wiring data and the layout and wiring data of other signals will be described with reference to FIGS. It is shown below.

The layout and wiring data output from the wiring processing unit 5 or the external design data interface 12 is input to the data structuring processing unit 13. Data structuring processor 13
Then, the wiring 35 of the input placement and wiring data is replaced with the line data 38 including the thickness, the starting point coordinates, and the ending point coordinates, and PA
D36 and VIA 37 are replaced with rectangular data 39 having center coordinates, width, and height.

The subsequent processing is the same as in the first or second embodiment.

According to this embodiment, the format of the layout and wiring data can be expressed by combining the layout and the shape of the layout and wiring, and the data can be saved in a data format that does not allow duplication of data, thereby reducing the amount of data. There is an effect that can be done.

Example 4. Embodiment 4 of the present invention will be described below with reference to the drawings. Example 1 or Example 2 of Example 4
Alternatively, since the same parts as those in the third embodiment have the same functions, the description thereof will be omitted.

In FIG. 12, reference numeral 14 is a matrix division processing unit for subdividing the layout and wiring data output from the wiring processing unit 5, the external design data interface 12, or the data structuring processing unit 13 into a matrix.
In FIG. 13, reference numeral 40 is placement / wiring data for the entire substrate, 4
Reference numeral 1 is a grid that divides the substrate into a certain area (hereinafter referred to as matrix grid), and 42 is placement and wiring data included in one matrix grid.

In the fourth embodiment, the wiring processing unit 5, the external design data interface 12, or the data structuring processing unit is used as the preprocessing of the memory expansion processing unit 6 in the first, second, or third embodiment. A matrix division processing unit 14 is added to divide the layout and wiring data output from 13 into a matrix.

12 and 13, the procedure for performing a three-dimensional data check between the prohibited area generated by the GND layout and wiring data and the layout and wiring data of other signals using this designing apparatus will be described with reference to FIGS. It is shown below.

The layout / wiring data 40 for the entire substrate output from the wiring processing unit 5, the external design data interface 12, or the data structuring processing unit 13 is input to the matrix division processing unit 14. Matrix division processing unit 1
The matrix grid 41 subdivides the layout and wiring data 40 of the entire substrate by the matrix grid 41, and outputs the layout and wiring data 42 included in one matrix grid to the memory expansion processing unit 6. The arrangement / wiring data 42 included in one matrix grid and the wiring prohibited area information corresponding to the matrix grid are expanded into an array by the memory expansion processing unit 6. The layout and wiring data and wiring prohibited area information included in one matrix lattice stored in the array are input to the three-dimensional data check processing unit 11. After the processing of the three-dimensional data check processing unit 11 is completed,
The layout and wiring data included in the next one matrix grid and the wiring prohibited area information corresponding to the matrix grid are sequentially checked.

The processes of the three-dimensional data check processing unit 11, the error report display unit 8 and the error two-dimensional image display unit 9 are the same as those in the first embodiment.

According to this embodiment, the layout and wiring data is subdivided into a matrix, and only the array capable of storing the divided data is created in the memory. Therefore, the memory pressure of the computer is prevented and the check processing speed is high. Has the effect of

Example 5. Embodiment 5 of the present invention will be described below with reference to the drawings. Example 1 or Example 2 of Example 5
Alternatively, since the same parts as those in the third embodiment have the same functions, the description thereof will be omitted.

In FIG. 14, reference numeral 15 is a raster division processing unit for subdividing the layout / wiring data output from the wiring processing unit 5, the external design data interface 12, or the data structuring processing unit 13 into a raster shape. FIG.
In FIG. 5, reference numeral 40 is placement and wiring data of the entire substrate, 43 is a line dividing the substrate into a certain area (hereinafter, raster dividing line), and 44 is included in a region divided by the raster dividing line (hereinafter, raster dividing region). Placement and wiring data.

The fifth embodiment is a wiring processing unit 5, an external design data interface 12, or a data structuring processing unit as preprocessing of the memory expansion processing unit 11 in the first, second or third embodiment. A raster division processing unit 15 for dividing the output data of 13 into a raster shape is added.

14 and 15, the procedure for performing a three-dimensional data check between the prohibited area generated by the GND placement and routing data and the placement and routing data of other signals using this designing apparatus will be described with reference to FIGS. It is shown below.

The layout / wiring data 40 for the entire board output from the wiring processing unit 5, the external design data interface 12, or the data structuring processing unit 13 is input to the raster division processing unit 15. Raster division processing unit 15
Is a layout dividing line 43 for the placement / wiring data 40 of the entire board output from the wiring processing unit 5, the external design data interface 12, or the data structuring processing unit 13.
The placement / wiring data 44 included in one raster division area is output to the memory expansion processing unit 6 by. The memory expansion processing unit 6 expands the layout and wiring data 44 included in one raster divided area and the wiring prohibited area information corresponding to the raster divided area into an array. The layout and wiring data and wiring prohibited area information included in one raster division area stored in the array are input to the three-dimensional data check processing unit 11. After the processing of the three-dimensional data check processing unit 11 is completed, the placement / wiring data included in the next raster divided area and the wiring prohibited area information corresponding to the raster divided area are sequentially checked.

The processes of the three-dimensional data check processing unit 11, the error report display unit 8 and the error two-dimensional image display unit 9 are the same as in the first embodiment.

According to this embodiment, the layout and wiring data is subdivided into rasters, and only the array capable of storing the divided data is created in the memory. Therefore, the memory pressure of the computer is prevented and the check processing speed is high. Has the effect of

Example 6. Embodiment 6 of the present invention will be described below with reference to the drawings. Example 1 or Example 3 of Example 6
Further, since the same parts as those in the fourth and fifth embodiments have the same functions, the description thereof will be omitted.

In FIG. 16, 16 is the design condition storage unit 4.
The check area information storage unit 10 extracts the prohibited area increase 25 for the VIA 22, the prohibited area increase 26 for the PAD 23, and the prohibited area increase 27 for the wiring 24 from the information stored in the check area information storage unit 10. It is a check area information automatic generation processing unit that outputs the information.

Check area information automatic generation processing unit 16
Is applicable only when the design condition storage unit 4 is provided in the first embodiment, the third embodiment, the fourth embodiment, or the fifth embodiment.

The check area information automatic generation processing unit 16 increases the prohibited area 25 / PAD 23 generated for the VIA 22 from the information such as the layer structure of the substrate and the GAP between the signal wirings stored in the design condition storage unit 4. The forbidden area increase 26 that occurs with respect to / the prohibited area increase 27 that occurs with respect to the wiring 24 are automatically generated, and the information is output to the check area information storage unit 10.

The other processes are the same as those in the above-described embodiment.

According to this embodiment, the wiring prohibited area information which is set through all the layers of the wiring board by the manufacturing process, the mounting method of the electronic components, etc. is automatically generated from the design condition storage unit, so that the human input error can be reduced. It has the effect of reducing the information creation time.

Example 7. Embodiment 7 of the present invention will be described below with reference to the drawings. The seventh embodiment can be applied to all the above-mentioned embodiments. Since the same parts as those in the other embodiments have the same functions, the description thereof will be omitted.

In FIG. 17, reference numeral 17 is an error three-dimensional image display unit for three-dimensionally displaying an error in the wiring judged to be an error by the three-dimensional data check processing unit 11. FIG.
Is an output example of the error three-dimensional image display unit 17. FIG.
In the figure, 34 is a three-dimensional data check error location.

Using this design apparatus, the procedure for performing a three-dimensional data check between the prohibited area generated by the GND layout and wiring data and the layout and wiring data of other signals will be described with reference to FIGS. 17 and 18. It is shown below.

The error three-dimensional image display section 17 receives the result of the three-dimensional data check processing section 11 as an input and displays the three-dimensional data check error location 34 by the three-dimensional image as shown in FIG.

According to this embodiment, since the location where the check error occurs is displayed in a three-dimensional image, it is easy to visually recognize the location of the error.

[0098]

According to the wiring board design apparatus of the present invention, the contact between the wiring prohibited area set through all layers of the wiring board and the layout wiring data of the wiring board is checked by the manufacturing process, the mounting method of the electronic components, and the like. It is possible.

According to a second aspect of the present invention, there is provided a wiring board designing apparatus, which includes a wiring prohibited area set through all layers of the wiring board by a manufacturing process, an electronic component mounting method, and the like, and wiring board layout and wiring data output from a wiring processing unit. It is possible to check the contact of.

The wiring board designing apparatus according to claim 3 corresponds to the standardized data format such as the manufacturing data so that the layout and wiring data of the wiring board designed by the designing apparatus other than this designing apparatus is the same as the above. It is possible to check the contact between the wiring prohibited area and the wiring data of each layer.

According to the wiring board designing apparatus of the present invention, the amount of data can be reduced by expressing the layout and wiring data by combining the layout and the shape of the layout and the coordinate values, and storing the layout and wiring data in a format that does not allow duplication of data. effective.

According to the wiring board designing apparatus of the present invention, the layout and wiring data is subdivided into a matrix, and only an array capable of storing the divided data is created in the memory. It has the effect of increasing the speed.

The wiring board design apparatus according to claim 6 subdivides the layout and wiring data into rasters and creates only the array capable of storing the divided data on the memory. It has the effect of increasing the speed.

Since the wiring board design apparatus of the present invention automatically generates wiring prohibited area information set from all the layers of the wiring board from the design condition storage unit according to the manufacturing process, the mounting method of electronic components, etc., it is manually input. It has the effect of reducing mistakes and information creation time.

According to the wiring board designing apparatus of the eighth aspect, since the location of the check error is displayed in a three-dimensional image, it is easy to visually recognize the location of the error.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a wiring board design device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a GND signal wiring structure of a wiring board designing device according to a first embodiment of the present invention.

FIG. 3 is a top view showing the wiring structure of the GND signal of the wiring board designing device according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a memory expansion process of a wiring prohibited area of the wiring board designing device according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a memory expansion process of layout and wiring data of the wiring board designing apparatus according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a result of the sum of FIGS. 4 and 5 of the wiring board designing device according to the first embodiment of the present invention.

FIG. 7 is a diagram showing an example of an error report displayed on the error report display unit of the wiring board design device according to the first embodiment of the present invention.

FIG. 8 is a diagram showing an example of an error two-dimensional image displayed on the error two-dimensional image display unit of the wiring board designing device according to the first embodiment of the present invention.

FIG. 9 is a configuration diagram showing a wiring board designing device according to a second embodiment of the present invention.

FIG. 10 is a configuration diagram showing a wiring board designing device according to a third embodiment of the present invention.

FIG. 11 is a diagram showing a processing result of a data structuring processing unit of a wiring board designing device according to a third embodiment of the present invention.

FIG. 12 is a configuration diagram showing a wiring board designing device according to a fourth embodiment of the present invention.

FIG. 13 is a diagram showing a processing result of matrix division processing of a wiring board designing device according to a fourth embodiment of the present invention.

FIG. 14 is a configuration diagram showing a wiring board design device according to a fifth embodiment of the present invention.

FIG. 15 is a diagram showing a processing result of raster division processing of a wiring board designing device according to a fifth embodiment of the present invention.

FIG. 16 is a configuration diagram showing a wiring board design device according to a sixth embodiment of the present invention.

FIG. 17 is a configuration diagram showing a wiring board design device according to a seventh embodiment of the present invention.

FIG. 18 is a diagram showing an example of an error three-dimensional image displayed on the error three-dimensional image display unit of the wiring board designing device according to the seventh embodiment of the present invention.

FIG. 19 is a configuration diagram showing a conventional wiring board design device.

FIG. 20 is a diagram showing parameters input to a component data storage unit of a conventional wiring board design device.

FIG. 21 is a diagram showing an example of wiring processing performed by a wiring processing unit of a conventional wiring board designing device.

FIG. 22 is a diagram showing parameters input to a design condition storage unit of a conventional wiring board design device.

FIG. 23 is a diagram showing an example of memory expansion performed by a memory expansion processing unit of a conventional wiring board design apparatus.

FIG. 24 is a diagram showing an example of an error report displayed on the error report display unit of the conventional wiring board design apparatus.

FIG. 25 is a diagram showing an example of an error two-dimensional image displayed on the error two-dimensional image display unit of the conventional wiring board design apparatus.

[Explanation of reference numerals] 1 input unit, 2 component data storage unit, 3 connection information storage unit, 4 design condition storage unit, 5 wiring processing unit, 6 memory expansion processing unit, 8 error report display unit, 9 error 2D image display Section, 10 check area information storage section, 11
Three-dimensional data check processing unit, 12 external design data interface, 13 data structuring processing unit, 14 matrix division processing unit, 15 raster decomposition processing unit, 16
Check area information automatic generation processing part, 17 error 3
Dimensional image display section.

Claims (8)

[Claims] 1. A wiring board design apparatus for designing a multilayer printed wiring board or the like, which is constructed by laminating a plurality of substrates,
Check area information storage unit that stores information on wiring prohibited areas set through all layers of the wiring board by the manufacturing process and mounting method of parts, etc. Through all wiring board layers stored in the check area information storage unit and layout area data A memory expansion processing unit that expands information on the set wiring prohibited area on the memory of the computer, and the wiring prohibited area that is set through all the layers of the wiring board and the layout wiring data expanded on the memory by the memory expansion processing unit. Check the contact with 3
A wiring board design device equipped with a dimensional data check processing unit. 2. A wiring processing unit for wiring between electronic components based on two-dimensional position information of electronic components mounted on a wiring board and connection information between electronic components and outputting placement and wiring data. Wiring board design device. 3. The wiring board design apparatus according to claim 1, further comprising an external design data interface for converting layout wiring data of a wiring board designed by another wiring board design apparatus into a format usable by this wiring board design apparatus. . 4. A data structuring unit for converting the layout and wiring data output from the wiring processing unit or the layout and wiring data output from the external design data interface into a data format represented by a rectangle and a line. The wiring board design device according to claim 2 or claim 3. 5. The method according to claim 2, further comprising a matrix division processing unit that divides the layout and wiring data output from the wiring processing unit, the external design data interface, or the data structuring processing unit into a matrix. 4. The wiring board design device described in 4. 6. The method according to claim 2, further comprising a raster division processing unit that divides the layout and wiring data output from the wiring processing unit, the external design data interface, or the data structuring processing unit into a raster shape. 4. The wiring board design device described in 4. 7. The wiring board design apparatus according to claim 2, further comprising a check area information automatic generation processing unit that automatically generates wiring prohibited area information set in the wiring board from information stored in the design condition storage unit. 8. The wiring board design apparatus according to claim 1, further comprising an error three-dimensional image display unit that three-dimensionally displays a wiring location determined to be an error by the three-dimensional data check processing unit.