JPH096615A - Information processor - Google Patents

Abstract

PURPOSE: To provide an information processor which avoids the increase of power consumption by allowing the serial access of a register bank memory at the time of bank switching. CONSTITUTION: When a general register set 6 is accessed at the time of instruction execution in a CPU main body part 1, data is written in the general register set 6 as well as in a corresponding address of a register bank memory 2 in the register read operation, and data in the register bank memory 2 is read put without saving data in the general register set 6 to an external memory at the time of register bank switching. In this information processor, a memory part 21 is provided with a precharge circuit 30 for each memory cell block 21a. An address pointer circuit 22 is provided with a serial access switching means to perform the serial access at the time of register bank switching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for accessing data by using a register bank method.

[0002]

2. Description of the Related Art As shown in FIG. 5, an information processing apparatus for performing data access using a register bank system has a CPU.
(Central processing unit) A main unit 1 and a single-port register bank memory 2 are provided. These are a dedicated internal address bus 3 and an internal data bus different from a data bus and an address bus for connection with peripheral devices. 4 and control signal line 5.

The CPU body 1 includes a set of general-purpose register sets (register array) 6 composed of a plurality of registers.
A dedicated register (CBNR) 7 for designating a bank number of the register bank memory 2, a current bank number from the dedicated register 7, and RGSn.
(Register selection control signal) and the bank address buffer 8 for supplying RA0 to RAm to the register bank memory 2, the current bank number and RGSn.
Address circuit 9 to which is input, a decode circuit 10 to which a signal from this address circuit 9 is input, RBCK (control clock), RBCE (memory enable), and RB
An instruction control unit 11 for supplying a signal such as WEB (read / write control) to the register bank memory 2, and RB0 to R
An input / output circuit 12 for exchanging Bn (register data) with the register bank memory 2 is provided.

The above address circuit 9 is the same as the above RGSn.
As shown in FIG. 6, as a portion corresponding to FIG. 6, a circuit including an inverter is provided, and the RGSn is input and its positive / inverted signals (IA0B to IAnB, IA0 to IA0B in the figure).
IAn) is output. Also, the above decoding circuit 10
As shown in FIG. 7, the address circuit 9 comprises a 4-input NAND circuit and a circuit composed of an inverter.
Output (IA0B to IA3B, IA0 to IA3 in the figure)
Is input, and decode signals (RG0 to RG15 in the figure) are output.

The register bank memory 2 includes a memory section 13
And an address circuit 14 for inputting the RA0 to RAm.
And a decoding circuit 15 for inputting the positive / inverted output from the address circuit 14, and the RBCK, RBCE and R
A control circuit 16 for receiving the signal such as BWEB and controlling the address circuit 14 and the like, and an input / output circuit 17 for exchanging the RB0 to RBn with the register bank memory 2.
With.

As shown in FIG. 8, the address circuit 14 is composed of a circuit composed of a NAND circuit and an inverter, and RA0 to RA0 from the bank address buffer 8 are provided.
RAm is input and its positive / inverted signal (IA0B to
IAmB, IA0 to IAm) are output. Input signal RA
0 to RAn correspond to the RGSn in the CPU body 1, and RAn + 1 to RAm correspond to the current bank number from the CBNR7 in the CPU body 1. The signal ICE is supplied from the control circuit 16 and controls the driving of the address circuit 14.

The decoding circuit 15 receives the signal from the address circuit 14 as shown in FIG.
It is composed of an input NAND circuit and NOR circuit, and outputs the address circuit 14 (IA0B to IA4B, IA in the figure).
0-IA4), and decode signals (WL0-WL0 in the figure)
WL31) is output.

As shown in FIG. 10, the memory section 13 comprises a memory cell array section 13a and a precharge circuit 13b, and has a memory space corresponding to the general-purpose register set 6. Then, signals (BL0 to BLm-1, BLB0 to BLBm-) are provided between the decode signal (WL0 to WLn-1 in the figure) and the input / output circuit 17.
Exchange 1). The signal ICKB is supplied from the control circuit 16 and controls precharge.

As shown in FIG. 11, the input / output circuit 17 is provided with a write circuit 17a and the like, and outputs the signals (BL0 to BLm-1, BLB0 to BLBm-1) to and from the memory section 13. While exchanging data, data (RB0 to RB) is exchanged with the input / output circuit 12 of the CPU body 1.
n) are exchanged. The signal IWE is the control circuit 1
6, which controls the read / write.

As shown in FIG. 12, the control circuit 16 is composed of a NAND circuit and an inverter, and the signals RBCK and RBC are output from the instruction control unit 11 on the CPU body 1 side.
E and RBWEB are input, and the control signals ICE and IC described above are input.
Outputs KB and IWE.

The precharge circuit 13 of the memory unit 13
FIG. 13 shows the timing of read / write and precharge of b. The signal RBCK from the CPU body 1 is Lo
When w, the signal ICKB becomes High, and all the memory cells (MC) are precharged. When this signal ICKB is High, WL (see FIG. 9) is not selected. When RBCK becomes High, one of WL0 to WLn-1 is selected according to the address at that time. RBWEB for the memory cell in this state
When is low, IWE becomes High and the write operation is performed, while when RBWEB is High, IW becomes high.
E becomes Low, and the read operation is performed. In addition, RBC
E is fixed to High when accessing the register.

The conventional information processing apparatus adopting the register bank system having the above configuration operates as follows.

When the CPU body 1 executes an instruction, when reading the data in the register, the data in the general-purpose register set 6 is read. At this time, the register bank memory 2 is supplied with the signals RA0 to RAm from the bank address buffer 8 and is in a read state. However, the CPU main body 1 preferentially takes in the read data of the general-purpose register set 6 instead of the read data from the register bank memory 2.

When the CPU main body 1 executes an instruction and writes data in the register, the data is written in the general-purpose register set 6 and at the same time, the same is applied to the memory area of the register bank memory 2 corresponding to the bank number. Write the data. For example, an addition instruction (R2 + R15 → R1
5, add: g. 1 r2, R15),
After the calculation of R2 + R15, at the same time as writing the result to R15, the above result is also written to the area of the register bank memory 2 corresponding to R15.

That is, the register bank memory 2 has the same data as the data in the general-purpose register set 6 in its corresponding area.

Here, in the case of not having the register bank system, in the bank switching, register store (data of the general-purpose register set 6 is saved to the register bank memory 2) is followed by register load (register bank memory 2). Therefore, it is necessary to store the data of the register set of the new bank in the general-purpose register set 6).
However, in the register bank method, the data in the bank before being updated retains the data identity with the general-purpose registers, so there is no need for register store.
There is an advantage that bank switching can be completed only by register loading.

[0017]

However, in the information processing apparatus which performs data access using the conventional register bank method, only random access can be performed at the time of bank switching. As shown in the timing chart, when the signal RBCK from the CPU body 1 is Low, the signal ICKB is High.
Since all the memory cells (MC) are precharged, there is a drawback that the power consumption is large.

In order to prevent an increase in power consumption,
A configuration is known in which bit lines and word lines are divided (see Japanese Patent Publication No. 3-4995, Japanese Patent Publication No. 3-11035, and Japanese Patent Publication No. 3-77399). But,
These conventional techniques have a drawback that the chip area is increased as compared with the case where the bit line or the word line is not divided.

There is also known a technique in which a memory cell is divided into a plurality of blocks and precharging is sequentially performed for each block (see Japanese Patent Laid-Open No. 5-298876). However, such a conventional technique is not used for the register bank method.

In view of the above circumstances, the present invention enables a register bank memory to perform serial access at the time of bank switching in an information processing apparatus of the register bank system, thereby avoiding an increase in power consumption and improving an operating speed. With the goal.

[0021]

An information processing apparatus according to the present invention is provided with a set of general-purpose register sets composed of a plurality of registers in a central processing unit main body, and has a memory area corresponding to the plurality of general-purpose register sets. A register bank memory is connected to the central processing unit main unit by a dedicated internal bus and an internal control signal line, and a register read operation is performed when the general-purpose register set is accessed when the central processing unit main unit executes instructions. While writing the data to the general-purpose register set and the same data to the corresponding address of the register bank memory,
In an information processing device that reads data in a register bank memory without saving data in a general-purpose register set to an external memory when switching register banks, the register bank memory has a memory composed of a plurality of memory cells. It is characterized in that a plurality of cell blocks are provided and each memory cell block is provided with a memory section having a precharge circuit, and a serial access switching means for performing serial access when switching register banks.

Further, in the above structure, an address is generated based on a signal from the counter circuit for supplying a counter value to the serial access switching means and the central processing unit body, and this address is generated by the serial access switching means. The address value of the address circuit may be input to the counter circuit.

Further, in the above structure, during each cycle of data reading by serial access, the precharge circuit of the memory block in which the memory cell to be read in the next cycle exists may be precharged. .

[0024]

According to the above structure, in the information processing apparatus using the register bank system, the serial access switching means can read data by serial access to the register bank memory when switching the register bank. By this serial access, precharging is performed sequentially for each memory block.
The power consumption can be reduced as compared with the case where the precharge is simultaneously performed on all the memory cells. Further, since the address value of the address circuit is inputted to the counter circuit, the serial access mode can be easily set. Further, during each cycle of data reading by the serial access, the memory cell of the block to be read in the next cycle is precharged, so that the operation speed can be increased.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing the embodiments.

FIG. 1 is a block diagram showing the information processing apparatus of this embodiment. The basic configuration of this information processing apparatus is the same as the configuration of FIG. 5 described in the conventional example, and thus the description will be made by appropriately using the diagram used in the conventional example.

The information processing apparatus includes a CPU (central processing unit) main body 1 and a single-port register bank memory 20, which are dedicated and different from a data bus and an address bus for connecting to peripheral devices. Are connected by an internal address bus 3, an internal data bus 4, and a control signal line 5. The CPU body 1 has the same configuration as that of FIG.

The register bank memory 20 includes the memory unit 2
1, an address pointer circuit 22 for inputting RA0 to RAm, a control circuit 23 for receiving signals such as RBCK, RBCE, and RBWEB to control the address pointer circuit 22 and the like, and RB0 to RBn for register bank memory 20. And an input / output circuit 24 for exchanging data between them.

The memory section 21 includes a plurality of memory cells (M
C) are arranged in a matrix having a plurality of columns respectively corresponding to the plurality of read bit lines, and the plurality of memory cells (MC) correspond to the plurality of read bit lines. Memory block 21a
It is divided into ... Then, each memory block 21a
Is provided with a precharge circuit (PRC) 30.

As shown in FIG. 2, the address pointer circuit 22 includes an address circuit 22a and a counter circuit 22b.
, A multiplexer 22c, and a decoding circuit 22d.

The address circuit 22a is composed of a circuit composed of a NAND circuit and an inverter as in FIG. 8 shown in the conventional example, and RA from the bank address buffer 8 is used.
Input 0 to RAm and output the positive / inverted signal.

The counter circuit 22b receives the RBCK from the control circuit 23 and performs a counting operation. Further, an address value is input from the address circuit 22a, and this address value is used as a counter initial value. Further, a signal RBSA 'is input from the control circuit 23a, and the counting operation is executed when the signal RBSA' becomes High. The signal RB
SA 'is High in synchronization with the rising edge of the signal RBSA.
Signal (see FIG. 4). Also, the signal RBSA
Is a signal related to mode selection, and is generated at the time of register bank switching in the instruction control of the CPU main body unit 1. It is Low in the RAM (random access) mode and is low in the SAM (serial access) mode. It becomes High.

The multiplexer 22c selects and outputs either the output from the address circuit 22a or the output from the counter circuit 22b. This selection operation is the same as R
This is done by the BSA signal. That is, the RBSA signal is H
When the output is high, the output of the counter circuit 22b is selected,
When the RBSA signal is low, the output of the address circuit 22a is selected.

The decode circuit 22d is configured to include, for example, a 5-input NAND circuit or NOR circuit as in FIG. 9 shown in the conventional example, and the output of the address circuit 22a,
Alternatively, the output of the counter circuit 22b is input and the decoded signals (denoted by BS _n and WL _n in the figure) are output. The signal BS _n is a signal for selecting a memory block generated by the decoding circuit 22d by inputting the RBSA signal or the like, and is B in the RAM mode.
All of S (BS _{0 to} BS _n ) become High, and SAM
In the mode, all except the BS corresponding to the selected memory block are Low.

FIG. 3 shows the nth precharge circuit 30.
(PRC _n ) and the (n + 1) th precharge circuit 3
It is a circuit diagram showing 0 (PRC _{n + 1} ). In each precharge circuit 30, a 2-input first NAND circuit 30a
The signal RBSA relating to the mode selection and RBSAB which is the inverted signal thereof are input to. Therefore, the first N
The output of the AND circuit 30a is always High.

The output of the first NAND circuit 30a is input to one input terminal of a 2-input second NAND circuit 30b. The block input signal BS from the decode circuit 22d is applied to the other input terminal of the second NAND circuit 30b.
Is entered. Here, the nth precharge circuit 3
The (N−1) th bit line selection signal BS _n−1 is input as the block selection signal BS to the second NAND 30 b of 0 (PRC _n ), and the ( _{n + 1} ) _th precharge circuit 30 (PRC _{n + 1} ) is input. The n-th bit line selection signal BS _n is input to the 2NAND 30b as a block selection signal BS.

The output of the second NAND circuit 30b is inverted by the inverter 30c, and the third NAND circuit 3 having two inputs is inverted.
It is input to one input terminal of 0d. Also, this 3N
The other input terminal of the AND circuit 30d receives the signal ICKB
Is entered. As described in the conventional example, the signal ICKB is a precharge control signal supplied from the control circuit 16, and becomes High when the signal RBCK from the CPU body 1 is Low. Then, the third NAND circuit 30
The output of d is inverted by the inverter 30e and becomes a precharge signal.

As a result, the SAM mode (RBSA = H
In the cycle (bit line selection signal BS _n = High) in which the read operation of the memory cell (MC) belonging to the nth block 21a is performed in (high), the (n + 1) th bit line selection signal BS _n is input. Precharge circuit 30 (PRC _{n + 1} ) of the block, that is, the precharge circuit 30 of the block that is read in the next cycle.
Only the inverter 30 in the third NAND circuit 30d
High is input from c, whereby ICKB which is the precharge control signal is selected, and the precharge operation is performed.

RAM mode (RBSA = Low)
In the above, as described above, the block selection signal BS
Since all of (BS _{0 to} BS _n ) are High, IC
When KB goes high, all memory blocks are precharged.

FIG. 4 is a timing chart showing the operation timing of the register bank memory 20, showing the serial mode. In the mode setting period and each cycle, the clock RBCK alternately repeats the High state and the Low state. Further, since it is in the serial mode, the RBSA is in the High state after the mode setting. PRC _{0 to} PRC ₂ are memory blocks 0 to
The precharge operation of the memory block 2 is shown. The precharge sequentially goes high according to the cycle, and becomes high during the Low period of RBCK in each cycle.

According to the above configuration, in the information processing apparatus using the register bank method, the multiplexer 22c as the serial access switching means can read data by serial access to the register bank memory 20 when switching the register bank. This can be performed, and since the precharge is sequentially performed for each block by this serial access, the power consumption can be reduced as compared with the case where the precharge is simultaneously performed for all the memory cells.

Since the address value of the address circuit 22a is input to the counter circuit 22b, the serial access mode can be set easily. Further, during each cycle of data reading by the serial access, the memory cell (MC) of the block to be read in the next cycle is precharged, so that the operation speed can be increased.

[0043]

As described above, according to the present invention, it is possible to reduce the power consumption, facilitate the setting of the serial access mode, and speed up the operation in the information processing apparatus using the register bank method. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an information processing apparatus of the present invention.

FIG. 2 is a block diagram showing an address pointer circuit of a register bank memory of the information processing apparatus of the present invention.

FIG. 3 is a circuit diagram of a precharge circuit.

FIG. 4 is a timing chart showing the operation of the information processing apparatus of the present invention.

FIG. 5 is a block diagram showing a conventional information processing apparatus.

FIG. 6 is a circuit diagram showing an address circuit on the CPU body side.

FIG. 7 is a circuit diagram showing a decoding circuit on the CPU body side.

FIG. 8 is a circuit diagram showing an address circuit on a register bank memory side.

FIG. 9 is a circuit diagram showing a decode circuit on the register bank memory side.

FIG. 10 is a circuit diagram of a conventional memory unit.

FIG. 11 is a circuit diagram showing an input / output circuit on the register bank memory side.

FIG. 12 is a circuit diagram of a control unit.

FIG. 13 is a timing chart of conventional read / write and precharge.

[Description of Reference Signs] 1 CPU main unit 20 Register bank memory 21 Memory unit 21a Memory block 22 Address pointer circuit 22a Address circuit 22b Counter circuit 22c Multiplexer (serial access switching means) 22d Decoder circuit 23 Control circuit 30 Precharge circuit

Claims (3)

[Claims] 1. A central processing unit main body unit is provided with one set of general-purpose register sets consisting of a plurality of registers, and a register bank memory having a memory area corresponding to the plurality of general-purpose register sets is dedicated to an internal bus and internal control. Connected to the main body of the central processing unit by a signal line,
When accessing the general-purpose register set at the time of executing an instruction by the central processing unit main unit, in the register read operation, data is written to the general-purpose register set and the same data is written to the corresponding address of the register bank memory, and the register bank is switched. In this case, in the information processing device in which the data in the register bank memory is read out without saving the data in the general-purpose register set in the external memory, the register bank memory includes a plurality of memory cell blocks each including a plurality of memory cells. An information processing apparatus, comprising: a memory unit having a precharge circuit in each memory cell block and serial access switching means for performing serial access when switching register banks. 2. A counter circuit for supplying a counter value to the serial access switching means, and an address circuit for generating an address based on a signal from the central processing unit main body and supplying the address to the serial access switching means. 2. The information processing apparatus according to claim 1, further comprising: and an address value of the address circuit being input to the counter circuit. 3. The precharge circuit of a memory block in which a memory cell to be read in the next cycle exists is precharged during each cycle of data read by serial access. Alternatively, the information processing apparatus according to claim 2.