JPH0965461A - Monitor controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a monitor controller with excellent maintenance performance by observing information relating to reset after initializing. SOLUTION: The controller is provided with a central processing unit 5a processing text data and making initializing when being reset, a 1st reset means 5c reset with a first cause, and a 2nd reset means 5d reset with a 2nd cause, a reset cause information storage section 5f storing reset cause information representing which of the 1st or 2nd reset means reset is made. Since the reset cause information storage section stores reset cause information, the reset cause information is observed after reset and whether reset is made by the 1st cause or the 2nd cause is recognized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitor control device for monitoring a terminal device and controlling a load device.

[0002]

2. Description of the Related Art A conventional supervisory control system will be described with reference to FIGS. FIG. 2 is a block diagram showing the configuration of the supervisory control system. FIG. 3 is a block diagram showing an example of the configuration of a conventional monitoring control device.

The supervisory control system shown in FIG.
A monitoring control device 2, a management device 3, and a load device 4.

The terminal 1 is provided at various places in the building and is connected to the state detection sensor 1a. Then, the terminal device 1 detects the on / off state of the state detection sensor 1a.

The load device 4 is provided at various places in the building, and is a lighting device, an air conditioner, a power device, or the like, and is controlled by the monitoring control device 2.

The supervisory controller 2 is provided for each floor or several floors in the building, and executes a plurality of tasks such as sequential collection of data detected by a plurality of terminals 1 and operation control of the load device 4. To do. In addition to the collecting operation, the monitoring control device 2 transmits the collected state data to the management device 3 in response to a request from the management device 3.

The management device 3 manages one or a plurality of supervisory control devices 2. The management device 3 is mainly installed in a central management room of a building or the like, displays state data in a visually easy-to-understand manner, and instructs the monitoring control device 2 to control the load device 4.

By the way, as shown in FIG. 3, the supervisory control device 2 includes a central processing unit (hereinafter referred to as CPU) 2a,
Random access memory (hereinafter referred to as RAM) 2b
And a reset IC 2c corresponding to the first reset means
And a power supply monitoring reset I corresponding to the second reset means.
It is configured to have a C2d and a clock IC2e.

The CPU 2a executes a program for the task of data collection and operation control of the load device 4, and outputs a pulse to the reset IC 2c at a constant cycle during operation, causing a malfunction and hangup. When it does, it does not output a pulse. When the reset signal is input from the reset IC 2c (hereinafter, the input of the reset signal is referred to as reset), the CPU 2a performs the initialization operation, and the power supply monitoring reset IC 2
When reset from d, the initialization operation is performed after a predetermined time. The initialization operation is to erase the stored contents of the RAM 2b and to execute the program of the task which the CPU 2a was processing from the beginning. Although the CPU 2a stops the process at the time of hang-up, the initialization operation can be performed by receiving the reset signal.

The RAM 2b has a "task state" (stop, wait, executable, interrupted, running, runaway stop) for a plurality of tasks executed by the CPU 2a and a "task wait cause" when the task state is "wait". (Waiting for time, waiting for event request, waiting for resource release), "task processing progress" indicating the progress of task processing, task work data,
Memorize the program of the task.

The reset IC 2c has a CP within a fixed period.
If no pulse is input from U2a, it is determined that the CPU2a is hung up, and a reset signal is output to the CPU2a.

The power supply monitoring reset IC 2d monitors the state of the power supply of the monitoring control device 2 and outputs a reset signal to the CPU 2a when the voltage becomes equal to or lower than the operation guarantee voltage of the CPU 2a.
Output to

The clock IC 2e outputs the present time. The initialization operation of the monitoring control device 2 configured as above will be described.

During the initial operation of the supervisory control system, an error (bug) is included in the program of the task of the supervisory controller 2, and when the CPU 2a executes the program, the CPU 2a malfunctions and hangs up. When the CPU 2a hangs up, the CPU 2a stops the pulse output to the reset IC 2c. Therefore, the reset IC 2c judges that there is no pulse input for a certain period or longer and outputs a reset signal to the CPU 2a.

Upon receiving the reset signal, the hung-up CPU 2a performs an initialization operation (reset IC 2c
The reset signal from the reset signal is called Watchdog reset), and the task program is restarted from the beginning. Therefore, due to a program error, C
Even if the PU 2a hangs up, the CPU 2a re-executes the program without being hung up forever by the initialization operation by the reset signal.

On the other hand, if the voltage drops below the operation guarantee voltage of the CPU 2a due to some inconvenience in the power source, CP
In order to guarantee the operation of U2a, the power supply monitoring reset IC2
d outputs a reset signal to the CPU 2a. CPU2a
When the reset signal is received, the initialization operation is performed at a constant time interval sufficient for the voltage to recover to the operation guarantee voltage or higher (reset by the reset signal from the power supply monitoring reset IC 2d is called power reset), and the program is reprogrammed. Start over from the beginning. Therefore, the CPU 2a does not operate in a state of the operation guarantee voltage or less.

[0017]

In the meantime, in the monitoring control system, from the viewpoint of maintenance, information related to reset such as reset cause (watchdog reset or power supply reset) and reset time when the initialization operation is performed. It is desirable that the maintenance personnel can understand later. This is because by analyzing the information related to the reset, it is possible to find and correct an error in the program that caused the reset.

However, in the supervisory control device 2 as shown in FIGS. 2 and 3, the maintenance person cannot know the information regarding the reset. Therefore, it is difficult to analyze a program error that causes a reset, and there is a problem in that maintenance work requires time and effort.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a supervisory control device which can see information related to resetting after an initialization operation and has good maintainability. To do.

[0020]

In order to solve the above problems, the present invention provides a central processing unit for processing data and a reset for the first factor. In a supervisory control device having one resetting means and a second resetting means for resetting by a second factor, reset cause information indicating which of the first resetting means and the second resetting means resets the information. It is characterized in that a reset cause information holding unit for storing is stored.

According to a second aspect of the present invention, the central processing unit has a reset cause writing section for reading the reset cause information from the reset cause information holding section and writing it in the memory during the initialization operation. To do.

According to a third aspect of the present invention, the central processing unit has a reset information writing section for reading reset information from the memory and writing the reset information in a predetermined area of the memory during an initialization operation. Is.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing an embodiment of a supervisory control device.

As shown in FIG. 1, the supervisory controller 5 includes a central processing unit (hereinafter referred to as CPU) 5a and a RAM 5b.
, Reset IC 5c, and power supply monitoring reset IC 5d
A clock IC 5e and a reset cause information holding unit 5f.

The RAM 5b stores the "task state" (stop, wait, executable, interrupted, running, runaway stop) for a plurality of tasks executed by the CPU 5a in the main storage area and the task state "wait". The “task wait cause” (waiting for time, waiting for event request, waiting for resource release), “task processing progress” indicating the progress of task processing, task work data, and task program are stored. Further, the RAM 5b has a reset information storage unit 5j and a reset cause storage unit 5k.

The reset information storage section 5j is a ring buffer in which the final address and the start address are logically connected, and stores the reset information. The reset information is the information written in the main memory area of the RAM 5b before the initialization operation, that is, "task status" and "task wait cause".
The “task processing progress”, the reset cause information (watchdog reset or power reset), and the current time (the value read from the clock IC 5e) that is the time when the reset is performed. Further, the reset information storage unit 5j can store the reset information for several times, and writes the reset information by the current reset after the area in which the reset information stored at the previous reset is written. Further, since the reset information storage unit 5j is a ring buffer, if the reset information for several times is stored and stored up to the last address of the storage area, the reset information storage unit 5j returns to the head address again and stores from the head address.

The reset cause storage unit 5k stores the "power reset count", which is the total number of power resets, and the "watch dock reset count", which is the total number of watchdog resets. The reset information storage unit 5j and the reset cause storage unit 5k are not cleared by the initialization operation.

The CPU 5a executes programs for tasks such as data collection and load device operation control as described in the prior art. The CPU 5a outputs a pulse to the reset IC 5c at a constant cycle during operation, and does not output a pulse when the CPU 5a malfunctions and hangs up. When the reset signal is input from the reset IC 5c, the initialization operation is performed, and when the reset signal is input from the power supply monitoring reset IC 5d, the initialization operation is performed after a predetermined time. Further, the CPU 5a reads the reset cause information from the reset cause information holding unit 5f at the time of the initialization operation and writes it in the reset cause storage unit 5k, and the "task state" stored in the main storage area of the RAM 5b. It has a reset information writing unit 5i which reads out the "task waiting cause" and "task processing progress" and writes it in the reset information storage unit 5j as reset information.

The CPU 5a performs the initialization operation as follows. First, when the CPU 5a receives the reset signal, the reset cause writing unit 5 immediately after the watchdog reset and after a predetermined time has elapsed after the power reset.
h reads the reset cause information (“0” or “1”) stored in the reset cause information holding unit 5f, and if “0”, the value of the “power reset count” stored in the reset cause storage unit 5k is 1 Is added, and if it is "1", 1 is added to the value of the "watchdog reset count" stored in the reset cause storage unit 5k. Next, the reset information writing unit 5i reads the "task status", "task wait cause", and "task processing progress" from the RAM 5b main storage area, and the clock IC
The current time is read from 5e, and the reset information storage unit 5
Write to j as reset information. And the CPU 5a
Erases the main memory area of the RAM 5b excluding the reset information storage unit 5j and the reset cause storage unit 5k, and restarts the execution of the task program.

The reset IC 5c has a CP within a fixed period.
If no pulse is input from U5a, the CPU 5a determines that it is hung up, outputs a reset signal to the CPU 5a, and outputs a watchdog signal to the reset cause information holding unit 5f.

The power supply monitoring and resetting IC 5d monitors the state of the power supply of the monitoring control device 5, and when the voltage becomes equal to or lower than the operation guarantee voltage of the CPU 5a, a reset signal is sent to the CPU 5a.
Output to

The clock IC 5e outputs the present time. The reset cause information holding unit 5f is a flip-flop circuit backed up by a battery or the like, and holds “1” as the reset cause information when receiving the watchdog signal from the reset IC 5c, and otherwise, as the reset cause information. Holds "0".

The input / output unit 5g is an input / output port for connecting an external maintenance device, and the maintenance device can see the stored contents of the RAM 5b via the input / output unit 5g.

The initialization operation of the supervisory control device 5 configured as above will be described. An error is included in the program of the task of the monitoring control device 5 at the time of initial operation of the monitoring control system, and when the CPU 5a executes the program, the CPU 5a malfunctions and hangs up. When the CPU 5a hangs up, the CPU 5a
Stops the pulse output to the reset IC 5c, so the reset IC 5c must input a pulse for a certain period or more,
The CPU 5a determines that the CPU 5a has hung up, outputs a reset signal to the CPU 5a, and outputs a watchdog signal to the reset cause information holding unit 5f.

The reset cause information holding section 5f receives the watchdog signal and holds the reset cause information "1".

When the CPU 5a receives the reset signal,
The reset cause writing unit 5h has the reset cause information holding unit 5f.
The reset cause information “1” stored in is read, and 1 is added to the value of the “watchdog reset count” stored in the reset cause storage unit 5k. Next, the reset information writing unit 5i reads "task state" from the main storage area of the RAM 5b.
The "task waiting cause" and "task processing progress" are read out, the current time is read out from the clock IC 5e, and the result is written in the reset information storage unit 5j as reset information. And CP
The U 5a erases the main memory area of the RAM 5b excluding the reset information storage unit 5j and the reset cause storage unit 5k, and restarts the execution of the task program from the beginning.

On the other hand, if the power supply has some trouble and the voltage drops below the operation guarantee voltage of the CPU 5a, CP
In order to guarantee the operation of U5a, the power supply monitoring reset IC5
d outputs a reset signal to the CPU 5a.

Since the reset cause information holding section 5f does not receive the watchdog signal, the reset cause information "0".
Hold.

When the CPU 5a receives the reset signal,
After a certain time interval, the reset cause writing unit 5h reads the reset cause information “0” stored in the reset cause information holding unit 5f, and sets the value of the “power reset count” stored in the reset cause storage unit 5k. Add 1 Next, the reset information writing unit 5i reads "task status", "task wait cause", and "task processing progress" from the main storage area of the RAM 5b, reads the current time from the clock IC 5e, and resets the reset information in the reset information storage unit 5j. Write as. Then, the CPU 5a erases the main storage area of the RAM 5b excluding the reset information storage unit 5j and the reset cause storage unit 5k, and restarts the execution of the task program from the beginning.

Therefore, when the reset is performed, the cause of the reset and the reset information are stored in the RAM 5b, and the maintenance person connects the maintenance device to the input / output unit 5g, and the RAM 5
By looking at the reset information in b, it is possible to analyze the cause of the reset by looking at the detailed reset information related to the reset that has occurred immediately before the reset, and the accumulated "power reset count" and "watchdog reset count". You can know the statistics of the reset cause by looking at.

In the embodiment of the present invention, the reset information is viewed by connecting the maintenance device to the input / output unit 5g. However, the present invention is not limited to this, and for example, the conventional technique has been described. Management device 3
The monitor control device 5 may send a reset information transmission request signal from the monitor control device 5 to the management device 3 so that the management device 3 can view the reset information. By doing so, the management device 3 can collectively manage the reset information of the plurality of monitoring control devices 5, so that the monitoring control system with higher maintainability can be obtained.

[0042]

Since the supervisory control device of the present invention is configured as described above, in the invention according to claim 1, the reset cause information holding section has the first reset means and the second reset means. Since the reset cause information indicating which of the two causes the reset cause is stored, it is possible to see the reset cause information after the reset, and to know whether the reset is caused by the first factor or the second factor. Therefore, it is possible to provide a monitoring control device that is easy to analyze, and that has good maintainability.

According to the second aspect of the present invention, the reset cause writing unit reads the reset cause information from the reset cause information holding unit and writes it in the memory during the initialization operation. It is possible to provide a monitoring control device that can be known and that has good maintainability.

According to the third aspect of the present invention, since the reset information writing unit reads the reset information from the memory and writes the reset information in the predetermined area of the memory during the initialization operation, the reset information is reset by looking at the predetermined area of the memory. It is possible to know the time and task status at the time of being removed, and it is possible to provide a monitoring control device with good maintainability.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a supervisory control device of the present invention.

FIG. 2 is a system configuration diagram of a conventional supervisory control system.

FIG. 3 is a block diagram of a conventional supervisory control device.

[Explanation of symbols]

 5 supervisory control device 5a central processing unit 5c first reset means 5d second reset means 5f reset cause holding unit 5h reset cause writing unit 5i reset information writing unit

Claims (3)

[Claims] 1. A central processing unit that processes data and performs an initialization operation when reset, a first reset means that resets by a first factor, and a second reset unit that resets by a second factor. In a supervisory control device having a reset means, a reset cause information holding section for storing reset cause information indicating which of the first reset means and the second reset means reset is provided. Monitoring and control equipment. 2. The supervisory control device according to claim 1, wherein the central processing unit has a reset cause writing unit that reads reset cause information from a reset cause information holding unit and writes the reset cause information in a memory during an initialization operation. . 3. The monitoring device according to claim 1, wherein the central processing unit has a reset information writing unit that reads reset information from the memory and writes the reset information in a predetermined area of the memory during an initialization operation. Control device.