JPH0964790A - Reserve line monitoring system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To unnecessitate a pilot signal generator monitoring the operation of a reserve line and to simplify a monitoring. SOLUTION: When a pilot signal is transmitted to a reserve line, the control voltage of the VCO 111 of a reserve transmission signal processing circuit 6 is defined as Vc by a switching device 1 and an oscillation frequency is fixed. A frequency divider 109 frequency-divides the oscillation clock of the VCO with a frequency division ratio fn-fm/fn. In this case, fm is the signal frequency before a multiplexing and fn is the signal frequency after the multiplexing. Next, the clock of a frequency fm is obtained in an AND output by inputting the oscillation clock of the VCO in an AND circuit 108 and inhibiting the clock output by the output of a frequency divider. By this clock, the PN pattern generator of a pilot signal generator 5 is driven.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection line monitoring system for a wireless device for switching a working line and a protection line to perform digital signal transmission, and more particularly to a simplified pilot signal timing clock generation circuit for monitoring. Protection line monitoring method.

[0002]

2. Description of the Related Art The configuration of a conventional digital radio transmission apparatus for switching lines will be described with reference to FIG. This example is 1
It has one protection line and two working lines. The line from the signal input 1 to the signal output 24 is the working 1 and the line from the signal input 2 to the signal output 25 is the working 2.

In the working 1 line, the transmission digital signal is input from the terminal 1 and is input to the transmission signal processing circuit 7 through the transmission switching device 3. Here, the frame synchronization signal is multiplexed and passed through 10 modulation circuits and transmitters to
Is output to the wireless section transmission line. 1 on the receiving side
In the reception signal processing circuit 19 through the receiver 6 and the demodulation circuit 6, the frame synchronization signal multiplexed in 7 is separated,
Outputs digital signal. Furthermore, it outputs to 24 via 21 reception switching devices.

Since the working 2 line has the same configuration as the working 1, the description thereof will be omitted.

Regarding the protection line, 6 transmission signal processing circuits, 9 modulation circuits, transmitters, 12 radio section transmission lines,
Up to 15 receivers, demodulation circuits, and 18 received signal processing circuits have the same configuration as the working line. When the working line is normal, a pilot signal is transmitted to monitor the protection line. That is, the pilot signal obtained by driving the pilot signal generator 5 at the timing of the clock oscillator 115 is input to the transmission signal processing circuit 6 through the transmission switching devices 4 and 3, and is transmitted through the protection line to 18 Output from the reception signal processing circuit of No. 2 and is input to the pilot signal detector of No. 23 via the reception switching unit Nos. 21 and 22. A PN pattern or the like is used as the pilot signal.

Next, a conventional example of the pilot signal generator 5 and the transmission signal processing circuit 6 will be described with reference to FIG.

Here, for simplification, the transmission switching device interposed between the pilot signal generator 5 and the transmission signal processing circuit 6 is omitted.

In the pilot signal generator 5, PN is generated according to the timing clock output from the clock oscillator 115.
The pattern generator 102 is driven, and the obtained signal 101
It is converted to a bipolar signal by the unipolar / bipolar converter of and is output to the transmission signal processing circuit.

In the transmission signal processing circuit 6, the input signal is converted into a unipolar signal again in 103, and the multiplexing circuit in 104 multiplexes the frame synchronization signal and outputs it. In order to generate the timing clock after multiplexing, the result of comparing the clocks before and after multiplexing with the clock phase comparator 110 is input to the VCO 111.

Regarding this prior art, for example, Japanese Unexamined Patent Publication No.
It is described in Japanese Patent Publication No. 79535.

[0011]

In the prior art, the pilot signal generator requires a clock oscillator for driving the PN pilot generator, which makes it impossible to reduce the size and cost of the device. Had.

The present invention eliminates the need for a clock oscillator conventionally required for generating a pilot signal.
The objective is to simplify the circuit configuration, improve the reliability of the device, and reduce the size and weight.

[0013]

The protection line monitoring system of the present invention does not require a dedicated clock oscillator for generating a timing clock, and divides the output clock of the VCO already provided in the transmission signal processing circuit. Generate a timing clock. That is, it is provided with a means for fixing the oscillation frequency of the VCO, a means for dividing the output clock of the VCO, and a means for prohibiting the output clock of the VCO in accordance with the division ratio to create a missing clock.

By driving the PN pattern generator with the missing clock generated by the transmission signal processing circuit, a pilot signal can be obtained without using a clock oscillator.

Further, even if the PN pattern signal is generated by the frequency-divided clock generated by the frequency divider, the PN pattern signal can be correctly transmitted by properly setting the frequency division of the frequency divider.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIGS.

FIG. 1 shows the overall configuration of a system in which the present invention is used, and FIG. 2 shows an embodiment of a concrete circuit of the present invention.

First, FIG. 1 shows the configuration of a digital radio transmission apparatus having one protection line and two working lines. In the working line 1, a transmission digital signal is input from 1 and is transmitted through 3 transmission switching devices. The frame synchronization signal is multiplexed by the transmission signal processing circuit of. Next, the signal is output to the 13 wireless section transmission line through the 10 modulation circuit and the transmitter. On the receiving side, 16 receivers and demodulation circuits pass through, and 19 receiving signal processing circuits separate the frame synchronization signals multiplexed in 7 and output digital signals. Further, it is output to 24 via 21 reception switching devices. Since the working 2 line has the same configuration as the working 1, the description thereof will be omitted.

When the working lines 1 and 2 are operating normally, a pilot signal is transmitted to the protection line for line monitoring. That is, a clock obtained by dividing the clock in the wireless section from the transmission signal processing circuit 6 is input to 5 to generate a pilot signal, and this signal is input to the transmission signal processing circuit 6 via the transmission switching devices 4 and 3. To do. After 9
The modulator circuit, transmitter, 12 wireless section transmission line, 15 receiver, demodulator circuit, and 18 received signal processing circuit are the same as the working line, and the received digital signals output from 18 are 21 and 22. It is input to 23 pilot signal detectors via the reception switcher. Here, it is confirmed that the protection channel is normal when the signals output from the pilot signal generator are collated and matched.

Next, a concrete example of the pilot signal generating circuit will be described with reference to FIG. Here, the detailed circuits of the pilot signal generator 5 and the transmission signal processing circuit 6 shown in FIG. 1 are shown. For simplicity, the transmission switch interposed between 5 and 6 is omitted.

First, in the transmission signal processing circuit 6, the bipolar signal input by the bipolar / unipolar converter 103 is converted into a unipolar signal, and the frame synchronizing signal is multiplexed by the multiplexing circuit 104. Here, the clock frequency of the bipolar signal is f _m, and the clock frequency after multiplexing is f _n . However, the f _n> f _m. In the 110 clock phase comparator, the clock of f _n is set to 11 according to f _m.
The control voltage is generated by the VCO of 1.
When transmitting a pilot signal, V is set by the switch 1.
The control voltage to the CO 111 is V _c , the oscillation frequency is fixed, and the clock of the VCO 111 is divided by the divider 109.

The frequency division ratio is (f _n -f _m ) / f _n . However, this frequency division ratio is selected as an integer. VCO frequency f
_When the clock of _n is input to the AND circuit of 108 and the clock is prohibited by the frequency divider output of 109, the obtained clock becomes [1- (f _n −f _m ) / f _n ] × f _n = f _m .
This clock drives the PN pattern generator 102 of the pilot signal generator 5, and the unipolar / bipolar converter 101 provides a bipolar pilot signal. This signal is converted into a unipolar signal by the bipolar / unipolar converter 103 and is output through the multiplexer 104.

The clock obtained at 108 has a frequency of f _n originally and is set to f _m by omitting a tooth. Therefore, although the bipolar signal output from 101 also has a missing tooth, the clock regenerated at 103 has a frequency of f _n due to the clock extraction circuit (tank circuit) of the bipolar unipolar converter. So using the AND circuit 105 to again f _m the clock frequency inputted to the multiplexing circuit. That is, the switch 2 is turned on, the clock input to 105 is prohibited, and the same missing clock as 108 is set. However, the clock output from 103 is 1
Since it is delayed from 08 to 101 and 103, a delay circuit 107 for compensating for this is inserted. Thus 10
To the multiplexing circuit of No. 4, the missing clock of frequency f _n and the PN pattern signal whose timing coincides with this are input. Since the input signal is temporarily stored in the buffer memory in the multiplexing circuit, even the missing clock and the signal can be multiplexed and output without loss of data.

The path of the signal output from the multiplexing circuit to the pilot signal detector on the receiving side is the same as described above.

[0025]

As described above, the clock oscillator, which is conventionally provided for generating the pilot signal, can be eliminated.

The reason is that the output of the clock oscillator provided in advance in the transmission signal processing circuit is divided to generate the timing clock of the pilot signal generator.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of a protection line monitoring system including a pilot signal generation circuit of the present invention.

FIG. 2 is an embodiment of a protection line monitoring system of the present invention.

FIG. 3 is a system configuration diagram including a conventional pilot signal generation circuit.

FIG. 4 is a diagram showing a conventional protection line monitoring system.

[Explanation of symbols]

 1, 2 Digital signal input terminals 3, 4 Transmission switcher 5 Pilot signal generator 6, 7, 8 Transmission signal processing circuit 9, 10, 11 Modulation circuit and transmitter 12, 13, 14 Radio signal transmission line 15, 16, 17 receiver and demodulation circuit 18,19,20 reception signal processing circuit 21,22 reception switcher 23 pilot signal detector 24,25 reception signal output terminal 101 unipolar / bipolar converter 102 PN pattern generator 103 bipolar / unipolar converter 104 Multiplexing circuit 105, 108 AND circuit 106 Switching device 2 107 Delay circuit 109 Frequency divider 110 Clock phase comparator 111 VCO (voltage controlled oscillator) 112 Switching device 1 113 Digital signal output terminal 114 Clock signal output terminal 115 Clock oscillator

Claims (6)

[Claims] 1. A protection line monitoring method using a pilot signal to monitor the protection line of a wireless transmission apparatus having a plurality of working lines and one protection line, wherein a frame synchronization signal is multiplexed with a transmission signal of the protection line. A protection line monitoring method, wherein the pilot signal is generated based on a multiplexed clock oscillation frequency of a transmission signal processing circuit that outputs the converted signal. 2. A digital radio transmission apparatus having a plurality of working lines and one protection line, wherein a pilot generator for generating a pilot signal for monitoring the protection line is provided on a transmitting side, the working line and the protection line. And a transmission signal processing circuit that switches the transmission signal to each of the working line and the protection line and outputs the multiplexed signal with a frame synchronization signal, and the modulation circuit, and the pilot signal on the receiving side. A pilot signal detector for detecting, a demodulation circuit for each of the working protection lines, and a reception signal processing circuit for separating the multiplexed transmission signals,
A reception signal switching device, and when the working line is normally transmitting signals, the output of the pilot signal generator is connected to the backup transmission signal processing circuit by the transmission signal switching device on the transmission side. In the protection line monitoring system in which the pilot signal detector is connected to the reception signal processing circuit by the reception signal switcher on the reception side to monitor the protection line, the clock oscillator output of the protection transmission signal processing circuit is divided. A standby line monitoring system characterized in that a timing clock for driving the pilot signal generator is generated using a frequency divider. 3. The preliminary transmission signal processing circuit, a bipolar / unipolar converter for converting an input bipolar digital signal into a unipolar signal, a multiplexing circuit for multiplexing a frame synchronization signal with the unipolar signal, and a pre-multiplexing circuit. A clock phase comparator for driving a VCO (voltage controlled oscillator) by comparing the clocks after the multiplexing, a switch for setting a control voltage input of the VCO to a fixed voltage, and an output clock of the VCO are divided. A divider that goes around,
3. The protection line monitoring system according to claim 1, further comprising: a first AND circuit that inhibits the VCO output clock by a frequency division output and creates a missing clock. 4. The frequency division ratio of the frequency divider is (f _n −f _m ) / f _{n, where} f _m is the clock frequency before the multiplexing and f _n is the clock frequency after the multiplexing. (However, it is an integer) 4. The protection line monitoring method according to claim 3, wherein 5. The backup line monitor according to claim 2, wherein the pilot signal generator generates a PN pattern signal which is output from the backup transmission signal processing circuit and operates with the missing clock. method. 6. The second transmission signal processing circuit inhibits the clock output of the bipolar / unipolar converter from the divided output through a delay circuit and a switch.
4. The protection line monitoring system according to claim 3, further comprising an AND circuit.