JPH0964743A - Semiconductor device, correlation arithmetic unit, a/d converter, d/a converter and signal processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale, to improve the arithmetic speed and to reduce the power consumption by separately providing a power supply means supplying power to a switch means and a power supply means supplying power to a sense amplifier. SOLUTION: Well terminals of 1st and 2nd reset switches 1, 7 and a signal transfer switch 3, well terminals and source terminals of an inverter 4 in a sense amplifier 5 are connected to a high level 1st power terminal 13 or a ground terminal 14. Furthermore, a well terminal of a 1st inverter 6 in the sense amplifier 5 connects to a 2nd power terminal 15 lower than the 1st power terminal 13. Thus, a power supply means 13 supplying power to the switch means 1, 3, 7 and a 2nd power supply means 15 supplying power to the sense amplifier 5 are provided separately. Thus, in the case of configuring the circuit and system, the circuit scale is reduced, the arithmetic speed and accuracy are improved and the power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for performing parallel operation signal processing, a correlation operation device, a D / A converter, and an A / A converter.
The present invention relates to a D converter and a signal processing system.

[0002]

2. Description of the Related Art Conventionally, with the advancement of signal processing, it has become important to realize an arithmetic unit for processing an extremely large amount of data at high speed at low cost. Among them, correlators used for motion detection of moving images, high-precision analog-digital, digital-analog converters, and other technologies such as spread spectrum (SS) communication, etc. Need.

When such a signal processing circuit is realized by a semiconductor integrated circuit, since it is operated at high speed, it is considerably large even if a plurality of semiconductor chips are used for parallel operation or the latest miniaturization rule is used. In reality, a circuit scale is required, a large-scale semiconductor device is integrated, multiple input terminals are required, and high-speed processing is possible.

Further, in a semiconductor device which performs parallel operation processing, the circuit scale increases exponentially as the number of signals to be operated in parallel increases, the manufacturing cost increases, and the yield decreases. In addition, as the circuit scale increases, the delay of wiring, etc. increases, and the number of calculations in the circuit increases, which reduces the calculation speed.
There is a problem that the power consumption increases remarkably.

For example, in the case of the solid-state image pickup device shown in FIG. 21, a high-density image pickup element 41 is arranged along the vertical and horizontal axes and a time series analog signal from a sensing section 60 as an area sensor is converted into an A / D converter 40. Convert to digital signal with
It is temporarily stored in the frame memory 39. These signals are processed by the arithmetic circuit 38 and output from the arithmetic output circuit 50. Specifically, the amount of movement of the object (ΔX, ΔY) or the like can be output by the correlation calculation between the data at different times, and the motion detection processing of the image signal can be performed.

[0006]

However, when attempting to perform real-time processing of a moving image, the number of the above-mentioned arithmetic processes is extremely large, and in order to obtain a more realistic image, the circuit scale increases exponentially. Therefore, there is a problem that the processing speed becomes slow. For example, MPEG proposed as a method of compressing / decompressing moving images.
A device that can actually process the two methods is still under development. Therefore, as a problem of the parallel arithmetic processing described above, there are problems that the arithmetic speed is reduced and the power consumption is increased with the increase of the circuit scale. Further, there are also problems that the manufacturing cost increases and the manufacturing yield decreases.

Further, regarding a majority arithmetic circuit useful for the above arithmetic processing circuit, Nikkei Electronics "Economical majority logic IC realized by CMOS" 1973.11.
5.132P to 144P. However, this is one in which a majority logic circuit is disclosed as one of digital signal processing, and it is formed by CMOS. In this case as well, the number of elements by CMOS increases and the number of stages of arithmetic processing increases, so the circuit is also In addition to the increase in scale and power consumption, there is a similar problem that the operation speed decreases.

In view of the above-mentioned conventional problems, the present invention provides a semiconductor device capable of reducing the circuit scale, improving the operation speed, and reducing the power consumption, and a semiconductor circuit using the same, a correlation operation device, A An object of the present invention is to provide a D / D converter, a D / A converter, and a signal processing system.

[0009]

In order to solve the above problems, the present invention relates to a sense amplifier in which a capacitance means is connected to multiple input terminals through a switch means, and one terminal of each capacitance means is commonly connected. In the semiconductor device to be input to, the power supply means for supplying to the switch means and the second power supply means for supplying to the sense amplifier are separately provided. With the above configuration, the effects of reducing the circuit scale, improving the operation speed, improving the operation accuracy, and reducing the power consumption can be obtained.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described in detail with reference to the drawings together with each embodiment.

[First Embodiment] FIG. 1 is a schematic explanatory view showing an embodiment according to the present invention. In the figure, 1 is the first
NMOS reset switch, 2 capacitor, 3 signal transfer switch composed of nMOS and pMOS, 5 sense amplifier, 6 first inverter in sense amplifier, 4 second inverter in sense amplifier, 7 Is the first
Second reset switch for resetting the input terminal of the inverter 6 of the second reset switch 8 and the second reset switch 8 for the second reset switch
Reset power source, 9 is a capacitor schematically showing the parasitic capacitance existing at one end of the capacitor 2 connected in common,
Reference numeral 10 is a first reset power supply, and 11 is an output terminal of the sense amplifier 5. Here, because of the structure of the integrated semiconductor,
The well terminals of the reset switches 1 and 7 and the signal transfer switch 3, and the well terminal and the source terminal of the inverter 4 are connected to the high-potential first power supply terminal 13 or the ground terminal 14. The well terminal of the first inverter 6 has a second power supply terminal 15 having a lower potential than that of the first power supply terminal 13.
And its source terminal are connected to a third power supply terminal 16 having a low potential higher than the ground potential.

FIG. 2 is an explanatory diagram of the operation timing of the circuit of this embodiment. The operation of this embodiment will be described with reference to FIG.
First, one end of the input side of the capacitor 2 is reset by the reset pulse φRES. The first reset voltage 10 is, for example, about half when the power supply voltage is a 5V system.
Use 5V. However, the reset voltage is not limited to this and may be another voltage. Also, multiple voltages may be used. At this time, almost simultaneously, the input terminal of the inverter 6 in the sense amplifier 5 is reset to the second reset voltage by making the second reset switch 7 conductive. At this time, as the second reset voltage, a value near the logic inversion voltage at which the output of the inverter 5 is inverted is selected. Next, when the reset pulse φRES is turned off, both ends of the capacitor 2 are held at the respective reset potentials.

Next, when the transfer switch 3 is turned on by the transfer pulse φT, a signal is transferred from the input terminal to one end of the capacitor 2. For example, the potential at one end of the capacitor 2 changes from a reset voltage of 2.5 V to VX. Here, as an example, when the capacitance of the capacitor 2 is C and the capacitance value of the parasitic capacitance is Co, and N capacitors 2 are connected in parallel, one commonly connected end of the capacitors 2 is capacitance-divided with respect to one input. Thus, the reset potential of the inverter 6 is changed by | (2.5-VX) * C / (N * C + Co) | (1).

When the input terminal voltage of the inverter 6 changes from near the logic inversion voltage, the output terminal voltage of the inverter 6 inverts accordingly. When a signal is input to each of the N inputs, the sum of the N capacitive division outputs is input to the input terminal of the inverter 6. After all, if the sum of these N inputs is positive, the input end of the inverter 6 shifts to a potential higher than the logic inversion voltage, and the output end 11 of the sense amplifier 5 has a high level.
However, if it is negative, it shifts to a low potential and Low Level is output. In the circuit of the present embodiment, desired weighting is applied to individual signals according to the processing desired to be performed, depending on the amplitude of the input signal and the size of the capacitor 2 to which the signal is input. It is calculated.

FIG. 3 shows the input / output static characteristics of the inverter 6. As shown in the figure, it has been found that the output voltage changes more greatly with a small change in the input voltage when the power supply voltage is lower within the range where the inverter 6 normally operates. FIG. 4 shows the dependency of the minimum detectable signal voltage on the power supply voltage of the inverter 6. By lowering the power supply voltage of the inverter 6, the input / output characteristics of the inverter 6 became steeper, and it became possible to detect even smaller signals. FIG. 5 shows the operation delay time of the inverter 6 and the power supply voltage dependency of power consumption. From the figure, it was found that even if the power supply voltage was reduced, the calculation speed did not decrease, and the power consumption decreased significantly.

From the above, it was found that the inverter 6 in the sense amplifier 5 can be operated with high accuracy and low power consumption by lowering the power supply voltage. Further, from the above formula (1), it is known that the larger the amplitude of the signal input to the capacitor 2, the larger the potential change at one end connected in common, and the higher the calculation accuracy. Therefore, the first reset switch 1 and the transfer switch 3 at the signal input end in the present invention
By supplying the high-potential first power supply voltage to the well terminal, and supplying the low-potential second and third power supply voltages to the well terminal and the source terminal of the inverter 6 and connecting them to different power supply terminals, A signal with a large amplitude can be input, and the inverter 6 can be independently set to the operating condition with the highest accuracy and low power consumption, and as a result, high-speed, high-accuracy parallel operation can be performed with low power consumption. is there. Further, as the number of inputs increases, the circuit scale increases at most in proportion to it, as shown in FIG. 1, which significantly reduces the circuit scale as compared with the conventional parallel operation circuit and also improves the manufacturing yield. Is something to be stripped. In addition, it goes without saying that the power consumption is further reduced as the circuit scale is reduced and the operation speed is improved as compared with the conventional example.

In this embodiment, the inverter 6 is adjusted in accordance with the inversion threshold voltage of the inverter 4 in the next stage of the sense amplifier 5.
Although an example in which the power supply terminals of both nMOS and pMOS are independently set so that the output of the power supply changes is shown, of course, the present invention is not limited to this, and only one power supply terminal is independently set according to the target circuit performance. You may set it. Further, in this embodiment, only the inverter 6 is provided with an independent power supply terminal, but the present invention is not limited to this, and the power supply terminal of the inverter 4 may be independently provided and optimized. Further, in the above-described embodiment, a single-sided power source that is positive with respect to the ground potential has been described.

Further, a voltage may be directly applied from the outside to the independent power supply terminal of this embodiment, or a constant voltage circuit may be built in and generated internally.

[Second Embodiment] FIG. 6 shows a second embodiment of the present invention.
It is a schematic explanatory drawing of the Example of. In the figure, 601 is a pMOS transistor, 602 is a p-type bipolar transistor, 603 is an nMOS transistor, and 604 is a p-type bipolar transistor. First in 601-604
Inverter 6 is constructed. By connecting as shown in the figure, a voltage which is lower than the voltage applied to the power supply terminal 13 by the voltage drop between the base and emitter of the n-type bipolar transistor 602 is applied to the source and well terminals of the pMOS transistor 601. It Similarly nM
The source and well terminals of the OS transistor 603 are
A voltage increased by the voltage drop between the base and emitter of the p-type bipolar transistor 604 from the voltage applied to the power supply terminal 14 at the ground level is applied. as a result,
The inverter 6 is effectively an n-type bipolar transistor 6
01 and the p-type bipolar transistor 604 operate as an inverter in which the power supply voltage is reduced by the voltage drop between the base and emitter.

By configuring as in this embodiment, unlike the case of the first embodiment, it is possible to supply the same single power source as the well region of the first reset switch, etc., and to the outside or inside. 1st without special power supply circuit
It is possible to obtain the same effect as that of the embodiment.

Further, the structure according to the present embodiment is not limited, and, for example, the power supply terminal 13 and the pMOS transistor 60.
Even if a p-type bipolar transistor is connected between 1 and n, there is n between the power supply terminal 14 and the nMOS transistor 603.
It goes without saying that the same effect can be obtained even if the bipolar transistor is connected as long as the collector and the base are short-circuited. Also, even if a plurality of n-type bipolar transistors are connected between the power supply terminal 13 and the pMOS transistor 601, or even if a plurality of p-type bipolar transistors are connected between the power supply terminal 14 and the nMOS transistor 603, As long as the base is short-circuited, it goes without saying that the same effect can be obtained in improving the characteristics of the operating region of the inverter 6.

[Third Embodiment] FIG. 7 shows a third embodiment of the present invention.
It is a schematic explanatory drawing of the Example of. In the figure, 701 is a pMOS transistor, 702 is a first diode element, 703 is an nMOS transistor, and 704 is a second diode element. The first inverter 6 is composed of 701 to 704. Not only the first inverter 6 but also the second inverter 4 and well terminals of the signal transfer switch 3 are commonly connected to the power supply terminal 13. By connecting as shown in the figure, a voltage which is lower than the voltage applied to the power supply terminal 13 by the potential drop of the first diode element 702 is applied to the source and well terminals of the pMOS transistor 702. Similarly, the source and well terminals of the nMOS transistor 703 are applied with a voltage increased by the potential drop of the second diode element 704 from the voltage applied to the power supply terminal 14 at the ground potential. As a result, the inverter 6 effectively operates as an inverter in which the power supply voltage is reduced by the potential drop of the two diode elements 702 and 704.

In this embodiment, the first and second diodes are
Although the example in which the number is set is shown, the same effect can be obtained from the operation region of the inverter 6 even when the number is plural. Further, by configuring as in this embodiment, the same effect as that of the first embodiment can be obtained without providing a special power supply circuit externally or internally.

[0024]

[Fourth Embodiment] FIG. 8 is a schematic explanatory view showing a fourth embodiment according to the present invention. In the figure, 801 is the first p
A MOS transistor, 802 is a second pMOS transistor, 803 is a first nMOS transistor, and 804 is a second nMOS transistor. The inverter 6 is composed of 801 to 804. The power supply terminal 13 is commonly connected to the first inverter 6, the second inverter 4, and the like. By connecting as shown in the figure, the second p
The source and well terminals of the MOS transistor 802 are connected to the first pMOS from the voltage applied to the power supply terminal 13.
A voltage lowered by the threshold voltage of the transistor 801 is applied. Similarly, the second nMOS transistor 80
The source and well terminals of 4 are the power supply terminal 1 of the ground potential.
From the voltage applied to the first nMOS transistor 8
A voltage increased by the threshold voltage of 03 is applied.
As a result, the inverter 6 is effectively nMOS and pMO.
It operates as an inverter in which the power supply voltage is lowered by the threshold voltage of S. The number of the nMOS transistor 803 and the pMOS transistor 801 is not limited to one, and a plurality of nMOS transistors 803 and pMOS transistors 801 can be used due to the characteristics of the inverter 6.

By configuring as in this embodiment, the same effect as in the first embodiment can be obtained without providing a special power supply circuit externally or internally. Further, since the added element is the same MOS transistor as that constituting the inverters 4 and 6 and the reset switches 1 and 7, the structure can be realized at low cost without increasing the manufacturing process.

[Fifth Embodiment] An example in which the above semiconductor device is applied to a correlation calculation circuit will be described as an eighth embodiment with reference to FIG. In FIG. 9, 221-A, 221-B, and 221-C having seven input terminals each have a multi-input terminal using the semiconductor circuit shown in the first to fourth embodiments, and the reset switch 1, This is a majority operation circuit block composed of a capacitor 2, a signal transfer switch 3, a sense amplifier 5, a first inverter 6, and the like. 1 corresponds to 221-A, FIG. 10 corresponds to 221-B, and FIG. 11 corresponds to 221-C.

In FIG. 9, 222 is an inverter and 22
Reference numeral 3 is a comparator for comparing the signal at the input terminal 232 with the correlation coefficient 233. Reference numerals 224 and 225 denote input terminal groups, to which signals similar to the seven input signals input to the majority operation circuit block 221-A are input. 226, 227, 2
28 is an input terminal for inputting the output signal from the majority arithmetic circuit block in the preceding stage, and 229, 230, 231 are input terminals 22 when the capacitance connected to the normal input terminal is C.
Capacitance value 4C corresponding to 6, 227, 228,
2C and 4C are shown.

In FIG. 9, the input signals are first input to the comparator 223 together with the respective correlation coefficients 233. The comparator 223 has a correlation coefficient 2 with each input signal.
If 33 matches, HIGH LEVEL; if they do not match, LOW LEVEL
Output VEL. The output of the comparator 223 is input to the majority operation circuit blocks 221-A to 22C. For example, when the output of the comparator 223 is input to the 7-input majority decision arithmetic circuit block 221-A, if the number of HIGH LEVEL is a majority,
In other words, if 4 or more of 7 inputs are HIGH LEVEL,
HIGH LEVEL is output from the majority calculation circuit block 221-A. This 7-input majority decision circuit block 221
If the output state of −A is shown for each number of input high levels, it becomes as shown in S3 of the chart of FIG.

Next, the polarity of the output of the 7-input majority operation circuit block 221-A is inverted by the inverter 222 and applied to the weighting input terminal of the majority operation circuit block 221-B. Specifically, in FIG. 10, reference numeral 240 is a capacitor having a capacitance value 4C which is about four times as large as that of the capacitor 2 connected to another input terminal path. Assuming that the capacitor value connected to the input terminal path is C, this circuit becomes a majority operation circuit equivalent to the one in which 11 Cs are commonly connected. The weighting input terminal 226 is added to the capacitor 4C.
To the other seven terminals and the same signal as that input to the majority decision operation circuit block 221 -A is applied to the 11-input majority decision operation circuit. For example, when 4 or more of 7 inputs are High Level, Low Level is applied to the weighting input terminal 226 as described above. Further, the input terminals 22 other than the weighting input terminal 226
Of the signals applied to 4, 6 or more of the 7 inputs are High
If it is Level, the 11-input majority calculation circuit as a whole judges that it is a majority and outputs High Level. If 4 or more and 5 or less of 7 inputs are output, Low Level is output without reaching the majority.

On the other hand, when 3 inputs or less out of 7 inputs are High Level, High Level is applied to the weighted input terminal. 4 + 2 (4 is weighted) or 4 + 3 when 2 to 3 out of 7 are High Level
(4 is a weighted portion), all inputs are 6 or more, and it is determined that the majority of the inputs, and High Level is output. Also, 1 input or less is Hi
If it is gh level, 4 + 0 or 4 + 1 is 6 or less
Low Level is output. Majority operation circuit block 22
The output value of 1-B is shown by S2 in the diagram of FIG. 12 for each input High Level.

Further, the majority operation circuit block 221-C
Also, as shown in FIG. 11, four times the capacity value 250,
It has two weighting terminals with a double capacitance value 251. The sense amplifier 5 shown in FIG.
Any of the inverters 6 described in the fourth embodiment is used. Then, as shown in FIG. 9, the 4C weighting terminal input 228 is via the inverter 222, and the 2C weighting terminal input 227 of the 2C weighting terminal is via the inverter 222. The inverted signal of the output of the block 221-B is applied, and the same signal as that input to the majority operation circuit block 221-A is applied to the other seven terminals. Thus, a total of 1
By operating as a 3 (= 7 + 2 + 4) input majority operation circuit block, an output as shown in S1 of FIG. 12 is obtained.

With this circuit configuration, as shown in FIG. 12, the number of inputs having the same correlation coefficient as the input signal among the plurality of inputs can be converted into a three-digit binary number and output. By using the circuit configuration according to the present invention, it is possible to realize a correlation calculation circuit with a smaller circuit scale, faster calculation, and lower power consumption than the conventional one.

[Sixth Embodiment] A sixth embodiment of the present invention will be described with reference to FIGS. 13 and 14. This embodiment is a 3-bit precision analog / digital converter (hereinafter referred to as an AD converter) using the present invention. FIG.
In FIG. 3, 121-A, -B, and -C are 1-input, 2-input, and 3-input arithmetic circuit blocks using the semiconductor device described in each of the above embodiments, and 122 is an inverter. Reference numerals 123, 124 and 125 denote input terminals for inputting output signals from the arithmetic circuit block at the preceding stage, 126 and 12
Reference numerals 7 and 128 denote capacitance values C / 2, C / 2, and C / 4 connected in correspondence with 123, 124, and 125, where C is a capacitance connected to a normal input terminal. 129 is an analog input terminal, 130 is a set input terminal, and
31 and 132 are capacitance values C connected correspondingly
/ 4 and C / 8 are shown. Further, S1, S2 and S3 are digital output signal terminals.

Here, the case of using a 5V power source in this embodiment will be described. In FIG. 13, first, the sense amplifier inputs in the arithmetic circuit blocks 121-A to 121-C are reset to 0V in the arithmetic circuit block 121-A and to approximately 2.5V in the arithmetic circuit blocks 121-B and C. Further, the input side of the input operation capacitor 202 of the signal input terminals 123, 124, 125 and the set input terminal 130 is reset to 5V. At this time, the analog signal input terminal 129 is at 0V. Next, the set input terminal 130
Is set to 0 V and the input voltage of the input terminal 129 is changed as an analog signal voltage that gradually rises from 0 V, in the arithmetic circuit block 121-A, when the analog input signal becomes approximately 2.5 V or more, the arithmetic circuit block The input voltage of the sense amplifier in 121-A exceeds the logic inversion voltage (assuming 2.5V here), and HIGH LEVEL is output. The result is shown in S3 of the chart of FIG.

Next, the operation of the arithmetic circuit block 121-B will be described. When the analog input signal is 2.5 V or more, the input terminal 123 changes from the reset potential of 5 V to 0 V. At this time, the potential change at the sense amplifier input terminal in the arithmetic circuit block 121-B is expressed by the following equation when the analog input signal voltage is VA. {C × VA− (C / 2) × 5− (C / 4) × 5} / (C + C / 2 + C / 4) [V] (2) From this equation, the arithmetic circuit block 121-B can output analog signals. It can be seen that HIGH LEVEL is output when the voltage VA is 3.75 V or higher, and LOW LEVEL is output when the voltage VA is 2.5 V or higher and lower than 3.75 V. The result is shown in S2 of FIG.

Similarly, the output of the arithmetic circuit block 121-C is obtained by inputting the inverted output of the arithmetic circuit block 121-A to the input terminal 128 and the inverted output of the arithmetic circuit block 121-B to the input terminal 127. The output state is shown in Figure 1.
It becomes like S1 of 4.

According to this embodiment, as shown in the chart of FIG. 14, an AD converter for converting an analog signal voltage into a 3-bit digital signal and outputting the digital signal has a very small structure.
It can be realized with high calculation speed and reduced power consumption.

In this embodiment, the 3-bit AD converter has been described, but the present invention is not limited to this, and it is possible to easily expand to more bits.

In the present embodiment, an example of a flash type AD converter using a capacitor is described, but the present invention is not limited to this method, and for example, a signal input to a resistor string and a reference signal are compared by a comparator. Needless to say, even if the present invention is applied to the encoder circuit section of the AD converter by encoding the result with an encoder, the same effect as described above can be obtained.

As described above, in the circuit block in which one terminal of the capacitance means corresponding to each of the multi-input terminals is commonly connected and input to the sense amplifier, the minimum capacitance among the capacitances connected to the multi-input terminals is obtained. When the capacity is C, the total of the capacity means is an odd multiple of C.

For example, in the case of the correlation calculation circuit, when it does not have a control input terminal, it is composed of the minimum value,
Also in the case of having a control input terminal, as described in the fourth embodiment shown in FIG. 9, for example, the capacitances connected to the control input terminal are 2C and 4C, which are even numbers, and the sum of the odd number of input signal terminals. Is almost an odd multiple of C. With such a configuration, it is possible to clearly distinguish the magnitude from the desired reference value and improve the calculation accuracy.

In the above description, the correlation operation circuit is described, but in the binary DA converter, assuming that the minimum bit LSB signal input capacity is C, the next bit is 2C, and the next bit is 4C, which is a multiple, and thus many. The total capacitance of the input terminals is almost an odd multiple of C, and highly accurate DA conversion can be realized.

As for the AD converter, as described in the fifth embodiment shown in FIG. 13, it is clearly judged whether the analog signal level exceeds 1/2 or less than 1/2 of the full range. The number of divisions to be performed is the arithmetic circuit block 121-A.
1C in 1C, 1 / in arithmetic circuit block 121-B
The number of divisions of 4 and 2/4, 3/4 becomes an odd number of 3, and the total becomes an odd multiple of 1 + 2 + 4 = 7 times with C / 4 as the minimum value, and C / 8 is set in the arithmetic circuit block 121-C. Double minimum C / 4, C / 2, C with 1 + 2 + 4 +
It is set to an odd multiple of 8 = 15.

In the above, the correlation calculator, DA converter,
Although the AD converter has been described as an example, the present invention is not limited to this, and the same effect can be obtained by applying it to various logic circuits such as a digital / analog conversion circuit, an addition circuit, and a subtraction circuit. Needless to say.

In particular, when configuring a DA converter, the LSB is
When the capacity for inputting data is C, binary digital-analog conversion can be realized by multiplying by 2C, 4C, and 8C as the next higher bit becomes. In this case, the MOS-type source follower amplifier may receive the commonly connected capacitance terminals.

[Seventh Embodiment] FIG. 15 shows a seventh embodiment of the present invention. In the seventh embodiment, the technique of the present invention described above is fused with the conventional circuit technique to realize a motion detecting chip for a moving image or the like. In FIG. 15, 161, 16
Reference numeral 2 is a memory unit that stores standard data and reference data, 163 is a correlation calculation unit, 164 is a control unit that controls the entire chip, and 165 is a correlation calculation unit 163.
, 166 is a register unit that stores the minimum value of the addition result of the addition operation unit 165, 167 is a comparison storage unit that stores the address of the comparator and the minimum value, and 168 is an output. A buffer and an output result storage unit. A standard data string is input to the input bus 169, while a reference data string to be compared with the standard data string is input to the input bus 170. The memory units 161 and 162 are, for example, SRAMs, and are composed of normal CMOS circuits.

The data sent from the reference data memory unit 162 and the standard data memory unit 161 to the correlation calculation unit 163 for correlation calculation are subjected to correlation calculation by the correlation calculation circuit according to the present invention. In addition to achieving extremely high speed, the number of elements is small, the chip size is small, and the cost is low. The correlation calculation result is subjected to a score (evaluation) of the correlation calculation in the addition calculation unit 165, and a comparison is made with the register unit 166 in which the maximum correlation result (the added value becomes the minimum value) before the correlation calculation is stored. This is performed in the storage unit 167. If the calculation result of this time is smaller than the minimum value up to the previous time, the result is newly added to the register unit 166.
If the result up to the previous time is small, the result is maintained. By performing such an operation, the maximum correlation result is always stored in the register unit 166, and after the calculation of all the data strings is completed, the result is output from the output bus 171 via the output buffer and output result storage unit 168, for example. It is output as a 16-bit signal.

The control unit 164, the addition calculation unit 165, the register unit 166, the comparison storage unit 167, and the output result storage unit 168 are composed of normal CMOS circuits this time, but the addition calculation unit 165 and the like are described above. Reset means having multiple input terminals of the present invention, a first inverter,
By using a circuit configuration including a sense amplifier and the like, parallel addition is realized at the same timing, accurate operation of the sense amplifier is realized, and high-speed processing is realized. As described above, not only high speed and low cost but also the inversion sensitivity of the input inverter of the sense amplifier is improved and the calculation is executed based on the capacitance, so that the current consumption is small and the low power can be realized. It is also suitable for portable devices such as 8 mm VTR cameras. The present embodiment is not limited to image recognition, but can be applied to automatic translation by voice recognition, speaker identification, and the like.

[Eighth Embodiment] An eighth embodiment of the present invention will be described with reference to FIG. The eighth embodiment shows a chip configuration in which the above-described technique of the present invention is fused with an optical sensor (solid-state image sensor) to perform high-speed image processing before reading image data.

FIG. 16 (a) is a block diagram showing the overall structure of the chip of the present invention, FIG. 16 (b) is a circuit diagram showing the structure of the pixel portion of the chip of the present invention, and FIG. 16 (c). [Fig. 3] is a conceptual diagram illustrating the contents of calculation of the chip of the present invention.

In the figure, 141 is a light receiving section including a photoelectric conversion element, 143, 145, 147, 149 are line memory sections, 144, 148 are correlation calculation sections, and 150 is a calculation output section. Further, 151, 152 of the light receiving unit 141 shown in FIG. 16B are optical signal output terminals 142, 146.
Coupling capacitance means for connecting to the output bus line shown in 15
3 is a bipolar transistor, 154 is capacitance means connected to the base region of the bipolar transistor 153,
55 is a switch MOS transistor. The image data incident on the image data sensing unit 160 is photoelectrically converted in the base region of the bipolar transistor 153.

The output corresponding to this photoelectrically converted photocarrier is read out to the emitter of the bipolar transistor 153, and the potential of the output bus lines 142 and 146 is converted into the input accumulated charge signal via the coupling capacitance means 151 and 152. Push up accordingly. By the above operation, the addition result of the pixels in the vertical direction is read to the line memory 147, while the addition result of the pixels in the horizontal direction is read to the line memory 143. This can be achieved by selecting a region for raising the base potential of the bipolar transistor 153 via the capacitor 154 of the pixel portion by a decoder (not shown in FIG. 13) or the like.
It is possible to output the addition result in the X and Y directions of an arbitrary area of the sensing unit 160.

For example, as shown in FIG. 16 (c), if an image as shown at 156 at time t ₁ and an image as shown at 157 at time t ₂ are input, the output results of addition in the Y direction are As indicated by 158 and 159, the image signals of the moving state of the illustrated car are obtained, and these data are stored in the line memories 147 and 149 of FIG. 16A, respectively. Also in the case of the horizontal direction, the line memory 143,
145.

Data string output 1 of image signal of FIG. 16 (c)
As can be seen from 58 and 159, both data are shifted corresponding to the movement of the image, and the correlation calculation unit 148 calculates the shift amount, and similarly the correlation calculation unit 144 calculates the horizontal data. For example, the movement of an object in a two-dimensional plane can be detected by a very simple method.

The correlation calculation circuit according to the present invention is shown in FIG.
Can be applied to the correlation calculation units 144 and 148 of FIG. Although the present configuration is based on the analog signal of the sensor, it goes without saying that the AD converter according to the present invention may be provided between the line memory section and the output bus line to support the digital correlation calculation.

Further, although the bipolar type has been described as the sensor element of the present invention, it goes without saying that the MOS type or the configuration of only the photodiode without providing the amplifying transistor is also effective.

Further, in the present embodiment, the correlation calculation between the data strings at different times is performed. However, if the X and Y projection results of a plurality of pattern data to be recognized are stored in one memory unit, the pattern recognition is performed. Can also be realized.

As described above, the following effects can be obtained by fusing the pixel input section and the correlation calculation circuit according to the present invention. (1) Rather than serially reading from a conventional sensor and performing post-processing, parallel and batch-read data are processed in parallel, so that high-speed motion detection and pattern recognition processing can be realized. (2) A one-chip semiconductor device including a sensor can be configured,
Since image processing can be realized without increasing the number of peripheral circuits, the following high-performance products can be realized at low cost. That is, (a) a control device for directing the TV screen toward the user,
(B) Control device for directing the wind direction of the air conditioner to the user, (c) Tracking control device for 8 mm VTR camera, (d)
Label recognition equipment in a factory, (e) automatic human recognition acceptance robot, (f) inter-vehicle distance control device, and the like.

The fusion with the image input unit has been described above, but it goes without saying that it is effective not only for image data but also for processing such as voice recognition.

[0060]

As described above, according to the present invention, the capacitance means is connected to the multiple input terminals through the switch means,
In a semiconductor device in which one terminal of each capacitance means is commonly connected and is input to a sense amplifier, a power supply means for supplying to the switch means and a second means for supplying to the sense amplifier
Since the power supply means is separately provided, it is possible to reduce the circuit scale, improve the operation speed, improve the operation accuracy, and reduce the power consumption when configuring the circuit and the system that perform the parallel operation processing. Is obtained.

Further, in order to make the power supply voltage of the present semiconductor device common, the configuration of the first inverter of the sense amplifier is PN.
A junction circuit is provided, and a high-sensitivity sense amplifier can be achieved by using the highest sensitivity part of the inverter as an operation range, which can contribute to improvement in calculation speed and calculation accuracy.

Further, the above semiconductor device has a correlation calculation circuit, D
By using it in an A conversion circuit, a DA conversion circuit, a signal processing system, etc., it is possible to reduce the circuit scale, improve characteristics such as calculation speed and calculation accuracy, and reduce power consumption.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a first embodiment according to the present invention.

FIG. 2 is a time chart of the first embodiment according to the present invention.

FIG. 3 is an input / output characteristic diagram of a first inverter used in each example according to the present invention.

FIG. 4 is a characteristic diagram of a minimum detectable signal amplitude with respect to a power supply voltage of a first inverter used in an embodiment according to the present invention.

FIG. 5 is a characteristic diagram of operation delay time and power consumption with respect to the power supply voltage of the first inverter used in the embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of an embodiment according to the present invention.

FIG. 7 is a circuit diagram showing a configuration of an example according to the present invention.

FIG. 8 is a circuit diagram showing a configuration of an example according to the present invention.

FIG. 9 is a circuit block diagram showing a configuration of an embodiment using a semiconductor device according to the present invention.

FIG. 10 is a circuit diagram showing a configuration of an example according to the present invention.

FIG. 11 is a circuit diagram showing a configuration of an example according to the present invention.

FIG. 12 is a chart showing the operation of the embodiment shown in FIG. 9 according to the present invention.

FIG. 13 is a circuit block diagram showing a configuration of an embodiment using a semiconductor device according to the present invention.

FIG. 14 is a chart showing the operation of the embodiment shown in FIG. 13 according to the present invention.

FIG. 15 is a circuit block diagram showing a configuration of an example using a semiconductor device according to the present invention.

FIG. 16 is a circuit block diagram showing a configuration of an example using a semiconductor device according to the present invention.

FIG. 17 is a circuit block diagram showing a configuration of an example using a conventional semiconductor device.

[Explanation of symbols]

 1 multi-input terminal reset switch 2 capacitor 3 multi-input terminal signal transfer switch 4 second inverter 5 sense amplifier 6 first inverter 7 second reset switch 8 second reset power supply 9 capacitor 10 first reset power supply 11 Output Terminal of Sense Amplifier 13 First Power Supply Terminal 14 Ground Terminal 15 Second Power Supply Terminal 16 Third Power Supply Terminal 121 Arithmetic Circuit Block 122 Inverter 141 Light Receiving Section 144, 148 Correlation Computation Section 161 Reference Data Memory 163 Correlation Computation Section 221 Majority calculation circuit 222 Inverter

Claims (12)

[Claims] 1. A semiconductor device in which a capacitance means is connected to multiple input terminals via a switch means, and one terminal of each capacitance means is commonly connected to a sense amplifier to supply power to the switch means. And a second power supply means for supplying to the sense amplifier separately. 2. A semiconductor device in which a capacitance means is connected to a multi-input terminal through a switch means, and one terminal of each capacitance means is commonly connected to a sense amplifier and the sense amplifier is composed of an inverter. A semiconductor device, wherein at least one bipolar transistor is connected in series between the inverter and a power supply means supplied to the inverter. 3. A semiconductor device in which a capacitance means is connected to multiple input terminals via a switch means, and one terminal of each capacitance means is commonly connected to a sense amplifier and the sense amplifier is composed of an inverter. A semiconductor device, wherein at least one or more diodes are connected in series between the inverter and a power supply means supplied to the inverter. 4. A semiconductor device in which a capacitance means is connected to a multi-input terminal via a switch means, and one terminal of each capacitance means is commonly connected to a sense amplifier, wherein the sense amplifier is composed of an inverter. A semiconductor device, wherein at least one or more MOS transistors are connected in series between the inverter and a power supply means supplied to the inverter. 5. A plurality of semiconductor devices according to any one of claims 1 to 4, wherein a first semiconductor device output and / or a semiconductor device output among the plurality of semiconductor devices are provided. A semiconductor device, wherein an inverted output is input to the second semiconductor device. 6. The semiconductor device according to claim 1, wherein when a minimum capacitance is C among the capacitance means corresponding to the multiple input terminals, the capacitance means commonly connected A semiconductor device, wherein a total capacitance value of the capacitances is approximately an odd multiple of the minimum capacitance C. 7. A correlation calculation apparatus, which performs a correlation calculation using the semiconductor circuit according to claim 5. 8. An A / D converter including the semiconductor device according to claim 1, wherein an analog signal is input to the semiconductor device, and a digital signal corresponding to the analog signal is output. An A / D converter characterized by: 9. A D / A converter including the semiconductor device according to claim 1, wherein a digital signal is input to the semiconductor device and an analog signal corresponding to the digital signal is output. A D / A converter characterized by: 10. The correlation calculation device according to claim 7, the A / D converter according to claim 8, or the D according to claim 9.
A signal processing system including any one or more of A / A converters. 11. The signal processing system according to claim 10, further comprising an image signal input device for inputting an image signal. 12. The signal processing system according to claim 10, further comprising a storage device that stores information.