JPH0964603A - Temperature compensation type phase delay circuit - Google Patents
Temperature compensation type phase delay circuitInfo
- Publication number
- JPH0964603A JPH0964603A JP24084295A JP24084295A JPH0964603A JP H0964603 A JPH0964603 A JP H0964603A JP 24084295 A JP24084295 A JP 24084295A JP 24084295 A JP24084295 A JP 24084295A JP H0964603 A JPH0964603 A JP H0964603A
- Authority
- JP
- Japan
- Prior art keywords
- transmission line
- phase delay
- dielectric constant
- delay circuit
- phase difference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Waveguide Switches, Polarizers, And Phase Shifters (AREA)
- Non-Reversible Transmitting Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はマイクロ波帯以上で
使用するストリップラインで形成した位相遅延回路に関
し、特に温度変化に伴う位相変化を補償する温度補償機
能を有する位相遅延回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase delay circuit formed by a strip line used in a microwave band or higher, and more particularly to a phase delay circuit having a temperature compensating function for compensating a phase change caused by a temperature change.
【０００２】[0002]
【従来の技術】従来のこの種の位相遅延回路の一例を図
５に示す。同図のように、入力端子ＩＮ１と出力端子Ｏ
ＵＴ１との間に、セラミック基板上に形成された長さＬ
のストリップラインパターンからなる伝送線路１０が接
続され、入力端子ＩＮ２と出力端子ＯＵＴ２との間に、
セラミック基板上に形成された長さＬ＋ΔＬのストリッ
プラインパターンからなる伝送線路２０が接続されてい
る。2. Description of the Related Art An example of a conventional phase delay circuit of this type is shown in FIG. As shown in the figure, the input terminal IN1 and the output terminal O
Length L formed on the ceramic substrate between UT1 and
The transmission line 10 formed of the strip line pattern is connected, and between the input terminal IN2 and the output terminal OUT2,
A transmission line 20 formed of a stripline pattern of length L + ΔL formed on a ceramic substrate is connected.
【０００３】したがって、入出力端子ＩＮ１−ＯＵＴ１
と入出力端子ＩＮ２−ＯＵＴ２との間では、伝送線路１
０，２０間にΔＬの経路差が生じているため、 Δθ＝ΔＬ／λｇ×３６０（ｄｅｇ） の位相遅延を得ることができる。なお、λｇは誘電率Ｚ
の短縮率を考慮したストリップライン上の波長である。Therefore, the input / output terminals IN1-OUT1
Between the input and output terminals IN2-OUT2 and the transmission line 1
Since a path difference of ΔL is generated between 0 and 20, a phase delay of Δθ = ΔL / λg × 360 (deg) can be obtained. Λg is the dielectric constant Z
Is the wavelength on the stripline considering the shortening rate of.
【０００４】〔発明が解決しようとする課題〕このよう
な従来の位相遅延回路では、伝送線路１０，２０はいず
れも正の温度係数の誘電率を有しているため、常温にお
いて両入出力端子間の位相差が所定のΔθであっても、
周囲温度の変動によって位相差Δθが変動してしまうと
いう問題がある。[Problems to be Solved by the Invention] In such a conventional phase delay circuit, since both transmission lines 10 and 20 have a dielectric constant having a positive temperature coefficient, both input / output terminals are kept at room temperature. Even if the phase difference between them is a predetermined Δθ,
There is a problem that the phase difference Δθ changes due to the change in ambient temperature.
【０００５】基本的に前記したセラミック基板（アルミ
ナセラミック：Ａｌ2 Ｏ3 ）の線熱膨張係数は７×１０
-6／℃程度であり、この線熱膨張係数による位相差Δθ
の温度変動は少ない。例えば、実例としては次の通りと
なる。 基板素材：アルミナセラミック基板（基板厚さ ０．６３５ｍｍ） 比誘電率：εｒ＝１０．８ ΔＬ：５０ｍｍ 解析周波数：１３．０ＧＨｚ −３０℃での位相差：１２５９．１（ｄｅｇ） ＋７０℃での位相差：１２６０．０（ｄｅｇ） したがって、−３０℃〜＋７０℃での位相差は１（ｄｅ
ｇ）以内となり、殆ど無視できる。Basically, the coefficient of linear thermal expansion of the above-mentioned ceramic substrate (alumina ceramic: Al 2 O 3 ) is 7 × 10.
-6 / ° C, and the phase difference Δθ due to this linear thermal expansion coefficient
There is little temperature fluctuation. For example, the following is a practical example. Substrate material: Alumina ceramic substrate (substrate thickness 0.635 mm) Relative permittivity: εr = 10.8 ΔL: 50 mm Analysis frequency: 13.0 GHz Phase difference at −30 ° C .: 1259.1 (deg) at + 70 ° C. Phase difference: 1260.0 (deg) Therefore, the phase difference at −30 ° C. to + 70 ° C. is 1 (deg).
It is within g) and can be almost ignored.
【０００６】しかしながら、比誘電率について考慮する
と、常温で１０．８の比誘電率をもつセラミック基板
は、温度−２０℃では１０．７程度であり、温度＋６０
℃では１０．９程度となる。したがって、前記した試料
について比誘電率による位相差の変動をみると、 すなわち、−２０℃〜＋５０℃で約位相差は９（ｄｅ
ｇ）の位相差変動となり、大きな影響が生じる。本発明
の目的は、このような温度変化に伴う位相差変動を補償
することを可能とした温度補償型位相遅延回路を提供す
ることにある。However, considering the relative permittivity, a ceramic substrate having a relative permittivity of 10.8 at room temperature is about 10.7 at a temperature of −20 ° C., and a temperature of +60.
It becomes about 10.9 at ° C. Therefore, looking at the variation of the phase difference due to the relative permittivity for the above-mentioned sample, That is, at −20 ° C. to + 50 ° C., the phase difference is about 9 (de
This results in the phase difference fluctuation of g), which has a great influence. It is an object of the present invention to provide a temperature compensation type phase delay circuit capable of compensating for the phase difference variation due to such temperature change.
【０００７】[0007]
【課題を解決するための手段】本発明の温度補償型位相
遅延回路は、セラミック基板上にそれぞれストリップラ
インパターンにより形成された一対の伝送線路を有し、
これら伝送線路間で位相遅延を生じるように構成した位
相遅延回路において、前記各伝送線路の一方にテフロン
基板上にストリップラインパターンにより形成された温
度補償伝送線路を接続したことを特徴とする。A temperature-compensated phase delay circuit of the present invention has a pair of transmission lines each formed by a stripline pattern on a ceramic substrate,
In a phase delay circuit configured to generate a phase delay between these transmission lines, a temperature compensation transmission line formed by a stripline pattern on a Teflon substrate is connected to one of the transmission lines.
【０００８】例えば、正の温度係数の誘電率を持つセラ
ミック基板上にストリップラインパターンにより形成さ
れたそれぞれの長さがＬ，Ｌ＋ΔＬの第１及び第２の伝
送線路と、正の温度係数の誘電率をもつセラミック基板
上にストリップラインパターンにより形成されて前記第
１の伝送線路に接続される第３の伝送線路と、負の温度
係数の誘電率をもつテフロン基板上にストリップライン
パターンにより形成されて前記第２の伝送線路に接続さ
れる第４の伝送線路とで構成される。For example, first and second transmission lines each having a length of L and L + ΔL formed by a strip line pattern on a ceramic substrate having a positive temperature coefficient dielectric constant, and a positive temperature coefficient dielectric. A third transmission line formed by a stripline pattern on a ceramic substrate having a dielectric constant and connected to the first transmission line; and a stripline pattern formed on a Teflon substrate having a dielectric constant with a negative temperature coefficient. And a fourth transmission line connected to the second transmission line.
【０００９】[0009]
【発明の実施の形態】次に、本発明の実施形態を図面を
参照して説明する。図１は本発明の一実施形態の平面構
成図である。入力端子ＩＮ１には、正の温度係数の誘電
率をもつセラミック基板に長さＬのストリップラインパ
ターンを形成した伝送線路（第１の伝送線路）１０を接
続する。また、入力端子ＩＮ２には、同様に正の温度係
数の誘電率をもつセラミック基板に長さＬ＋ΔＬのスト
リップラインパターンを形成した伝送線路（第２伝送線
路）２０を接続する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan configuration diagram of an embodiment of the present invention. A transmission line (first transmission line) 10 in which a stripline pattern having a length L is formed on a ceramic substrate having a positive temperature coefficient dielectric constant is connected to the input terminal IN1. Further, a transmission line (second transmission line) 20 in which a strip line pattern having a length L + ΔL is formed on a ceramic substrate similarly having a positive temperature coefficient dielectric constant is connected to the input terminal IN2.
【００１０】したがって、常温ではこれら伝送線路１
０，２０の経路差ΔＬによって、 Δθ＝ΔＬ／λｇ×３６０（ｄｅｇ） の位相遅延を得ることができることはこれまでと同じで
ある。また、温度変化に伴なう比誘電率の変化によって
位相差が変動されることも前記した通りであり、その一
例を図２に示す。Therefore, at room temperature, these transmission lines 1
It is the same as before so that a phase delay of Δθ = ΔL / λg × 360 (deg) can be obtained by the path difference ΔL of 0, 20. Further, the phase difference is changed by the change of the relative dielectric constant due to the temperature change, as described above, and an example thereof is shown in FIG.
【００１１】そして、温度補償用のストリップラインパ
ターンとして、前記伝送線路１０には、同じく正の温度
係数の誘電率をもつセラミック基板に長さＬ１で位相遅
延θ１をもつストリップラインパターンを形成した伝送
線路（第３の伝送線路）３０を接続する。一方、前記伝
送線路２０には、負の温度係数の誘電率をもつテフロン
基板に長さＬ２で位相遅延θ１を持つストリップパター
ンを形成した伝送線路（第４の伝送線路）４０を接続す
る。そして、前記伝送線路３０には出力端子ＯＵＴ１を
接続し、伝送線路４０には出力端子ＯＵＴ２を接続す
る。As a strip line pattern for temperature compensation, the transmission line 10 is formed by forming a strip line pattern having a length L1 and a phase delay θ1 on a ceramic substrate having a dielectric constant of a positive temperature coefficient. The line (third transmission line) 30 is connected. On the other hand, the transmission line 20 is connected to a transmission line (fourth transmission line) 40 in which a strip pattern having a length L2 and a phase delay θ1 is formed on a Teflon substrate having a negative temperature coefficient dielectric constant. An output terminal OUT1 is connected to the transmission line 30 and an output terminal OUT2 is connected to the transmission line 40.
【００１２】ここで、前記テフロン基板（ＡＲＬＯＮ
ＩＮＣ社製 ＤＩＣＬＡＤ５２２）の温度変化に対する
比誘電率の特性の一例を図３に示す。ここでは、常温に
てεｒ＝２．４５であるが、＋７０℃では２．４３５程
度に変化される。すなわち、０．０１４％／℃の温度変
化率を有している。Here, the Teflon substrate (ARLON)
FIG. 3 shows an example of the characteristic of the relative permittivity with respect to the temperature change of INCL DICLAD522). Here, εr = 2.45 at room temperature, but it changes to about 2.435 at + 70 ° C. That is, it has a temperature change rate of 0.014% / ° C.
【００１３】そして、このテフロン基板で構成されるス
トリップラインパターンの位相変化特性は図４に示すよ
うになる。 基板素材：テフロン基板（ＤＩＣＬＡＤ５２２） 基板厚さ ０．８ｍｍ 比誘電率：εｒ＝２．５前後 測定周波数：１３．０ＧＨｚ −２０℃での位相差：約−７（ｄｅｇ） ＋５０℃での位相差：約０（ｄｅｇ） したがって、−２０℃〜＋５０℃での位相差変動は約−
７（ｄｅｇ）となる。Then, the phase change characteristics of the strip line pattern formed of this Teflon substrate are as shown in FIG. Substrate material: Teflon substrate (DICLAD522) Substrate thickness 0.8 mm Relative permittivity: εr = 2.5 or so Measurement frequency: 13.0 GHz Phase difference at -20 ° C: Approximately -7 (deg) Phase difference at + 50 ° C : Approximately 0 (deg) Therefore, the phase difference variation from -20 ° C to + 50 ° C is approximately-.
It becomes 7 (deg).
【００１４】これにより、図１の回路では、セラミック
基板で構成した伝送線路３０と、テフロン基板で構成し
た伝送線路４０の各位相遅延はいずれも常温でθ１であ
るが、両伝送線路３０，４０間においては、伝送線路４
０には伝送線路３０に対して前記した−７（ｄｅｇ）の
位相差変動が生じることになる。この値は前記したよう
に伝送線路３０，４０の長さをそれぞれＬ１，Ｌ２とし
た場合であり、伝送線路３０，４０の長さを適宜に変化
させることで、この位相差変動の値を更に大きく、或い
は小さくすることが可能となる。As a result, in the circuit of FIG. 1, the phase delays of the transmission line 30 formed of a ceramic substrate and the transmission line 40 formed of a Teflon substrate are both θ1 at room temperature, but both transmission lines 30, 40 In between, the transmission line 4
At 0, the above-mentioned -7 (deg) phase difference variation with respect to the transmission line 30 occurs. This value is the case where the lengths of the transmission lines 30 and 40 are set to L1 and L2, respectively, as described above. By appropriately changing the lengths of the transmission lines 30 and 40, the value of this phase difference fluctuation is further increased. It is possible to make it large or small.
【００１５】したがって、図１の回路の伝送線路１０，
２０間に生じる温度変化に伴う位相差の変動を、この伝
送線路４０による位相差の変動によって抑制し、或いは
相殺して解消することができる。前記したように、伝送
線路１０，２０の間の位相差変動がΔＬ＝５０ｍｍのと
きに、−２０℃〜＋５０℃で＋９（ｄｅｇ）とすれば、
伝送線路４０によって少なくとも−２０℃〜＋５０℃で
−７（ｄｅｇ）の位相差変動を抑制することができ、位
相差の変動を温度補償することが可能となる。Therefore, the transmission line 10 of the circuit of FIG.
The fluctuation of the phase difference due to the temperature change that occurs between 20 can be suppressed or canceled by the fluctuation of the phase difference by the transmission line 40. As described above, when the phase difference variation between the transmission lines 10 and 20 is ΔL = 50 mm, if it is +9 (deg) at −20 ° C. to + 50 ° C.,
The transmission line 40 can suppress the phase difference variation of −7 (deg) at least at −20 ° C. to + 50 ° C., and the temperature difference can be compensated for.
【００１６】なお、前記実施形態は本発明の一例を示し
たものであり、必要に応じて温度補償用の伝送線路を複
数段にわたって接続し、或いは異なる長さのものを各伝
送線路に接続するように構成して、位相差変動を微細に
補償することができるように構成することも可能であ
る。The above embodiment is an example of the present invention. If necessary, temperature compensating transmission lines are connected in a plurality of stages, or those having different lengths are connected to the respective transmission lines. It is also possible to finely compensate for the phase difference variation.
【００１７】[0017]
【発明の効果】以上説明したように本発明は、正の温度
係数の誘電率をもつ基板に形成された伝送線路からなる
位相遅延回路に、負の温度係数の誘電率をもつ基板に形
成された伝送線路を接続することで、正の温度係数の誘
電率が温度変化によって変動することにより生じる位相
差変動を、負の温度係数の誘電率が温度変化によって変
動することにより生じる位相差変動によって相殺し、結
果として温度変化に伴う位相差変動を抑制ないし解消す
ることができる効果がある。As described above, according to the present invention, a phase delay circuit composed of a transmission line formed on a substrate having a positive temperature coefficient is formed on a substrate having a negative temperature coefficient. By connecting the transmission line, the phase difference fluctuation caused by the change of the permittivity of the positive temperature coefficient due to the temperature change is caused by the phase difference change caused by the change of the permittivity of the negative temperature coefficient due to the temperature change. This has the effect of canceling each other and, as a result, suppressing or eliminating fluctuations in the phase difference due to temperature changes.
【図１】本発明の一実施形態の平面図である。FIG. 1 is a plan view of an embodiment of the present invention.
【図２】セラミック基板の伝送線路における位相差変動
の特性を示す図である。FIG. 2 is a diagram showing characteristics of phase difference fluctuation in a transmission line of a ceramic substrate.
【図３】テフロン基板の伝送線路における比誘電率の温
度変化特性を示す図である。FIG. 3 is a diagram showing a temperature change characteristic of a relative permittivity in a transmission line of a Teflon substrate.
【図４】テフロン基板の伝送線路における位相差変動の
特性を示す図である。FIG. 4 is a diagram showing characteristics of phase difference fluctuation in a transmission line of a Teflon substrate.
【図５】従来の位相遅延回路の一例を示す平面図であ
る。FIG. 5 is a plan view showing an example of a conventional phase delay circuit.
１０ 伝送線路（第１の伝送線路） ２０ 伝送線路（第２の伝送線路） ３０ 伝送線路（第３の伝送線路） ４０ 伝送線路（第４の伝送線路） 10 transmission line (first transmission line) 20 transmission line (second transmission line) 30 transmission line (third transmission line) 40 transmission line (fourth transmission line)
Claims (4)
ラインパターンにより形成された一対の伝送線路を有
し、これら伝送線路間で位相遅延を生じるように構成し
た位相遅延回路において、前記各伝送線路の一方にテフ
ロン基板上にストリップラインパターンにより形成され
た温度補償伝送線路を接続したことを特徴とする温度補
償型位相遅延回路。1. A phase delay circuit having a pair of transmission lines each formed by a stripline pattern on a ceramic substrate and configured to generate a phase delay between these transmission lines, wherein one of the transmission lines is provided. A temperature-compensated phase delay circuit comprising a temperature-compensated transmission line formed by a stripline pattern on a Teflon substrate.
れぞれストリップラインパターンにより形成された一対
の伝送線路を有し、これら伝送線路間で位相遅延を生じ
るように構成した位相遅延回路において、負の温度係数
の誘電率を持つ基板上にストリップラインパターンによ
り形成された温度補償伝送線路を前記伝送線路の一方に
接続したことを特徴とする温度補償型位相遅延回路。2. A phase delay circuit having a pair of transmission lines each formed by a stripline pattern on a substrate having a positive temperature coefficient permittivity, and configured to generate a phase delay between these transmission lines. A temperature compensation type phase delay circuit characterized in that a temperature compensation transmission line formed by a stripline pattern on a substrate having a negative temperature coefficient is connected to one of the transmission lines.
基板上にストリップラインパターンにより形成されたそ
れぞれの長さがＬ，Ｌ＋ΔＬの第１及び第２の伝送線路
と、正の温度係数の誘電率をもつセラミック基板上にス
トリップラインパターンにより形成されて前記第１の伝
送線路に接続される第３の伝送線路と、負の温度係数の
誘電率をもつテフロン基板上にストリップラインパター
ンにより形成されて前記第２の伝送線路に接続される第
４の伝送線路とを備えることを特徴とする温度補償型位
相遅延回路。3. A first and second transmission lines each having a length of L, L + ΔL formed by a stripline pattern on a ceramic substrate having a positive temperature coefficient dielectric constant, and a positive temperature coefficient dielectric. A third transmission line formed by a stripline pattern on a ceramic substrate having a dielectric constant and connected to the first transmission line, and a stripline pattern formed on a Teflon substrate having a dielectric constant with a negative temperature coefficient. And a fourth transmission line connected to the second transmission line.
遅延が等しい請求項３の温度補償型位相遅延回路。4. The temperature-compensated phase delay circuit according to claim 3, wherein the third transmission line and the fourth transmission line have the same phase delay.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24084295A JPH0964603A (en) | 1995-08-26 | 1995-08-26 | Temperature compensation type phase delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24084295A JPH0964603A (en) | 1995-08-26 | 1995-08-26 | Temperature compensation type phase delay circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0964603A true JPH0964603A (en) | 1997-03-07 |
Family
ID=17065521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24084295A Pending JPH0964603A (en) | 1995-08-26 | 1995-08-26 | Temperature compensation type phase delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0964603A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20200021300A (en) * | 2018-08-20 | 2020-02-28 | 고려대학교 산학협력단 | Receiving device and operation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5593304A (en) * | 1978-12-28 | 1980-07-15 | Cselt Centro Studi Lab Telecom | Method of and device for compensating thermal phase change of transfer function of distributed parameter bidirectional device |
| JPS5710104B2 (en) * | 1972-04-17 | 1982-02-24 |
-
1995
- 1995-08-26 JP JP24084295A patent/JPH0964603A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710104B2 (en) * | 1972-04-17 | 1982-02-24 | ||
| JPS5593304A (en) * | 1978-12-28 | 1980-07-15 | Cselt Centro Studi Lab Telecom | Method of and device for compensating thermal phase change of transfer function of distributed parameter bidirectional device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20200021300A (en) * | 2018-08-20 | 2020-02-28 | 고려대학교 산학협력단 | Receiving device and operation method thereof |
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