JPH096442A - Power supply circuit - Google Patents

Power supply circuit

Info

Publication number
JPH096442A
JPH096442A JP7150090A JP15009095A JPH096442A JP H096442 A JPH096442 A JP H096442A JP 7150090 A JP7150090 A JP 7150090A JP 15009095 A JP15009095 A JP 15009095A JP H096442 A JPH096442 A JP H096442A
Authority
JP
Japan
Prior art keywords
circuit
power supply
voltage
integrated circuit
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP7150090A
Other languages
Japanese (ja)
Inventor
Takaaki Kitano
孝明 北野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba AVE Co Ltd
Original Assignee
Toshiba Corp
Toshiba AVE Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba AVE Co Ltd filed Critical Toshiba Corp
Priority to JP7150090A priority Critical patent/JPH096442A/en
Publication of JPH096442A publication Critical patent/JPH096442A/en
Withdrawn legal-status Critical Current

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  • Logic Circuits (AREA)
  • Control Of Electrical Variables (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

PURPOSE: To allow an integrated circuit to have an external power supply capable of dealing with a dual power supply or a single power supply and to reduce the power consumption in the inside of the integrated circuit to the utmost even when the single power supply is employed. CONSTITUTION: A high voltage source Vh is supplied to a high voltage power supply using circuit section 12 of an integrated circuit 11 via a high voltage application terminal 14. A proper low voltage is given to a current supply terminal 16 via a voltage drop circuit 15 from the high voltage source Vh to supply a current to an active element section 17. A stabilized reference voltage is supplied to the active element section 17 via a bias circuit 18 and a power supply with a lower voltage than the high voltage source Vh is extracted stably from the output of the active element section 17 and fed to a low voltage power supply using circuit section 13.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、高電圧及び低電圧の
電源を必要とする集積回路における電源回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit in an integrated circuit which requires high and low voltage power supplies.

【0002】[0002]

【従来の技術】近年の集積回路においては、アナログ回
路部やデジタル回路部を混在したものが多く出回ってい
る。このような集積回路では、アナログ回路部に高電圧
電源、デジタル回路部に低電圧電源が必要となる場合が
多い。
2. Description of the Related Art In recent years, many integrated circuits have a mixture of analog circuit parts and digital circuit parts. In such integrated circuits, a high voltage power source is often required for the analog circuit section and a low voltage power source is often required for the digital circuit section.

【0003】図6は、従来の高電圧及び低電圧電源の使
用回路を有する集積回路の電源回路の構成を示すもので
ある。集積回路1内に構成された2は、高電圧電源使用
回路部であり、高電圧供給端子4を介して高電圧源Vh
に接続する。また、同集積回路1内に構成された3は、
低電圧電源使用回路部であり、低電圧供給端子5を介し
て低電圧源Vlに接続する。
FIG. 6 shows a structure of a power supply circuit of an integrated circuit having circuits using conventional high voltage and low voltage power supplies. Reference numeral 2 formed in the integrated circuit 1 is a circuit portion using a high voltage power source, and a high voltage source Vh is supplied via a high voltage supply terminal 4.
Connect to. In addition, 3 formed in the integrated circuit 1 is
It is a low voltage power supply using circuit unit, and is connected to the low voltage source Vl via the low voltage supply terminal 5.

【0004】図6の構成では、高電圧及び低電圧電源V
h、Vlの使用回路を有する集積回路1の電源回路とし
ては、外部に必ず高・低の2種類の電圧源を必要とする
ため、回路設計に当たって集積回路1の外部自由度のな
いものであった。
In the configuration of FIG. 6, a high voltage and low voltage power supply V
As a power supply circuit of the integrated circuit 1 having a circuit using h and Vl, two kinds of voltage sources, high and low, are necessarily required outside, so that there is no external freedom of the integrated circuit 1 in the circuit design. It was

【0005】図7を用い、三端子レギュレータを使用し
た従来の電源回路について説明する。この構成では、高
電圧源を利用し安定度の高い低電圧源を得るものであ
る。すなわち、集積回路1は図6と同様の構成で示し、
三端子レギュレータ6の電源端子を高電圧源Vhに、出
力端子を低電圧供給端子5に、共通端子を接地点にそれ
ぞれ接続する。
A conventional power supply circuit using a three-terminal regulator will be described with reference to FIG. In this configuration, a high voltage source is used to obtain a low voltage source with high stability. That is, the integrated circuit 1 is shown in the same configuration as in FIG.
The power supply terminal of the three-terminal regulator 6 is connected to the high voltage source Vh, the output terminal is connected to the low voltage supply terminal 5, and the common terminal is connected to the ground point.

【0006】三端子レギュレータ6は、一般に安定した
電圧源を供給する素子として使用されており、図7の構
成により、安定した低電圧源を低電圧使用回路部3に供
給することができる。
The three-terminal regulator 6 is generally used as an element for supplying a stable voltage source. With the configuration of FIG. 7, a stable low voltage source can be supplied to the low voltage using circuit section 3.

【0007】しかしながら、この電源回路では、外付け
された三端子レギュレータ6が高価であるため、集積回
路11外部の負担が大きいという欠点があった。
However, this power supply circuit has a drawback in that the external three-terminal regulator 6 is expensive, so that the load on the outside of the integrated circuit 11 is large.

【0008】さらに、図8は電源回路を集積回路外部に
構成した従来例を説明するためのもので、集積回路1
は、図6、図7と同様の構成にしてある。また、集積回
路1の外にバイアス回路7及び低電圧源用のトランジス
タQ1とにより電源回路を構成し、低電圧供給端子4を
介して低電圧電源使用回路部3に安定した低電圧源を供
給する。
Further, FIG. 8 is for explaining a conventional example in which the power supply circuit is formed outside the integrated circuit.
Has the same configuration as in FIGS. 6 and 7. In addition to the integrated circuit 1, a bias circuit 7 and a transistor Q1 for a low voltage source constitute a power supply circuit, and a stable low voltage source is supplied to the low voltage power supply using circuit section 3 via the low voltage supply terminal 4. To do.

【0009】このような構成において、バイアス回路7
は安定した定電位をトランジスタQ1のベースに供給す
る。また、トランジスタQ1のコレクタを高電圧源Vh
に接続し電流供給を得ることにより、トランジスタQ1
のエミッタを出力とする安定した低電圧源を低電圧電源
使用回路部3に供給する。
In such a configuration, the bias circuit 7
Supplies a stable constant potential to the base of the transistor Q1. Further, the collector of the transistor Q1 is connected to the high voltage source Vh.
Transistor Q1
A stable low voltage source that outputs the emitter of is supplied to the low voltage power source using circuit unit 3.

【0010】この手段でも、外付けで電源回路を構成す
るため、外付け部品数が多くなり、外付けが複雑になる
ばかりではなく、高価となり、集積回路外部の負担が大
きくなるという欠点があった。
Even with this means, since the power supply circuit is constructed externally, the number of externally mounted parts becomes large, and not only the external mounting becomes complicated, but also it becomes expensive and the burden on the outside of the integrated circuit becomes large. It was

【0011】また、図9は電源回路を集積回路内部で構
成した従来の例を示すもので、集積回路1内に構成され
た2は、高電圧電源使用回路部であり、上記と同様、高
電圧供給端子4を介して高電圧源Vhに接続する。同集
積回路1内の低電圧電源使用回路部3の電圧源は、バイ
アス回路71及び集積回路1内で高電圧電源使用回路部
2にコレクタを接続した低電圧源用トランジスタQ11
で構成する電源回路により得る。
Further, FIG. 9 shows a conventional example in which a power supply circuit is constructed inside an integrated circuit. Reference numeral 2 constructed in the integrated circuit 1 is a circuit portion using a high voltage power supply, which is the same as above. It is connected to the high voltage source Vh via the voltage supply terminal 4. The voltage source of the low voltage power source using circuit section 3 in the integrated circuit 1 is a low voltage source transistor Q11 having a collector connected to the bias circuit 71 and the high voltage power source using circuit section 2 in the integrated circuit 1.
It is obtained by the power supply circuit configured in.

【0012】図9でのバイアス回路71、トランジスタ
Q11は、図8同様の動作をし、低電圧電源使用回路部
3に安定した低電圧源を供給する。この構成では、集積
回路1外部の電源は単一で良いものの、集積回路1内部
でトランジスタQ11による高電圧からの電圧降下を生
じさせているため、集積回路1内の消費電力が大きくな
り、集積回路パッケージの熱容量の点で不利であるとい
う欠点があった。
The bias circuit 71 and the transistor Q11 in FIG. 9 operate in the same manner as in FIG. 8 and supply a stable low voltage source to the low voltage power source using circuit section 3. In this configuration, although a single power source outside the integrated circuit 1 may be used, the voltage drop from the high voltage due to the transistor Q11 is generated inside the integrated circuit 1, so that the power consumption in the integrated circuit 1 increases and There is a disadvantage that it is disadvantageous in terms of heat capacity of the circuit package.

【0013】[0013]

【発明が解決しようとする課題】上記した従来の電源回
路では、二電源方式にした場合、必ず集積回路外部で二
つの電源が必要となり集積回路外部の自由度がなく、高
電圧電源を利用し集積回路外部で電源回路を構成する場
合、外付け部品が高価となり、あるいは、外付け点数が
増えるため集積回路外部の負担が大きいという欠点があ
った。集積回路内部に電源回路を構成した単電源方式で
は、低電圧源用トランジスタによる消費電力が大きいた
め、集積回路内部での消費電力が大きくなり、集積回路
パッケージの熱容量の点で不利であるという欠点があっ
た。
In the conventional power supply circuit described above, when the dual power supply system is used, two power supplies must be provided outside the integrated circuit, and there is no freedom outside the integrated circuit, and a high voltage power supply is used. When the power supply circuit is configured outside the integrated circuit, there is a drawback that the external parts are expensive or the number of external parts increases, so that the load on the outside of the integrated circuit is large. In the single power supply method in which the power supply circuit is configured inside the integrated circuit, the power consumption by the transistor for the low voltage source is large, so the power consumption inside the integrated circuit is large, which is disadvantageous in terms of the heat capacity of the integrated circuit package. was there.

【0014】この発明は、集積回路の外部電源を二電源
及び単電源のどちらにでも対応できるとともに、単電源
の場合でも集積回路内部の消費電力を抑えることのでき
る電源回路を提供する。
The present invention provides a power supply circuit capable of supporting an external power supply of an integrated circuit with either a dual power supply or a single power supply, and suppressing power consumption inside the integrated circuit even with a single power supply.

【0015】[0015]

【課題を解決するための手段】この発明は、高電圧電源
を使用する第1の回路及び低電圧電源を使用する第2の
回路を有する集積回路において、前記第1の回路へ高電
圧電源を供給する第1の外部接続端子と、バイアス回路
と、前記バイアス回路から基準電圧の供給を受けて前記
第2の回路へ前記低電圧電源を供給する能動素子と、前
記能動素子の電源側から電流供給を受ける第2の外部接
続端子とからなることを特徴とする。
SUMMARY OF THE INVENTION The present invention is an integrated circuit having a first circuit using a high voltage power supply and a second circuit using a low voltage power supply, wherein a high voltage power supply is provided to the first circuit. A first external connection terminal for supplying, a bias circuit, an active element that receives the reference voltage from the bias circuit and supplies the low-voltage power source to the second circuit, and a current from the power source side of the active element. It is characterized by comprising a second external connection terminal which receives supply.

【0016】[0016]

【作用】上記した手段により、集積回路の外部電源を二
電源及び単電源のどちらでも選択可能で、集積回路外部
の自由度が増える。単一電源で使用の場合には、従来集
積回路内の低電圧源用能動素子で消費していた電力の大
部分を集積回路外で消費させることが可能で、集積回路
内部消費電力を極力削減でき、集積回路パッケージの熱
容量の点で有利である。
By the means described above, the external power source of the integrated circuit can be selected from the dual power source and the single power source, and the degree of freedom outside the integrated circuit is increased. When used with a single power supply, most of the power consumed by the active elements for low voltage sources in the conventional integrated circuit can be consumed outside the integrated circuit, reducing the internal circuit power consumption as much as possible. This is advantageous in terms of heat capacity of the integrated circuit package.

【0017】[0017]

【実施例】以下、この発明の実施例について図面を参照
にして詳細に説明する。図1はこの発明の一実施例を説
明するための回路構成図である。図1において、11は
内部回路が異なる電圧により駆動される機能を備える集
積回路であり、高電圧電源使用回路部12と低電圧電源
使用回路部13を備える。この集積回路11の高電圧供
給端子14は高電圧電源Vhに接続し、高電圧供給端子
14は高電圧源使用回路部12に接続する。また、高電
圧電源Vhは電圧降下回路15を介して集積回路11の
電流供給端子16に接続する。電流供給端子16は、低
電圧源用の能動素子部17の電流供給端に接続する。能
動素子部17の基準電圧を受ける端子は、集積回路11
内に構成されたバイアス回路18に接続する。能動素子
部17の出力は、低電圧電源使用回路部13の低電圧電
源として接続する。
Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit configuration diagram for explaining one embodiment of the present invention. In FIG. 1, reference numeral 11 denotes an integrated circuit having a function of driving an internal circuit with different voltages, and includes a high voltage power source using circuit section 12 and a low voltage power source using circuit section 13. The high voltage supply terminal 14 of the integrated circuit 11 is connected to the high voltage power supply Vh, and the high voltage supply terminal 14 is connected to the high voltage source using circuit unit 12. Further, the high voltage power supply Vh is connected to the current supply terminal 16 of the integrated circuit 11 via the voltage drop circuit 15. The current supply terminal 16 is connected to the current supply terminal of the active element section 17 for the low voltage source. The terminal that receives the reference voltage of the active element unit 17 is the integrated circuit 11
It is connected to the bias circuit 18 configured inside. The output of the active element section 17 is connected as a low voltage power source of the low voltage power source using circuit section 13.

【0018】この構成では、バイアス回路18により安
定した基準電圧を能動素子部17に供給することによ
り、能動素子部17の低電圧電源使用回路13への電源
供給端の電位を安定にする。また、能動素子部17の電
源側から電流供給を受ける電流供給端子16に適当な低
電圧を接続し、能動素子部17に電流供給し、低電圧電
源使用回路部13に安定した低電圧源を供給する。
In this configuration, the bias circuit 18 supplies a stable reference voltage to the active element section 17, thereby stabilizing the potential of the power supply terminal of the active element section 17 to the low voltage power supply using circuit 13. Further, an appropriate low voltage is connected to the current supply terminal 16 that receives a current supply from the power source side of the active element section 17 to supply current to the active element section 17, and a stable low voltage source is supplied to the low voltage power source using circuit section 13. Supply.

【0019】この実施例による電源回路では、高電圧供
給端子14に高電圧源Vhを、能動素子部17の電源側
から電流供給を受ける電流供給端子16に、低電圧源を
接続することにより、二電源で使用できる。また、高電
圧供給端子14に高電圧源を、高電圧供給端子14と電
流供給端子16間に電圧降下回路15を接続することに
より単電源で使用でき、集積回路11の外付けされる回
路設計の自由度が増すことになる。単電源で使用した場
合には、集積回路11外部の電圧降下回路15で電力消
費するため、集積回路内の消費電力が不要に増大するこ
とはない。
In the power supply circuit according to this embodiment, the high voltage source Vh is connected to the high voltage supply terminal 14, and the low voltage source is connected to the current supply terminal 16 which receives the current from the power supply side of the active element section 17. Can be used with two power supplies. Further, by connecting a high voltage source to the high voltage supply terminal 14 and a voltage drop circuit 15 between the high voltage supply terminal 14 and the current supply terminal 16, it can be used as a single power source, and the circuit design external to the integrated circuit 11 can be used. The degree of freedom of will increase. When used with a single power supply, power is consumed by the voltage drop circuit 15 outside the integrated circuit 11, so that power consumption in the integrated circuit does not unnecessarily increase.

【0020】図2は、図1の能動素子部17をNPN型
のトランジスタで実現した場合の構成図を示すものであ
る。すなわち、能動素子部17である、NPNトランジ
スタQとし、ベースをバイアス回路18に接続してバイ
アス回路18からの基準電圧の供給を受け、エミッタを
低電圧源使用回路部13に接続して電流を供給し、コレ
クタを電流供給端子16に接続する。
FIG. 2 is a block diagram showing a case where the active element section 17 of FIG. 1 is realized by an NPN type transistor. That is, the NPN transistor Q which is the active element section 17 is used, the base is connected to the bias circuit 18, the reference voltage is supplied from the bias circuit 18, and the emitter is connected to the low voltage source using circuit section 13 to supply current. Supply and connect the collector to the current supply terminal 16.

【0021】バイアス回路18より供給される安定した
基準電圧をトランジスタQのベースに供給することで、
トランジスタQのエミッタ電位は安定し、低電圧電源使
用回路部13に安定した低電圧を供給する。また、トラ
ンジスタQのコレクタを電流供給端子16を介して適当
な低電圧に接続し、トランジスタQへの電流供給を行う
ことで、トランジスタQのエミッタから低電圧電源使用
回路部13への電流供給ができ、集積回路11内の消費
電力を不必要に増大させることなく安定した低電圧源を
得る。
By supplying the stable reference voltage supplied from the bias circuit 18 to the base of the transistor Q,
The emitter potential of the transistor Q is stable, and a stable low voltage is supplied to the low voltage power source using circuit unit 13. Further, by connecting the collector of the transistor Q to an appropriate low voltage via the current supply terminal 16 and supplying the current to the transistor Q, the current can be supplied from the emitter of the transistor Q to the low voltage power supply using circuit unit 13. Therefore, a stable low-voltage source can be obtained without unnecessarily increasing the power consumption in the integrated circuit 11.

【0022】また、トランジスタQは、pチャネル型M
OSトランジスタあるいは、nチャネル型MOSトラン
ジスタとしてもよい。
The transistor Q is a p-channel type M
It may be an OS transistor or an n-channel MOS transistor.

【0023】図3は、単電源で使用した場合の、この他
の実施例を説明するための回路構成図である。図3にお
いて図2と同一部分には同一の符号を付して説明する。
すなわち、バイアス回路18は、高電圧供給端子14と
基準電位間に抵抗R31、R32を直列接続し、抵抗R
31、R32の接続点にはコレクタを基準電位点に、エ
ミッタが抵抗R33を介して高電圧供給端子14に接続
されたトランジスタQ31のベースにそれぞれ接続して
構成する。バイアス回路18のトランジスタQ31のエ
ミッタを、トランジスタQのベースに接続する。電圧降
下回路18は、高電圧供給端子14と電流供給端子16
間に、ツェナーダイオードZ31を接続して構成する。
FIG. 3 is a circuit configuration diagram for explaining another embodiment when used with a single power source. In FIG. 3, the same parts as those in FIG.
That is, the bias circuit 18 connects the resistors R31 and R32 in series between the high voltage supply terminal 14 and the reference potential, and
The connection point of 31 and R32 has a collector connected to a reference potential point and an emitter connected to the base of a transistor Q31 connected to the high voltage supply terminal 14 via a resistor R33. The emitter of the transistor Q31 of the bias circuit 18 is connected to the base of the transistor Q. The voltage drop circuit 18 includes a high voltage supply terminal 14 and a current supply terminal 16
A Zener diode Z31 is connected between them to form a structure.

【0024】このように、バイアス回路は抵抗R31と
R32の抵抗分割比で決まる電圧からトランジスタQ3
1のVbe(ベース・エミッタ間電圧)分上がった電圧
を基準電圧として能動素子部17であるトランジスタQ
のベースに供給する。そのため、低電圧電源使用回路1
3への電源供給端であるトランジスタQのエミッタ電位
も安定する。トランジスタQは、コレクタから電流供給
を受けなければ低電圧電源使用回路部13に電源供給で
きないので、トランジスタQのコレクタを電流供給端子
16に接続しなければならない。このとき、トランジス
タQのコレクタには、電流供給端子16を介して、高電
圧源VhにツェナーダイオードZ31を接続する。ツェ
ナーダイオードZ31は電流を流すと、ある適当な電圧
降下を生じる。従って、トランジスタQに流れる電流に
よる電力消費の大部分をツェナーダイオードZ31の電
圧降下による消費電力として集積回路外部で消費させる
ことができる。
In this way, the bias circuit operates from the voltage determined by the resistance division ratio of the resistors R31 and R32 to the transistor Q3.
The transistor Q, which is the active element section 17, with the voltage raised by Vbe (base-emitter voltage) of 1 as the reference voltage.
Supply to the base. Therefore, low voltage power supply using circuit 1
The emitter potential of the transistor Q, which is the power supply terminal to 3, is also stabilized. Since the transistor Q cannot supply power to the low-voltage power supply circuit unit 13 unless it receives current supply from the collector, the collector of the transistor Q must be connected to the current supply terminal 16. At this time, the zener diode Z31 is connected to the high voltage source Vh via the current supply terminal 16 at the collector of the transistor Q. The Zener diode Z31 causes an appropriate voltage drop when a current is passed. Therefore, most of the power consumption due to the current flowing through the transistor Q can be consumed outside the integrated circuit as the power consumption due to the voltage drop of the Zener diode Z31.

【0025】この実施例では、集積回路内部での低電圧
源用トランジスタによる電力消費の大部分を、高電圧供
給端子14と電流供給端子16間の電圧降下による電力
消費として集積回路11の外部側で消費できるため、集
積回路の内部に電源回路を構成したことによる不要な集
積回路11の消費電力増大はなく、集積回路パッケージ
の熱容量の点でも有利となる。
In this embodiment, most of the power consumption by the transistors for low voltage source inside the integrated circuit is regarded as the power consumption due to the voltage drop between the high voltage supply terminal 14 and the current supply terminal 16 on the outside of the integrated circuit 11. Since the power supply circuit is configured inside the integrated circuit, unnecessary power consumption of the integrated circuit 11 does not increase, which is also advantageous in terms of heat capacity of the integrated circuit package.

【0026】なお、電圧降下回路18は、ツェナーダイ
オードに限らず、抵抗あるいは抵抗及びトランジスタで
構成するバイアス回路でもよい。
The voltage drop circuit 18 is not limited to the Zener diode, but may be a bias circuit composed of a resistor or a resistor and a transistor.

【0027】図4は、この発明の第2の他の実施例を説
明するための回路構成図であり、図1の実施例と同一の
構成部分には同一の符号を付して説明する。この実施例
は、集積回路11のジャンクション温度を検出する温度
検出回路41を集積回路11内に設け、出力値を温度検
出回路41の出力端子42を介して出力する。高電圧供
給端子14と電流供給端子16間に接続した制御型の電
圧降下回路151の降下電圧は、出力端子42の出力値
により制御したものである。
FIG. 4 is a circuit configuration diagram for explaining a second other embodiment of the present invention. The same components as those of the embodiment of FIG. 1 are designated by the same reference numerals. In this embodiment, a temperature detection circuit 41 for detecting the junction temperature of the integrated circuit 11 is provided in the integrated circuit 11, and the output value is output via the output terminal 42 of the temperature detection circuit 41. The voltage drop of the control type voltage drop circuit 151 connected between the high voltage supply terminal 14 and the current supply terminal 16 is controlled by the output value of the output terminal 42.

【0028】この構成で、温度検出回路41は、そのと
きの集積回路11のジャンクション温度に対応する検出
出力値を出力端子42に出力する。また、高電圧供給端
子14と電流供給端子16間の電圧降下回路として制御
型の電圧降下回路151を設け、その降下電圧を温度検
出回路41の検出出力値により制御する。このとき制御
型の電圧降下回路151は、集積回路11のジャンクシ
ョン温度が高いときには降下電圧を大きくし、集積回路
内での消費電力を減らし、集積回路のジャンクション温
度が低いときには、降下電圧を小さくして集積回路内で
の消費電力を大きくするように設定しておけば、集積回
路のジャンクション温度を一定に保つことができる。
With this configuration, the temperature detection circuit 41 outputs the detected output value corresponding to the junction temperature of the integrated circuit 11 at that time to the output terminal 42. Further, a control type voltage drop circuit 151 is provided as a voltage drop circuit between the high voltage supply terminal 14 and the current supply terminal 16, and the drop voltage is controlled by the detection output value of the temperature detection circuit 41. At this time, the control type voltage drop circuit 151 increases the voltage drop when the junction temperature of the integrated circuit 11 is high, reduces the power consumption in the integrated circuit, and decreases the voltage drop when the junction temperature of the integrated circuit is low. If the power consumption in the integrated circuit is set to be large, the junction temperature of the integrated circuit can be kept constant.

【0029】この実施例では、集積回路11のジャンク
ション温度の変化で電圧降下回路151の降下電圧を変
化させ、トランジスタQのコレクタ電圧を制御すること
で、そのときの温度の状態で集積回路11内の消費電力
を増減させることができ、集積回路11のジャンクショ
ン温度を一定に保つことができる。回路特性の温度変動
が大きいときに有利である。
In this embodiment, the voltage drop of the voltage drop circuit 151 is changed by the change of the junction temperature of the integrated circuit 11 to control the collector voltage of the transistor Q, so that the temperature inside the integrated circuit 11 is kept at that temperature. Power consumption can be increased or decreased, and the junction temperature of the integrated circuit 11 can be kept constant. This is advantageous when the temperature fluctuation of the circuit characteristics is large.

【0030】図5は図4の温度検出回路41及び電圧降
下回路151の具体例を説明するための回路構成図であ
る。温度検出回路41は、高電圧供給端子14と基準電
位点に抵抗R51、R52、R53を直列接続し、エミ
ッタが基準電位点に、コレクタが抵抗R51、R52の
接続点に接続されたトランジスタQ51のベースを抵抗
R52、R53の接続点に接続し、抵抗R51、R52
の接続点より出力回路A51を介して出力端子42に接
続して構成する。
FIG. 5 is a circuit configuration diagram for explaining a specific example of the temperature detection circuit 41 and the voltage drop circuit 151 of FIG. The temperature detection circuit 41 includes a high voltage supply terminal 14 and resistors R51, R52, and R53 connected in series at a reference potential point, an emitter of the transistor Q51 connected to the reference potential point, and a collector of which is connected to a connection point of the resistors R51 and R52. The base is connected to the connection point of the resistors R52 and R53, and the resistors R51 and R52 are connected.
The connection point is connected to the output terminal 42 via the output circuit A51.

【0031】また、電圧降下回路151はトランジスタ
Q52を用い、ベースを出力端子42に、エミッタを電
流供給端子16に、コレクタを高電圧供給端子14にそ
れぞれ接続して構成する。
The voltage drop circuit 151 uses a transistor Q52, and has a base connected to the output terminal 42, an emitter connected to the current supply terminal 16 and a collector connected to the high voltage supply terminal 14.

【0032】ここで、使用する温度検出回路41は、ト
ランジスタQ51のVbeの増倍回路であり、抵抗R5
2のトランジスタQ51のコレクタに接続された点の電
位Vは、 V=Vbe(1+R52/R53) となる。トランジスタQ51のVbeは、一般に−2m
V/℃程度の負の温度係数を持つことから、電位Vは−
2(1+R52/R53)mV/℃程度の温度係数をも
つ。この電位を出力回路A51により適当な値に増幅
し、出力端子42を介して出力し、温度検出回路41の
検出出力とする。この出力値を制御型の電圧降下回路1
51であるトランジスタQ52の制御電圧として使用す
る。高電圧供給端子14、電流供給端子16間の降下電
圧はトランジスタQ52のVce(コレクタ・エミッタ
間電圧)であり、出力端子42より供給される制御電圧
の温係により、集積回路ジャンクション温度が高いとき
には端子1cの電位が低くなることから、トランジスタ
Q52のVceは大きくなり、集積回路11内の消費電
力を少なくし集積回路ジャンクション温度を低くしよう
とする。集積回路のジャンクション温度が低いときには
その逆の状態となり、集積回路内の消費電力を大きくし
集積回路ジャンクション温度を高くしようとする。以上
の動作により、集積回路ジャンクション温度を一定に保
とうとする。
Here, the temperature detection circuit 41 used is a Vbe multiplication circuit of the transistor Q51, and has a resistor R5.
The potential V at the point connected to the collector of the second transistor Q51 is V = Vbe (1 + R52 / R53). Vbe of the transistor Q51 is generally -2 m.
Since it has a negative temperature coefficient of about V / ° C, the potential V is-
It has a temperature coefficient of about 2 (1 + R52 / R53) mV / ° C. This potential is amplified to an appropriate value by the output circuit A51, output through the output terminal 42, and used as the detection output of the temperature detection circuit 41. This output value is used as a control type voltage drop circuit 1
It is used as the control voltage of the transistor Q52 which is 51. The voltage drop between the high-voltage supply terminal 14 and the current supply terminal 16 is Vce (collector-emitter voltage) of the transistor Q52, and when the integrated circuit junction temperature is high, the temperature dependence of the control voltage supplied from the output terminal 42 Since the potential of the terminal 1c becomes low, Vce of the transistor Q52 becomes large, and the power consumption in the integrated circuit 11 is reduced and the integrated circuit junction temperature is lowered. When the junction temperature of the integrated circuit is low, the opposite situation occurs, and the power consumption in the integrated circuit is increased to increase the junction temperature of the integrated circuit. The above operation attempts to keep the integrated circuit junction temperature constant.

【0033】このように、集積回路11のジャンクショ
ン温度を一定に保つことができ、図4の実施例で説明し
たように、集積回路11の内部の回路特性の温度変動が
大きいときに有利である。
As described above, the junction temperature of the integrated circuit 11 can be kept constant, which is advantageous when the temperature variation of the circuit characteristics inside the integrated circuit 11 is large as described in the embodiment of FIG. .

【0034】以上説明したように、この発明の電源回路
では、高電圧源及び低電圧源が必要な集積回路におい
て、能動素子部の電流供給を受ける端子を独立に集積回
路外部に取り出すことにより、外部電源を二電源、単電
源の双方で使用可能でき、単電源で使用時には集積回路
内部の消費電力を極力削減できる。また、温度検出回路
及び制御型の電圧降下回路をさらに組み合わせることに
より集積回路のジャンクション温度を一定に保つ電源回
路を構成できる。
As described above, in the power supply circuit of the present invention, in the integrated circuit which requires the high voltage source and the low voltage source, the terminals for receiving the current supply of the active element portion are independently taken out to the outside of the integrated circuit. The external power supply can be used with both dual power supply and single power supply, and the power consumption inside the integrated circuit can be reduced as much as possible when using the single power supply. Further, a power supply circuit that keeps the junction temperature of the integrated circuit constant can be configured by further combining the temperature detection circuit and the control type voltage drop circuit.

【0035】[0035]

【発明の効果】以上説明したように、この発明の電源回
路では、能動素子部の電流供給を受ける端子を独立に集
積回路外部に取り出すことにより、外部電源を二電源、
単電源の双方で使用可能となるばかりか、単電源使用時
には集積回路内部の消費電力を極力削減できる。
As described above, in the power supply circuit of the present invention, two external power supplies are provided by independently taking out the terminals of the active element portion to which the current is supplied from the integrated circuit.
Not only can it be used with both single power supplies, but power consumption inside the integrated circuit can be reduced as much as possible when using a single power supply.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例を説明するための回路構成
図。
FIG. 1 is a circuit configuration diagram for explaining an embodiment of the present invention.

【図2】図1の実施例の能動素子部にNPNトランジス
タを用いた場合の一実施例を説明するための回路構成
図。
FIG. 2 is a circuit configuration diagram for explaining an embodiment in which an NPN transistor is used in the active element section of the embodiment of FIG.

【図3】図2を単電源で使用した場合の一実施例を説明
するための回路構成図。
FIG. 3 is a circuit configuration diagram for explaining an embodiment when FIG. 2 is used with a single power source.

【図4】他の実施例を説明するための回路構成図。FIG. 4 is a circuit configuration diagram for explaining another embodiment.

【図5】図4の一具体例を説明するための回路構成図。5 is a circuit configuration diagram for explaining one specific example of FIG. 4;

【図6】従来の高電圧電源使用回路及び低電圧電源使用
回路を有する集積回路の電源回路の構成図。
FIG. 6 is a configuration diagram of a power supply circuit of an integrated circuit having a conventional high voltage power supply using circuit and a low voltage power supply using circuit.

【図7】三端子レギュレータを使用し電源回路を構成し
た一従来例を説明するための回路構成図。
FIG. 7 is a circuit configuration diagram for explaining a conventional example in which a power supply circuit is configured using a three-terminal regulator.

【図8】電源回路を集積回路外部で構成した一従来例を
説明するための回路構成図。
FIG. 8 is a circuit configuration diagram for explaining a conventional example in which a power supply circuit is configured outside the integrated circuit.

【図9】電源回路を集積回路内部で構成した一従来例を
説明するための回路構成図。
FIG. 9 is a circuit configuration diagram for explaining a conventional example in which a power supply circuit is configured inside an integrated circuit.

【符号の説明】[Explanation of symbols]

11…集積回路、12…高電圧電源使用回路部、13…
低電圧電源使用回路部、14…高電圧供給端子、15、
151…電圧降下回路、16…電流供給端子、17…能
動素子部、18…バイアス回路、41…温度検出回路、
42…出力端子、Vh…高電圧源、Vl…低電圧源。
11 ... Integrated circuit, 12 ... Circuit part using high voltage power supply, 13 ...
Low voltage power supply circuit section, 14 ... High voltage supply terminal, 15,
151 ... Voltage drop circuit, 16 ... Current supply terminal, 17 ... Active element section, 18 ... Bias circuit, 41 ... Temperature detection circuit,
42 ... Output terminal, Vh ... High voltage source, Vl ... Low voltage source.

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 高電圧電源を使用する第1の回路及び低
電圧電源を使用する第2の回路を有する集積回路におい
て、 前記第1の回路へ高電圧電源を供給する第1の外部接続
端子と、 バイアス回路と、 前記バイアス回路から基準電圧の供給を受けて前記第2
の回路へ前記低電圧電源を供給する能動素子と、 前記能動素子の電源側から電流供給を受ける第2の外部
接続端子とからなることを特徴とする電源回路。
1. An integrated circuit having a first circuit using a high voltage power supply and a second circuit using a low voltage power supply, wherein a first external connection terminal for supplying a high voltage power supply to the first circuit. A bias circuit; and a second bias circuit that receives a reference voltage from the bias circuit.
2. A power supply circuit comprising: an active element that supplies the low-voltage power supply to the circuit of 1); and a second external connection terminal that receives a current supply from the power supply side of the active element.
【請求項2】 前記電源用能動素子をNPNトランジス
タとし、そのベースを前記バイアス回路に接続し、その
エミッタを前記低電圧電源を使用する回路に接続し、そ
のコレクタを独立に外部接続端子に接続してなることを
特徴とする請求項1記載の電源回路。
2. An active element for power supply is an NPN transistor, its base is connected to the bias circuit, its emitter is connected to a circuit using the low voltage power supply, and its collector is independently connected to an external connection terminal. The power supply circuit according to claim 1, wherein:
【請求項3】 前記電源用能動素子は、pチャネル型M
OSトランジスタとし、そのゲートを前記バイアス回路
に接続し、そのドレインを前記低電圧電源を使用する回
路に接続し、そのソースを独立に外部接続端子に接続し
てなることを特徴とする請求項1記載の電源回路。
3. The active element for power supply is a p-channel type M
An OS transistor, the gate of which is connected to the bias circuit, the drain of which is connected to a circuit that uses the low-voltage power supply, and the source of which is independently connected to an external connection terminal. The power supply circuit described.
【請求項4】 前記電源用能動素子は、nチャネル型M
OSトランジスタとし、そのゲートを前記バイアス回路
に接続し、そのソースを前記低電圧電源を使用する回路
に接続し、そのドレインを独立に外部接続端子に接続し
てなることを特徴とする請求項1記載の電源回路。
4. The active element for power supply is an n-channel type M
2. An OS transistor, the gate of which is connected to the bias circuit, the source of which is connected to a circuit that uses the low-voltage power supply, and the drain of which is independently connected to an external connection terminal. The power supply circuit described.
【請求項5】 集積回路電源端子と前記電源用能動素子
の電源側から電流供給を受ける端子間に集積回路外部に
設けた電圧降下回路を備えることを特徴とする請求項1
記載の電源回路。
5. A voltage drop circuit provided outside the integrated circuit between an integrated circuit power supply terminal and a terminal that receives a current supply from the power supply side of the power supply active element.
The power supply circuit described.
【請求項6】 集積回路内部にあり、その出力が外部接
続端子に導出される温度検出回路と、集積回路外部の、
集積回路電源端子と前記電源用能動素子の電源側から電
流供給を受ける端子間に電圧制御型の電圧降下回路を備
え、前記温度検出回路の出力値により、前記電圧降下回
路の出力電圧値を制御することを特徴とする請求項1記
載の電源回路。
6. A temperature detection circuit, which is inside the integrated circuit and whose output is led to an external connection terminal, and outside the integrated circuit,
A voltage control type voltage drop circuit is provided between an integrated circuit power supply terminal and a terminal that receives current supply from the power supply side of the power supply active element, and the output voltage value of the voltage drop circuit is controlled by the output value of the temperature detection circuit. The power supply circuit according to claim 1, wherein:
【請求項7】 前記電圧制御型の電圧降下回路としてト
ランジスタを用い、そのベースを温度検出回路出力端子
に、そのコレクタを前記集積回路電源端子に、そのエミ
ッタを前記電源用能動素子の電源側から電流供給を受け
る端子に接続し、温度検出回路の出力値により前記電源
用能動素子の電源側から電流供給を受ける端子の電圧を
制御することを特徴とする請求項6記載の電源回路。
7. A transistor is used as the voltage control type voltage drop circuit, the base of which is used as a temperature detection circuit output terminal, the collector of which is used as the integrated circuit power supply terminal and the emitter of which is used as a power supply side of the power supply active element. 7. The power supply circuit according to claim 6, wherein the power supply circuit is connected to a terminal supplied with a current, and the voltage of the terminal supplied with the current from the power supply side of the active element for power supply is controlled by the output value of the temperature detection circuit.
JP7150090A 1995-06-16 1995-06-16 Power supply circuit Withdrawn JPH096442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7150090A JPH096442A (en) 1995-06-16 1995-06-16 Power supply circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7150090A JPH096442A (en) 1995-06-16 1995-06-16 Power supply circuit

Publications (1)

Publication Number Publication Date
JPH096442A true JPH096442A (en) 1997-01-10

Family

ID=15489299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7150090A Withdrawn JPH096442A (en) 1995-06-16 1995-06-16 Power supply circuit

Country Status (1)

Country Link
JP (1) JPH096442A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6798709B2 (en) 2002-04-25 2004-09-28 Samsung Electronics Co., Ltd. Memory device having dual power ports and memory system including the same
JP2006332850A (en) * 2005-05-24 2006-12-07 Toshiba Corp Semiconductor device and system
JP2008009625A (en) * 2006-06-28 2008-01-17 Sanyo Electric Co Ltd Integrated circuit for electric power source
CN105549671A (en) * 2014-10-24 2016-05-04 硅实验室公司 System and Apparatus for Improving the Utility of Regulators and Associated Methods

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6798709B2 (en) 2002-04-25 2004-09-28 Samsung Electronics Co., Ltd. Memory device having dual power ports and memory system including the same
KR100456595B1 (en) * 2002-04-25 2004-11-09 삼성전자주식회사 Memory device having dual power port and memory system including thereof
JP2006332850A (en) * 2005-05-24 2006-12-07 Toshiba Corp Semiconductor device and system
JP4761833B2 (en) * 2005-05-24 2011-08-31 株式会社東芝 Semiconductor device and system
JP2008009625A (en) * 2006-06-28 2008-01-17 Sanyo Electric Co Ltd Integrated circuit for electric power source
CN105549671A (en) * 2014-10-24 2016-05-04 硅实验室公司 System and Apparatus for Improving the Utility of Regulators and Associated Methods

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