JPH0964353A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve breakdown strength by forming a semiconductor device with a high-concentration impurity implantation region formed adjacent to the impurity implantation region with an intermediate concentration and achieving a gentle inclination in the concentration profile of a transistor. SOLUTION: A semiconductor device consists of a gate electrode 5B formed on a semiconductor substrate via a gate oxide film 4, a low-concentration impurity implantation region I formed adjacent to both edges of the gate electrode, an intermediate concentration impurity implantation region II formed adjacent to a low-concentration impurity implantation region, and a high-concentration impurity implantation region III formed adjacent to a middle-concentration impurity implantation region and the concentration profile of a transistor is gently inclined by the implantation regions.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an LDD (Light).
The present invention relates to a manufacturing method technique capable of improving the withstand voltage of a semiconductor device having a tly doped drain structure and reducing the number of manufacturing steps.

[0002]

2. Description of the Related Art A semiconductor device having such an LDD structure is
Since the strong electrolysis in the channel region can be relaxed, various problems in the short channel can be solved. Such an LDD structure semiconductor device is shown in FIGS.
It was formed by the manufacturing method shown in FIG.

First, as shown in FIG. 8, a field oxide film 22 is formed on the surface of a semiconductor substrate of one conductivity type, for example, a P-type semiconductor substrate 21 according to a selective oxidation method, and a device region 23 is covered with a gate oxide film 24. After forming the gate electrode 25 made of polysilicon, N-type impurities are ion-implanted at a low concentration using the gate electrode 25 as a mask. Next, as shown in FIG. 9, a CVD oxide film 26 is deposited on the substrate.

Subsequently, as shown in FIG. 10, the CVD oxide film 26 is etched by anisotropic etching to form a sidewall spacer 27 made of the CVD oxide film remaining on the side surface of the gate electrode 25, and then the gate is formed. Electrode 2
N-type impurities are ion-implanted at a high concentration by using 5 and the sidewall spacer 27 as a mask. Then, as shown in FIG. 11, heat treatment is performed to activate each of the impurity ion-implanted layers to form a source / drain consisting of an N- type diffusion layer 28 near the channel region and an N + type diffusion layer 29 adjacent to this layer. Had formed layers.

However, in this method, in order to form the LDD structure, the CVD oxide film 26 is deposited and the sidewall spacers 27 are formed by anisotropic etching. Therefore, two steps are required to form the sidewall spacers 27. That is, the manufacturing process was complicated. In addition, in the above-described low-concentration and high-concentration impurity ion implantation, a technique of implanting with a certain tilt angle for preventing channeling, for example, a state in which an angle of 7 degrees from the vertical direction is provided, has also been used.

However, this method has an asymmetrical transistor structure depending on the direction of the transistor, that is, the positions of the source / drain diffusion layers formed on the left and right of the gate electrode are different, and the characteristics are different depending on the transistor. Therefore, in order to prevent this, the injection is performed again from the direction opposite to the injection direction so that the injection is made symmetrical. However, in the case where there are mixed transistors whose transistor orientations differ by 90 degrees, for example,
After all, there was a drawback that there were things with different characteristics.

Further, in the semiconductor device formed by such a method, the slope is steep as shown by the dotted line in the drawing of the concentration profile of FIG. 7, so that the pressure resistance is poor.

[0008]

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a method of manufacturing a semiconductor device, which can improve the characteristics such as withstand voltage of the semiconductor device and reduce the number of manufacturing steps.

[0009]

Therefore, according to the semiconductor device of the present invention, a gate electrode formed on a semiconductor substrate via a gate insulating film and a low concentration impurity formed adjacent to both ends of the gate electrode. An implantation region, a medium-concentration impurity implantation region formed adjacent to the low-concentration impurity implantation region, and a high-concentration impurity implantation region formed adjacent to the medium-concentration impurity implantation region, These injection regions give the concentration profile of the transistor a gentle slope.

The semiconductor device manufacturing method of the present invention is
Forming a gate electrode on a semiconductor substrate via a gate insulating film, and masking the resist film after covering one formation region of the source / drain diffusion layers formed at both ends of the gate electrode with the resist film A step of injecting a low-concentration impurity at a certain inclination angle from two directions intersecting at a predetermined angle, a step of injecting a high-concentration impurity at a certain inclination angle from two directions facing each of the injection directions, and the resist A step of removing the film, covering the other source / drain diffusion layer forming region with a resist film, and then implanting a low concentration impurity at a certain inclination angle from two directions intersecting at a predetermined angle using the resist film as a mask; And a step of injecting a high-concentration impurity at a certain inclination angle from two directions opposite to each of the injection directions.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device of the present invention effective for forming a transistor structure in which a source / drain diffusion layer is bilaterally symmetric and a method for manufacturing the same will be described with reference to FIGS.
This will be described with reference to the drawings. In this embodiment, a P-type semiconductor substrate is used as the one conductivity type semiconductor substrate, but the present invention is also applicable to an N-type semiconductor substrate.

FIG. 1 is a schematic view showing an arrangement of two transistors TR1 and TR2 formed on a semiconductor substrate and having different arrangement directions. FIG. 2, FIG. 3, FIG. 5 and FIG.
FIG. 2 is a diagram showing an X-X cross section of one transistor TR2 shown in FIG. From now on, based on these figures, the transistor T
The manufacturing process of R2 will be described, but naturally the transistor TR1 is also formed at the same time.

In FIG. 2, for example, a P-type semiconductor substrate 1
The field oxide film 2 is formed on the surface according to the selective oxidation method,
After the gate electrode 5B made of polysilicon is formed in the element region 3 with the gate oxide film 4 interposed therebetween, a source electrode formed at both ends of the gate electrode 5B in a post process as shown in FIG.
N- and N + diffusion layers 8 which will be described later as drain diffusion layers
A resist film 6B is formed so as to cover one of the formation regions of B and 9B, and a low concentration N-type impurity is used as a mask with the gate electrode 5B and the resist film 6B as a mask, for example, an inclination angle (from an arrow direction shown in FIG. For example, ion implantation is performed obliquely above the substrate at about 7 degrees from the vertical direction. still,
When phosphorus (31 P +) ions are used as the N-type impurity, the implantation conditions are an accelerating voltage of 30 to 60 KeV and an implantation amount of 10 13th order. At this time, as shown in FIG. 2, the impurity ions implanted from the direction of the arrow are implanted into the transistor TR2 on the right side shown in FIG.
A predetermined amount is overlapped below B.
The inclination angle is set so that the overlap formed between the gate electrode 5B and the ion-implanted layer of the low concentration N-type impurity is desired. In addition, the resist film 6
Impurity ions are implanted into the transistor TR1 on the left side, which is covered with one of the source / drain diffusion layers formed in the later step by A, in a direction parallel to the gate length of the gate electrode 5A. Impurity ions do not enter.

Subsequently, a low-concentration impurity is implanted under the same conditions from the direction of the arrow shown in FIG. 1 (for example, the direction of 90 degrees with respect to the implantation direction). At this time, the impurity ions to be implanted into the transistor TR1 on the left side shown in FIG. 1 are implanted in the direction perpendicular to the gate length as described above, so that they are overlapped below the gate electrode 5A. become. In this case as well, the inclination angle is set so that the overlap formed between the gate electrode 5A and the ion-implanted layer of the low concentration N-type impurity is desired. Further, since the transistor TR2 on the right side is implanted in the direction parallel to the gate length, impurity ions do not enter below the gate electrode 5B.

Next, a high-concentration N-type impurity is injected from the direction of the arrow shown in FIG. 1 (the direction opposite to the direction of the arrow), so that the transistor TR2 on the right side of FIG.
As shown in FIG. 3, part of the impurities to be implanted is shielded by the gate electrode 5B, and high-concentration N-type impurities are deeply ion-implanted from a position away from the end of the gate electrode 5B by a predetermined distance (offset length). . The implantation conditions when arsenic (75 As @ +) ions are used as N-type impurities are an acceleration voltage of 30 to 60 KeV and an implantation amount of 10 @ 15. At this time, the inclination angle is set so that a desired offset length can be obtained between the gate electrode 5B and the ion-implanted layer of the high concentration N-type impurity. Further, impurity ions are implanted into the transistor TR1 on the left side only in a portion which is not masked by the gate electrode 5A and the resist film 6A.

Next, from the direction of the arrow shown in FIG. 1 (the direction opposite to the direction of the arrow), the high concentration of N
By implanting the type impurity, the transistor TR1 on the left side of FIG. 1 has part of the impurity implanted by the gate electrode 5A shielded as described above, and has a predetermined distance (offset length) from the end of the gate electrode 5A. High-concentration N-type impurities are deeply ion-implanted from a distant position. Also at this time, the inclination angle is set so that a desired interval (offset length) can be obtained between the gate electrode 5A and the ion-implanted layer of the high concentration N-type impurity. Further, impurity ions are implanted into the transistor TR2 on the right side only in a portion which is not masked by the gate electrode 5B and the resist film 6B.

Next, in FIG. 4, the resist films 6A and 6B are removed, and the other source / drain diffusion layer forming regions of the transistors TR1 and TR2 are covered with the resist films 7A and 7B, and then the substrate 1 is coated with 180 °. In a diagram showing a state of being rotated by a degree, in the same manner as described above, first, low-concentration N-type impurities are implanted at a desired inclination angle from the arrow direction, and then the same low-concentration is implanted from the arrow direction orthogonal to the implantation direction. N-type impurities are implanted at a desired inclination angle. Then, a high-concentration N-type impurity is implanted in the direction of the arrow, and a high-concentration N-type impurity is similarly implanted in the direction of the arrow to complete the implantation of the other impurity ion for forming the diffusion layer.

FIG. 5 shows a semiconductor device in which impurity ions are implanted as described above. For example, a region (I) overlapping below the gate electrode 5B is a low concentration N-type impurity implanted in the direction of the arrow. Formed by ions,
A region (II) adjacent to the region (I) is formed by low-concentration N-type impurity ions implanted in the direction indicated by the arrow and high-concentration N-type impurity ions implanted in the direction indicated by the arrow. The region (III) adjacent to () is formed by low-concentration N-type impurity ions implanted from the arrow and direction and high-concentration N-type impurity ions implanted from the arrow and direction. Of course, the transistor T
R1 has a similar structure, and the source / drain diffusion layers of the transistors TR1 and TR2 are formed symmetrically regardless of the orientation of the transistors.

Then, heat treatment is performed as shown in FIG.
The impurity ion-implanted layers of the transistors TR1 and TR2 are activated to activate the N-type diffusion layer 8B near the channel region.
(Transistor TR1 side not shown) and N + type diffusion layer 9B adjacent to this layer (Transistor TR1 side not shown)
A source / drain layer is formed. In the semiconductor device thus formed, the concentration gradient becomes gentle through each region (I, II, III) as shown in the concentration profile of FIG. It can be improved.

Further, according to the manufacturing method of the present invention, the LD can be formed without forming the sidewall spacer as in the conventional case.
It can be a D structure. Further, even when transistors having different arrangement directions are mixed, the transistor structure can be symmetrical. In this embodiment, the impurity ions are implanted under the same conditions from two intersecting directions. For example, the substrate mounting table is rotated by 90 degrees so that the implantation region of the transistor is aligned with the impurity ion source side. The ion source side may be moved.

[0021]

As described above, in the semiconductor device having the LDD structure of the present invention, the region where the low concentration impurity ions are implanted once and overlapped below the gate electrode, and the low concentration impurity ions adjacent to the region are 2 1 time and high concentration of impurity ions
Since there is a region that has been twice implanted and a region that is adjacent to the region that has been twice implanted with low-concentration impurity ions and twice implanted with high-concentration impurity ions, the concentration gradient becomes gentle and the withstand voltage is improved. And other characteristics can be improved.

Further, in the manufacturing method of the present invention, the LD can be formed without forming the side wall spacer as in the conventional case.
The D structure can be used, and the number of manufacturing steps can be reduced.
Further, even when transistors having different orientations are formed on one circuit board, the transistor structure can be bilaterally symmetric, and transistors having the same characteristics can be formed.

[Brief description of drawings]

FIG. 1 is a plan view showing a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 4 is a plan view showing a method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 6 is a cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 7 is a diagram showing a concentration profile of the semiconductor device of the present invention.

FIG. 8 is a first sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 9 is a second cross-sectional view illustrating the conventional method for manufacturing a semiconductor device.

FIG. 10 is a third cross-sectional view showing the method of manufacturing the conventional semiconductor device.

FIG. 11 is a fourth sectional view showing the conventional method for manufacturing a semiconductor device.

Claims (3)

[Claims] 1. A gate electrode formed on a semiconductor substrate with a gate insulating film interposed therebetween, a low-concentration impurity implantation region formed adjacent to both ends of the gate electrode, and a low-concentration impurity implantation region. The transistor has a medium-concentration impurity-implanted region formed adjacently and a high-concentration impurity-implanted region formed adjacent to the medium-concentration impurity-implanted region, and has a gentle slope in the concentration profile of the transistor. A semiconductor device characterized by the above. 2. A step of forming a gate electrode on a semiconductor substrate via a gate insulating film, a step of forming low concentration impurity implantation regions adjacent to both ends of the gate electrode, and the low concentration impurity implantation region. And a step of forming a high concentration impurity implantation region adjacent to the medium concentration impurity implantation region, and a step of forming a high concentration impurity implantation region adjacent to the medium concentration impurity implantation region. 3. A step of forming a gate electrode on a semiconductor substrate via a gate insulating film, and a resist film on one area of a source / drain diffusion layer forming area formed at both ends of the gate electrode in a later step. After the coating, a step of implanting a low concentration impurity at a certain inclination angle from two directions intersecting at a predetermined angle using the resist film as a mask, and a high concentration impurity at a certain inclination angle from two directions respectively facing the implantation directions. And removing the resist film, covering the other source / drain diffusion layer forming region with the resist film, and then using the resist film as a mask to reduce the concentration at a certain inclination angle from two directions intersecting at a predetermined angle. And a step of injecting a high-concentration impurity at a certain inclination angle from two directions opposite to the respective injection directions. Method of manufacturing a body apparatus.