JPH096321A - Computer system - Google Patents

Abstract

PURPOSE: To transfer image data to an image memory at a high speed. CONSTITUTION: After generating the starting address of one scanning line to output it onto the address/data bus of a high-speed bus 208, a dynamic image transfer controller 210 consecutively outputs the image data of each pixel on that scanning line. A video controller 212 generates the pixel address of each pixel on that scanning line from the starting address of the scanning line and writes the image data of each pixel to a VRAM 222 in accordance with this pixel address. The dynamic image transfer controller 210 has additional functions of magnifying and reducing dynamic images with an arbitrary scale factor in the vertical and horizontal directions when transferring the images.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system for transferring a video signal of a moving picture to a video memory and displaying the moving picture.

[0002]

2. Description of the Related Art Conventionally, so-called DMA (Direct Memory Access) transfer has been used as a method for transferring externally supplied video data to a video memory of a personal computer.

FIG. 19 is a block diagram showing a conventional computer system having a DMA controller for transferring video data to a video RAM. The three video memories 51R, 51G and 51B have color data Dr and D which are color-separated into red (R), green (G) and blue (B).
g and Db are stored respectively. These color data Dr, Dg, Db are binarized in advance by, for example, the dither method. The DMA controller 55 uses the address bus 53
The right to use the data bus 52 and the control bus 54 to the CPU
59 video, three video memories 51R, 51G, 5
Video RAM 56R, 56G, 56 for displaying binary color data Dr, Dg, Db stored in 1B in real time
Transfer to B respectively. The transferred binary color data Dr,
Dg and Db are sent to the monitor control unit 57 through the VRAMs 56R, 56G and 56B to display the image on the monitor 58.

In the DMA transfer, first, the CPU 59
Sends the display start address in the VRAM 56R for the R component to the DMA controller 55 to activate the DMA controller 55. The DMA controller 55 acquires the right to use the bus from the CPU 59, transfers the binary color data Dr of the R component of the first line to the VRAM 56R for the R component, and then returns the right to use the bus to the CPU 59. next,
When the CPU 59 sends the display start address of the VRAM 56G for the G component to the DMA controller 55 and activates the DMA controller 55, the binary color data D is generated in the same manner as the R component.
Transfer of g is performed. Further, the B component is transferred in the same manner. When transferring the video data of the second line, use CP
U59 is 2 for each of VRAM 56R, 56G, 56B
The display start address of the line is calculated and sent to the DMA controller 55, and the binary color data Dr of each color of RGB is drawn.
, Dg, Db are sequentially transferred.

As described above, the CPU 59 controls the V for each line.
The display start address of the RAM 56R, 56G, 56B is calculated and taught to the DMA controller 55, and the DMA controller 55 responds to this by the color data Dr, D of each line.
By sequentially DMA-transferring g and Db, color data for one field is transferred to the VRAM 56. The "1 field" refers to an image covered by one scan from the upper left corner to the lower right corner of the screen. In many cases, 2: 1 interlace (interlaced scanning) is performed, and one field (one screen) image is composed of two fields. In this way, a moving image is displayed on the monitor 58 by sequentially DMA-transferring about 60 fields of binary color data per second.

[0006]

[Problems to be Solved by the Invention] NTSC (National T
When a video signal based on the Elevation System Commuttee method is used, the scanning period for one horizontal line is 63 μs. On the other hand, in the system of FIG. 19, the time when the CPU 59 calculates the display start address and transfers it to the DMA controller 55, the time when the DMA controller 55 acquires the right to use each bus from the CPU 59, and each binary color data D
When the time for DMA transfer of one line of r, Dg, and Db is summed up, only a few fields worth of data can be transferred per second. This is considered to be because it takes more time than necessary for the CPU 59 to calculate the display start address and to set the display start address in the DMA controller 55. As described above, in the conventional device, it is impossible to display a smooth moving image because only a few fields of data can be transferred per second.

The present invention has been made to solve the above problems in the prior art, and an object thereof is to transfer a video signal representing a moving image to a video memory at high speed.

[0008]

According to a first aspect of the present invention, there is provided a computer system including: a microprocessor for executing various calculations and controls according to a software program; and a first microprocessor connected to the microprocessor. A bus, a second bus in which addresses and data are transferred in a time division manner by a common signal line, a bridge connecting the first and second buses, a display device for displaying a video, and the display device. A video memory that stores a video signal of a video to be displayed, a video controller that is connected to the second bus and controls writing and reading of a video signal to and from the video memory, and a composite video of a moving image given from the outside. A video decoder for decoding a signal to generate a component video signal and a sync signal; For each scan line of the image represented by the image signal, the second to generate a start address of each scan line
And a video transfer means for continuously outputting the component video signal of each pixel on the scanning line after the head address to the second bus after the start address. An address generation unit that generates a pixel address for each pixel on each scanning line from the head address and a writing unit that writes the component image signal of each pixel of each scanning line in the video memory according to the pixel address are provided.

When the video transfer means outputs the start address to the second bus, the address generation means of the video controller generates the pixel address of each pixel from the start address, so that the video transfer means uses the start address of each scanning line. Only output it. The video transfer means only needs to output the head address and the video signal for each scanning line, so that the video signal can be transferred at high speed.

[0010]

【Example】

A. System Configuration: FIG. 1 is a block diagram showing the configuration of a computer system as a first embodiment of the present invention. In this computer system, a CPU 200 and a main memory 202 are connected to a host bus 204. The host bus 204 is connected to the high speed bus 208 via the bridge 206. This express bus 208
It is a bus in which addresses and data are transferred in a time division manner by a common signal line. The high-speed bus 208 is a synchronous bus that operates in synchronization with a clock signal, but the frequency of the clock signal may be 33 MHz or less, and the clock frequency can be changed during the operation.

A moving image transfer controller 210, a video controller 212 and an expansion bus bridge 214 are connected to the high speed bus 208. The moving image transfer controller 210 includes an AD converter 218 and a video decoder 2.
20 are connected in series. Video decoder 220
Decodes the composite video signal VS given from the outside to generate a component video signal (YUV signal or RGB signal), synchronization signals VSYNC and HSYNC, and a field instruction signal FIS. The field instruction signal FIS is a signal that indicates an odd field or an even field in the case of interlaced scanning. In the video decoder 220, a color signal conversion circuit that converts a YUV signal into an RGB signal is provided. A-D converter 21
Reference numeral 8 converts the analog component video signal into a digital component video signal DS.

A video RAM (VRAM) 222 as a frame memory and a color CRT 224 or a color liquid crystal display (LCD) 226 as a display device are connected to the video controller 212.
The video controller 212 uses a VRAM for the digital video signal (video data) provided via the high-speed bus 208.
It has a writing function of writing to the 222 and a display function of displaying an image by reading the image signal from the VRAM 222 and giving it to the color CRT 224 or the liquid crystal display 226.

The expansion bus bridge 214 is used for the high speed bus 20.
8 is a bridge for connecting the low speed bus 230.
Various I / O controllers 232, connectors (not shown), etc. are connected to the low-speed bus 230. Low-speed bus 23
0 has a lower data transfer rate than the high speed bus 208,
A relatively low speed input / output device such as a floppy disk device or a keyboard is connected.

FIG. 2 is a block diagram showing the internal structure of the moving image transfer controller 210. The video transfer controller 210 has an interface 300 with the high-speed bus 208.
A bus control signal generation unit 302 for generating a control signal for the high speed bus 208; a switching circuit 304 for switching an address and data to output on the address / data bus ADB in the high speed bus 208; and a bus control signal generation A switching control unit 306 that controls the operations of the unit 302 and the switching circuit 304, an address calculation unit 312 that calculates an address, a data output unit 314, a FIFO memory unit 318, and a color adjustment unit 320 are provided.

The digital video signal DS supplied to the color adjusting section 320 is 24-bit (8 bits for each RGB) full-color video data. The color adjusting unit 320 can reproduce the 24-bit digital video signal DS by 16 bits (R: G: B = 5: 6: 5 bits can reproduce 60,000 colors) and 8 bits (R: G). : B = 3: 3: 25 with 25 bits
6 colors can be reproduced) 4 bits (1 by color palette)
6 colors can be reproduced) 3 bits (8 by color palette)
It is a circuit that converts video data that can reproduce colors. 8
When converting to 4-bit, 3-bit, or 3-bit video data, binarization by the dither method is executed. The type of video data to be converted is set by the CPU 200 according to the operator's designation. However, a case will be described below where the color adjusting unit 320 outputs 24-bit full-color video data (referred to as “component video data”) as they are.

The component video data VD output from the color adjusting section 320 is stored in the FIFO memory unit 318.
Are sequentially stored. FIG. 3 shows a FIFO memory unit 3
It is a block diagram which shows the internal structure of 18. As shown in FIG. 3A, the FIFO memory unit 318 is
O control unit 321 and two FIFO memories 322, 32
It is equipped with 4. In addition, as shown in FIG.
The FO control unit 321 has five PLL circuits 325 to 328,
It has a 510 and a waveform shaping section 511. The first to third PLL circuits 325 to 327 are used for the horizontal synchronization signal HS.
The frequency of YNC is NH0 times, (NH0 * HX) times, and
The signals CLKI, CLKO and DCLK multiplied by NH are generated respectively. Further, the fourth PLL circuit 328 generates a signal HINC that is the frequency of the vertical synchronizing signal VSYNC multiplied by NV. As shown in FIG. 3C, the fifth PLL circuit 510 generates a signal HSYNC * HX which is the frequency of the horizontal synchronizing signal HSYNC multiplied by HX, and the waveform shaping section 511 detects the rising edge thereof to generate the second edge. Horizontal sync signal X
Generate HSYNC. This second horizontal synchronizing signal XHS
YNC is a sync signal having a frequency that is HX times the frequency of the first horizontal sync signal HSYNC. The set values NH0, (NH0 * HX), NH, NV and HX in each PLL circuit are C
It is set by the PU 200. These PLL circuits 3
Reference numerals 25 to 328 are circuits for enlarging / reducing an image, the function of which will be described later.

Two FIFO memories 322 and 32 are provided.
Reference numeral 4 has a function as a video data buffer for temporarily storing a predetermined amount of video data, and the FIFO control unit 321 has a function as a video data buffer control unit. Further, the first PLL circuit 325 serves as an input clock generation means, the second PLL circuit 326 serves as an output clock generation means, the third PLL circuit 327 serves as a dot clock generation means, and the fourth PLL circuit 328 serves as a line increment. Each has a function as a signal generation means. The second and fourth PLL circuits 326, 3
28 and the FIFO memory unit 318 work together,
It exerts a function as a scaling unit that can scale an image vertically. In addition, the second and third PLL circuits 326 and 327
Cooperate with each other to exert a function as a scaling means capable of scaling a video represented by video data in the horizontal direction.

As shown in FIG. 2, the video data output from the FIFO memory unit 318 is stored in the data output unit 3.
It is output onto the address / data bus ADB via 14 and the switching circuit 304. The switching circuit 304 switches between the video data MDATA output from the data output unit 314 and the address MADD output from the address calculation unit 312 in accordance with the switching signal SW given from the switching control unit 306, and the address MADD and the data MDATA are switched. Is output in time division. Further, the 3-state buffer 305 in the switching circuit 304 is switched between an output state and a high impedance state according to the first output control signal C1 given from the switching control unit 306. The bus control signal generation unit 302 for various control signals (C / BE, FRAME #, etc.) for the high-speed bus 208 also has a 3-state buffer 303 at its output unit. The 3-state buffer 303 is switched between an output state and a high impedance state according to the second output control signal C2 provided from the switching control unit 306.

FIG. 4 is a block diagram showing the internal structure of the address calculation unit 312 in the moving image transfer controller 210. The address calculation unit 312 includes an offset address storage unit 330, an addition address value storage unit 332, a vertical counter unit 334, and an adder 340. The multiplier 338 multiplies the added address value ADAD stored in the added address value storage unit 332 by the vertical count value VCNT output from the vertical counter unit 334.
The adder 340 includes the offset address OFAD stored in advance in the offset address storage unit 330 and the multiplier 33.
By adding the multiplication result of 8 and MUL, the address MADD of the video data is generated. As described below,
This address MADD is the start address of each scanning line.

FIG. 5 is a block diagram showing the internal structure of the video controller 212. Video controller 21
2 is a decoder 350, an address counter 352,
Address latch 354, data conversion circuit 356, V
And a GA controller 358. Decoder 35
0, address counter 352, and address latch 354
From the start address MADD of each scanning line given via the address / data bus ADB of the high speed bus 208,
Address (pixel address) PAD of each pixel on each scanning line
It has a function as an address generating means for generating D.
In addition, the VGA controller 358 controls the pixel address PA
Video data PDATA of each pixel of each scanning line according to DD
To the VRAM 222.

The decoder 350 generates signals for controlling the address counter 352, the address latch 354 and the data conversion circuit 356 from various control signals of the high speed bus 208. The data conversion circuit 356 is the high-speed bus 2.
When a YUV signal is given via 08, it is RG
It is a circuit for converting into a B signal. When the RGB signal is supplied, the RGB signal passes through the data conversion circuit 356 as it is. Whether or not data conversion circuit 356 performs data conversion is determined according to the mode signal provided from decoder 350.

B. Transferring video data to VRAM:
FIG. 6 is a memory map of the VRAM 222. This V
One word of the RAM 222 is 24 bits, and one word contains the R component, G component and B component of the video data. Further, one pixel (dot) on the screen corresponds to one word.

FIG. 7 is an explanatory diagram showing the correspondence between the memory space of the VRAM 222 and the screen. In this figure, VR
The number of pixels of the horizontal range 80 of AM222 is 640 (50h
The number of scanning lines in the vertical range 81 is 480. In the example of FIG. 7, for simplicity, the moving image area MPA in which the moving image data is written has a width of 8 pixels in the horizontal direction starting from the start position of the second pixel in the second line in the vertical direction in the horizontal direction. It is assumed that there is a total area of 16 pixels having a width of 2 lines in the vertical direction. In addition,
The position and size of the moving image area MPA are designated by the operator on the screen of the color CRT 224 or the color liquid crystal display 226.

FIG. 8 is a plan view showing a moving image area MPA designated on the screen of the color CRT 224. The memory space shown in FIG. 6 is a color CRT 224 shown in FIG.
It corresponds to the display screen of 1: 1. In the following, the data transfer without interlaced scanning will be described first, and the data transfer with interlaced scanning will be described later.

Offset address storage unit 33 shown in FIG.
The offset address OFAD stored in 0 corresponds to the write start position address (0051) of the moving image area MPA from the start address 0000h of the VRAM 222 in FIG.
It is the offset value (51h) up to h).

The start address (= 0051h) of the first scanning line of the moving picture area MPA is determined according to the position of the upper left point P1 of the moving picture area MPA designated by the operator on the screen. That is, when the operator specifies the moving image area MPA, the CPU 200 calculates an address (= 0051h) corresponding to the upper left point P1, and this address (= 005
1h) is set in the offset address storage unit 330 as the offset address OFAD. The operator can set the moving image area MPA of any size at any position on the screen of the color CRT 224 or the color liquid crystal display 226, and the offset address O can be set accordingly.
FAD is set.

When interlaced scanning is not performed,
The addition address ADAD stored in the addition address value storage unit 332 is equal to the number of pixels of one scanning line in the memory space of the VRAM 222, and is set to 50h in this embodiment.

The output MUL of the multiplier 338 and the adder 34
The output MADD of 0 is given by the following arithmetic expressions, respectively. MUL = ADAD × VCNT (1) MADD = OFAD + MUL (2)

Summarizing the above equations (1) and (2), the output MADD of the adder 340 for each scanning line is given by the following arithmetic equation. MADD = (ADAD × VCNT) + OFAD (3)

The vertical count VCNT indicates the scanning line number in the moving image area MPA. The output MUL of the multiplier 338 indicates the difference (offset) in address from the write start position P1 of the moving image area MPA to the leading pixel of each scanning line. Therefore, the output MADD of the adder 340 is the address of the leading pixel of each scanning line (the leading address of each scanning line).

FIG. 9 is a timing chart showing the operation of data transfer from the moving image transfer controller 210 to the video controller 212. 9A to 9G.
The two controllers 21 via the high speed bus 208.
This is a signal exchanged between 0 and 212, and is shown in FIG.
(J) is from the video controller 212 to the VRAM 222
Is a signal to. The transfer of the video data is executed in synchronization with the dot clock signal DCLK (FIG. 9A) generated by the FIFO memory unit 318 (FIG. 3).

The moving image transfer controller 210 generates the start address MADD (FIG. 9B) of each scanning line in the address calculation unit 312 (FIGS. 2 and 4) and outputs it on the address / data bus ADB of the high speed bus 208. Output to. Then, the switch (multiplexer) in the switching circuit 304 is switched to the data output unit 314 side by the switching signal SW given from the switching control unit 306. As a result, eight pixels on the scanning line of the head address MADD (0051 in FIG. 7)
image data D1 to D8 regarding pixels h to 0058h)
Are continuously output on the address / data bus ADB in synchronization with the dot clock signal DCLK.

9C to 9G show control signals when a PCI (Peripheral Component Interconnect) bus is used as the high speed bus 208. FIG. 9 (c)
Signal C / BE of the address / data bus ADB (see FIG. 9).
While the address MADD is output in (b)), a bus command designating the type of bus cycle of the high-speed bus 208 (memory access, I / O access, etc.) is transmitted, and the address / data bus ADB is also transmitted. Data D on top
While 1 to D8 are being output, the byte enable signal of the address / data bus ADB is transmitted. The address / data bus ADB has a bus width of 32 bits (4 bytes), and a 4-bit byte enable signal C /
Each bit of BE indicates which byte lane of 4 bytes is valid. For example, when transferring 24-bit video data in the lower 3 bytes, the value of the signal C / BE is 1000h. The byte enable has a negative logic. The signal C / BE is output by the moving image transfer controller 210 that is the transfer source.

The signal IRDY # in FIG. 9E is a moving image transfer controller 2 which is a transfer source (initiator device).
10 is a signal indicating that data transfer is possible, and is output by the moving image transfer controller 210. In addition,
In this specification, a signal having "#" after the signal name is a signal of negative logic. Signal TR of FIG. 9 (f)
DY # is a signal indicating that the video controller 212 that is the transfer destination (target device) can transfer data, and is output by the video controller 212. Further, the signal FRAME # in FIG. 9C is a signal output by the moving image transfer controller 210 that is the initiator, and when the signal FRAME # is asserted (when it becomes L level), a bus cycle is started. When the signal FRAME # is deasserted (at H level), the bus cycle ends at the next clock. The signal DEVSEL # in FIG. 9G is a signal indicating that the target video controller 212 accepts data transfer, and is output by the video controller 212. Although there are other control signals for the high-speed bus 208, they are omitted for convenience of illustration.

In the example of FIG. 9, the signal FRAME # (FIG. 9
When (d)) is asserted to start the bus cycle, the head address MADD of each scan line is output to the address / data bus ADB, and then 8 on one scan line is output.
The video signals D1 to D8 of one pixel are continuously output.
At this time, the signal FRAME # is deasserted when the video data D7 for the seventh pixel is transferred, and the video data D8 for the next eighth pixel becomes the final transfer data, and the bus cycle ends. By repeating such data transfer for one scanning line a plurality of times, the video data for one field is transferred from the moving image transfer controller 210 to the video controller 212.

The decoder 350 shown in FIG. 5 checks the address output from the moving picture transfer controller 210, which is the initiator, to determine whether the video controller 212 is the target device. If the video controller 212 is the target device, the decoder 350 controls the control signal TRDY # (see FIG. 9).
(F)), DEVSEL # (FIG. 9 (g)) to high-speed bus 2
08, and supplies a control signal to the address counter 352, the address latch 354, and the data conversion circuit 356 to control their operations. That is, when the address MADD is output on the address / data bus ADB, the load terminal of the address counter 352 is activated to change the address MAD.
D is set as the initial value of the address counter 352.
The pixel write signal PWR # is input from the decoder 350 to the clock terminal of the address counter 352. The pixel write signal PWR # is a signal that is synchronized with the clock signal DCLK of the high-speed bus 208 at the same frequency and indicates the timing at which the VGA controller 358 writes the video data of each pixel in the VRAM 222. Therefore, the address counter 352 has the clock signal DCLK (see FIG. 9).
The address is incremented by 1 for each pulse in (a)), and the pixel address PADD for each pixel is output. The address latch 354 has an address counter 352.
Latch the pixel address PADD output from
It is output to the A controller 358.

The VGA controller 358 controls the pixel write signal PWR #, the pixel address PADD, and the video data PDA.
TA and receive the pixel write signal EP in the VRAM 222.
WR #, pixel address EPADD, video data EPDA
And TA to supply video data EPDATA to VRAM
Write to 222. That is, as shown in FIGS. 9H to 9J, the video data D1 to D8 for eight pixels on one scanning line are VR in synchronization with the pixel write signal EPWR #.
Written in AM 222. Since the pixel address EPADD given from the VGA controller 358 to the VRAM 222 is defined in the local address space of the VGA controller 358, the high speed bus 20
Although it is different from the value of the pixel address PADD in 8, the meaning is the same. That is, the pixel address EPAD
The value of D is a value that is incremented by 1 every one clock from the start address SP of each scanning line.

In the example of FIG. 9, after the moving image transfer controller 210 outputs the head address MADD of each scanning line, the video data for all the pixels on the scanning line is continuously transferred. However, it is not always necessary to continuously transfer the video data for all the pixels on each scanning line. That is, the video transfer controller 210
Video data having a desired number of pixels can be continuously transferred following one address. It is also possible to alternately output the address and data of each pixel. However,
As shown in FIG. 9, if the video data for all the pixels on the scanning line is continuously transferred after the head address MADD of each scanning line is output, the data transfer can be performed at a higher speed. There is an advantage that smooth video display can be performed.

C. Address calculation when interlaced scanning is performed: FIG. 10 is an explanatory diagram showing a memory space of an odd line field and an even line field when interlaced scanning is performed, and is a diagram corresponding to FIG. 7. The odd line field is 16 in the moving image area MPA.
The pixel address includes eight pixel addresses 00A1h to 00A8h for one scanning line, and the even line field includes the other eight pixel addresses 0051h to 00A.
58h is included.

When interlacing is performed, an offset address OFAD1 = A1h for odd line fields and an offset address OFAD2 = for even line fields are stored in the offset address storage unit 330 (FIG. 4).
51h and are registered. Offset address storage unit 330
Are those two offset addresses OFAD1, O
One of FAD2 is selectively output according to the field instruction signal FIS. In the case of 2: 1 interlace, the addition address ADAD is twice (= A0h) the value (= 50h) when there is no interlace. Thus, in the case of interlaced scanning, by adjusting the offset address OFAD and the addition address ADAD, the start address MADD of the video data of each scanning line is calculated according to the above equation (3), as in the case without interlacing. Can be calculated.

Even when video data for interlacing is transferred, it is possible to write video data of odd line fields and even line fields at the same address without intentionally performing interlacing. In this case, the offset address OFAD and the addition address ADAD when there is no interlace may be commonly used for both fields.

D. Image enlargement / reduction processing: The moving image transfer controller 210 has a function of performing image enlargement / reduction. The image enlargement / reduction processing is mainly performed by the address calculation unit 312 and the FIFO memory unit 318 shown in FIG.
Executed by and. FIG. 11 shows the address calculation unit 31.
2 is a block diagram showing an internal configuration of a vertical counter unit 334 in FIG. 2 and related parts in a FIFO control unit 321. FIG. FI
The PLL circuit 327 of the FO control unit 321 generates a dot clock signal DCLK that is NH times the frequency of the horizontal synchronizing signal HSYNC given from the video decoder 220. The PLL circuit 328 also controls the vertical synchronization signal VSYN.
Line increment signal HI, which is the frequency of C multiplied by NV
Generate NC. Line increment signal HINC
Is used when the image is reduced in the vertical direction, as will be described later. When the frequency of the line increment signal HINC is the same as the second horizontal synchronization signal XHSYNC, the image is not reduced.

The vertical counter section 334 has a back porch storage section 402, a comparator 404, a back porch counter 406, a vertical counter 408, and a latch 410. The back porch storage unit 402 is the highway bus 20.
The back porch number BP given from the CPU 200 via 8 is stored. Here, the back porch number BP is the pulse number of the horizontal synchronizing signal HSYNC in the back porch period. The back porch counter 406 is supplied with the first horizontal synchronizing signal HSYNC, and the clock input terminal of the latch 410 is supplied with the second horizontal synchronizing signal XHSYNC. A line increment signal HINC is given to the clock input terminal of the vertical counter 408. Further, the vertical sync signal VSYN is applied to the reset input terminals of the back porch counter 406 and the vertical counter 408.
C is given. The comparator 404 compares the back porch number BP stored in the back porch storage unit 402 with the count value BPC of the back porch counter 406.

The output CMP of the comparator 404 is BP = BPC
When it is, it becomes H level, and when BP ≠ BPC, it becomes L level. The back porch counter 406 is the comparator 4
When the output CMP of 04 is L level, it is enabled,
The vertical counter 408 is enabled when CMP is at H level.

When the vertical synchronizing signal VSYNC is applied to the vertical counter section 334, the back porch counter 406 and the vertical counter 408 are reset. At this time, since the output CMP of the comparator 404 is L level, the back porch counter 406 is enabled, and the horizontal synchronization signal HS is output.
Count the number of YNC pulses. On the other hand, the vertical counter 408 remains stopped. Horizontal sync signal HSYNC
When the number of pulses of (1) is input to the back porch counter 406 by the number equal to the back porch number BP, BP = BPC. As a result, the output CMP of the comparator 404 becomes H level, the back porch counter 406 stops, and the vertical counter 408 starts counting up.
The count value CNT of the vertical counter 408 is latched 410 at the rising edge of the second horizontal synchronization signal XHSYNC.
, And is output as the vertical count VCNT. This vertical count VCNT indicates the scanning line number on the screen. When no reduction is performed in the vertical direction, the frequencies of the second horizontal synchronizing signal XHSYNC and the line increment signal HINC are equal, and thus the vertical count VCNT is equal to the number of pulses of the second horizontal synchronizing signal XHSYNC.

As described above, the vertical counter 408 and the latch 410 have a function as means for adding the scanning line numbers.

FIG. 12 is a timing chart showing the operation of the vertical counter section 334. The back porch period has passed, and the second horizontal synchronizing signal XHSY is generated in the effective video period.
When NC becomes L level, counting up of the vertical counter unit 334 is started. That is, in the effective video period, the value of the vertical count VCNT output from the vertical counter unit 334 is incremented by one each time the second horizontal synchronizing signal XHSYNC is generated by one pulse.

In this way, when the image is not reduced in the vertical direction, the vertical count VCNT is reset to 0 every time the vertical synchronizing signal VSYNC is generated by one pulse, and then the second horizontal synchronizing signal XHSYNC is generated by one pulse. Each time it occurs, the vertical count VCNT is incremented by one. On the other hand, when the image is reduced in the vertical direction, the second horizontal synchronizing signal XHSYNC and the line increment signal HIN
The vertical count VCNT increases in accordance with C. The operation will be described later.

FIG. 13 shows a FIFO memory unit 318.
4A and 4B are explanatory diagrams for explaining the vertical enlargement processing function according to FIG. 3, in which (a) shows input video data VDI, (b) shows output video data VDO, and (c) shows operations of two FIFO memories. ing. However, in FIG.
In (b), for convenience of illustration, the video data is drawn in the form of the original analog video signal VS.

As shown in FIG. 13C, two FIFs are
Input terminals and output terminals of the O memories 322 and 324 are complementarily and alternately switched by virtual toggle switches 323a and 323b. These virtual toggle switches 323a and 323b receive the two FIFO memories 322 and 32 according to the input enable signal RE and the output enable signal OE provided from the FIFO control section 321.
It is equivalently shown that the inputs and outputs of 4 are complementarily and alternately switched. Two FIFO memories 322,3
An input clock signal CLKI and an output clock signal CLKO are commonly supplied to 24. The frequency fCLKI of the input clock signal CLKI is obtained by multiplying the frequency of the horizontal synchronizing signal HSYNC by NH0, as can be seen from FIG. 3B, and the video signal V supplied to the video input terminal 221.
When S is an NTSC signal, it has a constant frequency of about 6 MHz. On the other hand, the frequency fCL of the output clock signal CLKO
KO is the HX of the frequency fCLKI of the input clock signal CLKI.
It is a doubled value (HX is an integer) (see FIG. 3B). That is, the set value (NH0 * HX) of the PLL circuit 326 that generates the output clock signal CLKO is the input clock signal C
HX of the set value NH0 of the PLL circuit 325 that generates LKI
Set to double. In this example, assume HX = 3.

First period TT1 of FIGS. 13 (a) and 13 (b)
In the first and third periods TT13, the first FIFO memory 3
The input video data VDI is written in 22 and the second FI
The output video data VDO is read from the FO memory 324. In the second period TT12, the input video data VDI is written in the second FIFO memory 324, and the first F
The output video data VDO is read from the IFO memory 322. As a result, in the first period TT11, the video data regarding the first scanning line L1 is stored in the first FIFO memory 32.
Written to 2. In addition, in the second period TT12, the video data regarding the second scanning line L2 is written in the second FIFO memory 324. In the example of FIG. 13, the frequency fCLKO of the output clock signal CLKO is the input clock signal CLK.
Since the frequency is set to 3 times the frequency fCLKI of I, the video data regarding the first scanning line L1 is read from the first FIFO memory 322 three times in the second period TT12.

FIG. 14 is an explanatory diagram showing how the image is enlarged and reduced in the vertical direction. FIG. 14A shows the input video data VDI, and FIG. 14B shows the output video data VDO.
Is shown. In the output video data VDO, each scanning line of the input video data VDI is repeated HX (= 3) times, so that the video is HX vertically.
(= 3) times as large. In FIG. 14B,
For example, “L1a”, “L1b”, and “L1c” indicate that the video data of the original scanning line L1 is repeatedly output three times. As described above, the frequency fCLKO of the output clock signal CLKO is changed to the frequency fCLKI of the input clock signal CLKI by using the two FIFO memories 322 and 324.
It is possible to enlarge the image in the vertical direction by an integral multiple by setting the integral multiple of.

The vertical reduction is performed by the FIFO shown in FIG.
It is realized by the PLL circuit 328 in the control unit 321 and the vertical counter 408 and the latch 410 in the vertical counter unit 334. FIG. 15 is a timing chart showing the reduction operation in the vertical direction. The line increment signal HINC generated by the PLL circuit 328 (see FIG.
(A)) shows the frequency fVSYNC of the vertical synchronization signal VSYNC.
Of the frequency fHINC. The second horizontal synchronizing signal XHSYNC (FIG. 15C) is the vertical synchronizing signal V
The frequency fXHSYNC is (NV0 * HX) times the frequency fVSYNC of SYNC, and the value of NV0 is the number of scanning lines in one field in the original analog video signal VS (hereinafter, referred to as "total number of image lines"). It is a constant value (NV0 = 262.5 in the case of NTSC signal) shown. Note that FIG.
As shown in (B), if the total number of image lines of the image represented by the analog image signal VS is NV0, the number of effective image lines is NVL, and the number of display lines when displaying the image on the display device is NVM, The set value NV of the PLL circuit 328 is given by the following equation. NV = NVM * HX * NVO / (HX * NVL) = NVM * NV0 / NVL However, NVM≤HX * NVL.

In the above equation, for example, NV0 = 262.
5, NVL = 240, NVM = 480 are substituted, NV = 5
It will be 25.

The vertical counter 408 (FIG. 11) counts up the count value CNT (FIG. 15 (b)) in response to the rising edge of the line increment signal HINC,
Further, the latch 410 receives the second horizontal synchronizing signal XHSYNC.
The count value CNT of the vertical counter 408 is latched in response to the rising edge of
(D)) is output.

In the example of FIG. 15, the frequency fHINC of the line increment signal HINC and the second horizontal synchronizing signal XHS are used.
YNC frequency fXHSYNC ratio (NV / NV0 * HX) is 2
/ 3, and accordingly, the vertical count VCNT (Fig. 15 (d)) has the same value of 1 for every second such as 0, 1, 2, 2, 3, 4, 4, 5. Repeated times. Since the vertical count VCNT indicates the vertical address in the VRAM 222, the video data of the third scanning line L1c and the video data of the fourth scanning line L2a are written in the third vertical address VCNT = 2. . As a result, the video data of the scanning line L1c first written at the third vertical address VCNT = 2 is changed to the next scanning line L2.
It is replaced with the video data of a. When this is repeated, the image data of the scanning lines located at the multiples of 3 are thinned out, and the result is reduced in the vertical direction.

FIGS. 14B and 14C show how the image is vertically reduced by the operation of FIG. The video data VDO expanded HX times by switching between the two FIFO memories 322 and 324 extends over the nine scanning lines L1a to L3c. Among them, the video data of the third scanning line L1c is the next. The video data of the scanning line L2a is replaced, and the video data of the sixth scanning line L2c is also replaced by the video data of the next scanning line L3a. As a result, the video is displayed in the vertical direction NV / (NV0
* HX) multiplied. The two FIFO memories 32
Since the image data is previously expanded in the vertical direction by HX times 2 and 324, the total vertical magnification MV is given by the following equation. MV = NV / NV0 (4)

Magnification factor MH for enlarging / reducing the image in the horizontal direction
Is the frequency fDCLK of the dot clock signal DCLK (FIG. 11) when writing the video data in the VRAM 222, and F
It is equal to the ratio fDCLK / fCLKO to the frequency fCLKO of the output clock signal CLKO (FIG. 13C) when reading the video data from the IFO memories 322 and 324. As described in FIG. 13, the frequency fCLKO of the output clock CLKO
Is HX times the frequency fCLKI of the input clock signal CLKI, and the input clock signal CLKI is a constant value according to the frequency characteristics of the composite video signal VS. Therefore,
The horizontal magnification MH is given by the following equation (5). MH = fDCLK / fCLKO = fDCLK / (HX * fCLKI) (5)

Further, as can be seen from FIG. 3B, the frequency fCLKI of the input clock signal CLKI is NH0 times the frequency fHSYNC of the horizontal synchronizing signal HSYNC, and fHSYN.
C and NH0 are constants. Also, dot clock signal DC
LK is N of the frequency fHSYNC of the horizontal synchronization signal HSYNC.
It has H times the frequency. Therefore, the above equation (5) can be rewritten as follows. MH = fDCLK / (HX * fCLKI) = fHSYNC * NH / (HX * fHSYNC * NH0) = NH / (HX * NH0) (6)

Equation (4) showing the vertical magnification MV and the horizontal magnification M
In the equation (6) indicating H, the three values that can be set from the CPU 200 are HX, NV and NH, all of which are set values in the FIFO control unit 321. These three values HX, NV and NH are determined by the following equations, for example.

HX = RND (MV) (7a) NV = NV0 * MV (7b) NH = NH0 * MH * HX (7c) Here, the operator RND rounds up the number below the decimal point in parentheses. Indicates an integer.

The expressions (7b) and (7c) are integers HX.
Since it holds even if any value is used as
It is also possible to determine the value of by an equation other than the equation (7a).

FIG. 16A shows the video OR represented by the original composite video signal VS, and FIG.
Indicates a VRAM space for storing the enlarged / reduced image MR. Here, the maximum number of pixels in the horizontal direction is 780, the number of effective pixels is 640, the maximum number of lines in the vertical direction is 525, and the number of effective lines is 480. The image MR in the VRAM space is displayed as it is on the color CRT 224 or the color liquid crystal display 226. Therefore, the vertical magnification MV and the horizontal magnification MH are equal to the ratio of the size of the video display window set on the display device and the size of the original video OR. The CPU 200 calculates the magnifications MV and MH from the size of the video display window set on the display device, and further calculates (7) above.
Three values HX, NV and NH are calculated according to a) to (7c) and set in the FIFO control unit 321.

As described above, in the above embodiment, the VRAM 2
When transferring the video data to 22, the video can be enlarged / reduced at an arbitrary magnification. Further, since the display position of the image can be arbitrarily set by the address calculation unit 312,
A moving image can be displayed at any position on the display device at any magnification.

E. Modifications: The present invention is not limited to the embodiments, and various modifications are possible as follows.

(1) The present invention can also be applied to the case where compressed digital video data is expanded and written in the VRAM 222. In this case, digital video data from the image decompression unit may be input to the input port of the moving image transfer controller 210.

(2) As the circuit for calculating the head address MADD given by the above equation (3), various structures other than the structure shown in FIG. 4 can be considered. For example, the same result can be obtained by replacing the adder in the address calculation unit 312 with a subtractor or changing the addition order.

Further, the multiplier 338 shown in FIG. 4 is replaced with an adder and a count-up counter, and the addition address ADAD stored in the addition address value storage unit 332.
May be added by the number of vertical counts VCNT of the vertical counter unit 334.

(3) As shown in FIG. 17, the PLL circuit 328 in FIG. 11 can be replaced with a 1 / N frequency divider 329. The 1 / N frequency divider 329 is reset by the vertical synchronizing signal VSYNC, and after being reset, divides the dot clock signal DCLK into 1 / N to generate a line increment signal HINC. Using the 1 / N frequency divider 329 in this way has the advantage that the jitter of the line increment signal HINC can be reduced as compared with the case where a PLL circuit is used.

(4) FIG. 18 is an explanatory diagram showing the structure and operation of a circuit for performing vertical enlargement and interpolation between scanning lines using three FIFO memories, and corresponds to FIG. As shown in FIG. 18 (c), this circuit
It includes three FIFO memories 421, 422, 423, three equivalent switches 431, 432, 433, two multipliers 441, 442, and an adder 450. As shown in FIGS. 18A and 18B, each period TT2
1, TT22, TT23, the video data for one scanning line is written in one FIFO memory, and the other two FIs are written.
Video data is read from the FO memory. The FIFO memory in which the video data is written and the FIFO memory in which the video data is read are selected in a predetermined order. FIG.
8C shows the connection state of the switches in the first half of the third period TT23. At this time, the video data of the first scanning line L1 read from the first FIFO memory 421 is multiplied by k1 by the first multiplier 441, and the second FIFO
The video data of the second scanning line L2 read from the O memory 422 is multiplied by k2 by the second multiplier 442. Since the outputs of the two multipliers 441 and 442 are added by the adder 450, the output video data VDO output from the adder 450 in the first half of the period TT23 is (L1 * k1 + L
2 * k2) (FIG. 18 (b)). Where the coefficient k
If both 1 and k2 are set to 0.5, the output video data VDO in the first half of the period TT23 has two scanning lines L1.
This is data obtained by simply averaging the L2 video data. k1,
If k2 is set to an appropriate value other than 0, a weighted average can be obtained. In the latter half of the period TT23, the video data of the second scanning line L2 is output as it is as the output video data VDO.

(5) FIF for enlarging the vertical direction
By providing a FIFO memory unit that functions similarly to the O memory unit 318 between the video decoder 220 and the color adjusting unit 320, vertical expansion and interpolation can be performed as in the configuration of FIG. In this case, the FIFO memory unit 318 of FIG. 3A is used as a circuit for adjusting the timing of data transfer without vertically expanding the video data VD.

In the present invention, the term "enlarge the image in the vertical direction" is not limited to the case of simply enlarging the image as shown in FIG. 13, but the case of enlarging the image by interpolating in the vertical direction as shown in FIG. Also means.

(7) R instead of a plurality of FIFO memories
It is also possible to construct a circuit having a function equivalent to that of the FIFO memory unit by using another type of video data buffer such as AM. In general, a plurality of video data buffers and a buffer control circuit are provided, and the plurality of video data buffers are switched in a predetermined order by the buffer control circuit, whereby the function of the FIFO memory unit described above can be realized.

(8) The function equivalent to the PLL circuit 325 of FIG. 3B is that the signal CLKO obtained by the PLL circuit 326 is used.
It can also be realized by using a circuit which receives (1 / NH0) as the input, frequency-divides and outputs, and resets with the horizontal synchronizing signal HSYNC.
As described above, although a plurality of PLL circuits are used in FIG. 3B, an equivalent circuit can be realized by combining frequency dividing circuits and the like.

(9) The color adjusting section 320 shown in FIG. 2 may be configured as a circuit which receives the digital video signal DS as a YUV signal and performs the hue conversion, and then outputs the component video data VD as an RGB signal.

[0076]

According to the present invention, when the video signal is transferred, the video transfer means has only to output the head address and the video signal for each scanning line, so that the video signal representing a moving image can be transferred at high speed. The effect is that you can do it.

[Brief description of drawings]

FIG. 1 is a block diagram showing a computer system as an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a moving image transfer controller 210.

FIG. 3 is a block diagram showing an internal configuration of a FIFO memory unit 318.

FIG. 4 is a block diagram showing an internal configuration of an address calculation unit 312.

FIG. 5 is a block diagram showing an internal configuration of a video controller 212.

FIG. 6 is an address map of VRAM 222.

FIG. 7 is an explanatory diagram showing a correspondence relationship between a VRAM 222 and a screen.

FIG. 8 is a plan view showing a moving image area MPA in the screen of the color monitor.

FIG. 9 is a timing chart showing a data transfer operation.

FIG. 10 is an explanatory diagram showing a memory space of an odd line field and an even line field when performing interlaced scanning.

FIG. 11 is a block diagram showing the internal configuration of a vertical counter section 334 and a FIFO control section 321.

FIG. 12 is a timing chart showing the operation of the vertical counter section 334.

FIG. 13 is an explanatory diagram showing a vertical enlargement operation of an image.

FIG. 14 is an explanatory diagram showing how the image is enlarged and reduced in the vertical direction.

FIG. 15 is a timing chart showing a vertical reduction operation of an image.

FIG. 16 is an explanatory diagram showing how the image is scaled up / down in the vertical and horizontal directions.

FIG. 17 is a block diagram showing a circuit configuration when the second PLL circuit 328 is replaced with a 1 / N frequency divider.

FIG. 18 is an explanatory diagram showing the configuration and operation of performing interpolation between scanning lines along with vertical expansion using three FIFO memories.

FIG. 19 is a block diagram of a computer system using a conventional DMA controller.

[Explanation of symbols]

 51R, 51G, 51B ... Video memory 52 ... Data bus 53 ... Address bus 54 ... Control bus 55 ... DMA controller 56 ... VRAM 56R, 56G, 56B ... VRAM 57 ... Monitor control unit 58 ... Monitor 59 ... CPU 200 ... CPU 202 ... Main memory 204 ... Host bus 206 ... Bridge 208 ... High-speed bus 210 ... Video transfer controller 212 ... Video controller 214 ... Expansion bus bridge 218 ... A / D converter 220 ... Video decoder 221 ... Video input terminal 222 ... VRAM 224 ... Color CRT 226 ... Color liquid crystal display 230 ... Low-speed bus 232 ... I / O controller 300 ... Interface 302 ... Bus control signal generation unit 304 ... Switching circuit 306 ... Switching control unit 312 ... Address arithmetic unit 314 ... Data output Input unit 318 ... FIFO memory unit 320 ... Color adjustment unit 321 ... FIFO control unit 322, 324 ... FIFO memory 323a, 323b ... Toggle switch 325-328, 510 ... PLL circuit 330 ... Offset address storage unit 332 ... Addition address value storage unit 334 ... Vertical counter section 338 ... Multiplier 340 ... Adder 350 ... Decoder 352 ... Address counter 354 ... Address latch 356 ... Data conversion circuit 358 ... VGA controller 402 ... Back porch storage section 404 ... Comparator 406 ... Back porch counter 408 ... Vertical counter 410 ... Latch 421, 422, 423 ... FIFO memory 431, 432, 433 ... Switch 441, 442 ... Multiplier 450 ... Adder 510 ... PLL circuit 511 ... Waveform shaping unit

Claims (1)

[Claims] 1. A computer system capable of displaying a moving image, comprising a microprocessor for executing various operations and controls according to a software program, a first bus connected to the microprocessor, and a common address and data. A second bus that is time-divisionally transferred by a signal line, a bridge that connects the first and second buses, a display device that displays a video, and a video signal of the video displayed on the display device is stored. A video memory, a video controller connected to the second bus for controlling writing and reading of a video signal to and from the video memory, a composite video signal of a moving image given from the outside, and a component video signal. And a video decoder for generating a synchronization signal, and each of the video represented by the composite video signal. A head address of each scanning line is generated for each scanning line and output to the second bus, and a component video signal of each pixel on the scanning line is output to the second bus after the head address.
And a video transfer unit for continuously outputting to the bus of the video controller, wherein the video controller generates an pixel address for each pixel on each scanning line from the start address, and A writing means for writing the component image signal of each pixel of the scanning line in the video memory.