JPH0962724A - Automatic layout device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the electromigration resistance of via holes of wiring with minimum line with by forming a plurality of via holes at the time of wiring layer replacement for a specific network with a heavy load among networks that are wired with minimum line width when a semiconductor integrated circuit is automatically laid out. SOLUTION: A network information file 31 contains new information wherein a plurality of via holes are arranged The automatic layout device arranges cells according to a layout library 12 and a layout rule, tests the cell arrangement, and wires a specific net according to a network list, the layout library 12, layout holes, and network information when the test result is OK. When a wiring layer is replaced in a network specified with the network information at the time of automatic wiring, a plurality of via holes are arranged. Then the automatic layout device performs normal net wiring and stores layout data in the file 14 when the result of a test of the automatic wiring is OK.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic layout apparatus for semiconductor integrated circuits, and more particularly to an ASIC (Appli).
(Cation Specific IC) and the like, the present invention relates to automatic placement of via holes when transferring wiring layers in an automatic layout method for semiconductor integrated circuits.

[0002]

2. Description of the Related Art First, a conventional automatic layout apparatus will be outlined with reference to FIG.

The automatic layout apparatus includes a netlist file 11, a layout library 12, and a layout rule file 13. The automatic layout apparatus firstly arranges cells based on the netlist, layout library, and layout rule. After performing (step s1), verifying the cell placement (step s2), and if the verification result is OK (OK), then perform wiring based on the netlist, layout library, and layout rule (step s3), the automatic wiring is verified (step s4). If the verification result is OK, the layout data is stored in the file 14.

In the conventional automatic layout apparatus, only the layout rule is checked at the time of automatic wiring, and the wiring that violates the layout rule is corrected.

Here, referring to FIG. 7, when performing an automatic layout, on a preset grid (wiring grid),
The wiring is arranged. In the illustrated example, the first and second wirings 21 and 22 are arranged along the wiring grid. Then, in order to maximize the wiring density, it is necessary to set the lattice spacing to the minimum value. In other words, the lattice spacing is set to the minimum value in which only one via hole 23 can be arranged at the time of wiring replacement.

As described above, when automatically laying out a semiconductor integrated circuit, only one via hole is arranged for a net wired with a minimum line width when the wiring layers are replaced.

[0007]

By the way, in a semiconductor integrated circuit, the film thickness of the wiring material attached to the inner surface of the via hole during manufacturing tends to be significantly deteriorated as compared with the flat portion of the wiring due to the miniaturization of the semiconductor process. is there.

That is, as shown in FIG. 8, the first wiring 21
Considering the case where the second wiring 22 and the second wiring 22 are connected to each other through the via hole 23 formed in the interlayer insulating layer 24, the wiring film thickness t2 on the inner surface of the via hole is the wiring in the flat portion (second wiring flat portion). It is about 20% of the film thickness t1. On the other hand, the peripheral length of the via hole 23 is about 4 times the minimum width of the flat portion, and as a result, the current density in the via hole 23 is about 1.3 times that of the flat portion.

It is generally known that the electromigration resistance deteriorates in inverse proportion to the square of the current density. Therefore, the electromigration resistance in the via hole 23 is about 0.6 times that in the flat portion. Become. Therefore, in the semiconductor integrated circuit, the reliability is significantly lowered in the via hole. In other words, when the automatic layout is performed as in the conventional case, there is a problem that the electromigration resistance is not sufficient in a heavily loaded net.

An object of the present invention is to provide an automatic layout device which can improve electromigration resistance.

[0011]

According to the present invention, there is provided an automatic layout apparatus used for automatically laying out a semiconductor integrated circuit, which is for a specific net having a heavy load among nets wired with a minimum line width. Thus, an automatic layout apparatus is provided which has a first means for arranging a plurality of via holes when transferring wiring layers.

The automatic layout device further comprises a file in which net information representing a net in which a plurality of via holes are to be arranged is stored, and the first means is, for example,
Wiring is performed for a specific net designated by the net information based on a netlist, a layout library, and a layout rule, and a plurality of via holes are arranged when the wiring layers are replaced.

A first means is a detecting means for detecting a net exceeding a predetermined load allowable value from the netlist to obtain net information, and the netlist for the specific net designated by the net information, Wiring may be performed based on a layout library and a layout rule, and designated net wiring means may be provided for arranging a plurality of the via holes when transferring the wiring layers.

Further, the first means is a wiring means for automatically wiring according to a netlist, a layout library, and a layout rule to obtain wiring data, and a load value of each net is checked in the wiring data in advance. Detecting means for detecting a net having a load value exceeding a predetermined load allowable value to obtain net information, and the above-mentioned wiring layer transfer to a specific net designated by the net information based on the wiring data. Via hole arranging means for arranging a plurality of via holes, and when a space error occurs between the specific net for the net adjacent to the specific net, the net list, the layout library, and the layout rule of the adjacent nets based on the layout rule. Rewiring means for performing rewiring may be provided.

Further, the first means detects a net exceeding a predetermined load allowable value from the net list and first detects the net.
Of the net information, and wiring for the specific net designated by the first net information based on the net list, the layout library, and the layout rule to replace the wiring layer. At this time, a designated net wiring means for arranging a plurality of the via holes, a wiring means for laying out all wirings to obtain wiring data, and a load value of each net in the wiring data are checked to determine a predetermined load allowable value. Detection means for detecting a net having a load value exceeding the second net information, and the via hole when transferring the wiring layer to the specific net designated by the second net information based on the wiring data. When a gap error occurs between the via hole arranging means for arranging a plurality of holes and the specific net adjacent to the specific net, Netlist, the layout library, and it may have a rewiring means for performing rewiring of said adjacent net based on the layout rules.

[0016]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below with reference to the drawings.

Referring to FIG. 1, the automatic layout apparatus according to the present invention comprises a netlist file 11, a layout library 12, a layout rule file 13, and a net information file 31, and the net information file 31 is a via hole. Net information for arranging a plurality of is stored.

The automatic layout apparatus first performs cell placement based on the layout library and layout rules (step ss1), verifies the cell placement (step ss2), and if the verification result is OK (OK). Then, the designated net is routed based on the netlist, the layout library, the layout rule, and the net information (step ss3), and the wiring layer is placed on the net designated by the net information during automatic routing. When the replacement occurs, a plurality of via holes are arranged. That is, the wiring of the designated net in which a plurality of via holes are to be arranged is performed.
After that, the automatic layout device performs normal net wiring based on the netlist, the layout library, and the layout rule (wiring nets other than the designated net: step ss4). Then, the automatic wiring is verified (step ss5). If the verification result is OK, it is stored in the file 14 as layout data.

FIG. 2 shows an example of the result (layout data) laid out as described above. In FIG. 2, a plurality of (two in FIG. 2) via holes 23 are arranged in the designated net, and in the designated net, the first wiring 21 and the second wiring 22 are connected by the plurality of via holes 23. Has been done.

Another example of the automatic layout apparatus according to the present invention will be described with reference to FIG.

This automatic layout apparatus includes a netlist file 11, a layout library 12, and a layout rule file 13 and a load allowable value file 32 in which load allowable values are stored. , And cell layout is performed based on the layout rule (step st1), and the cell layout is verified (step st2). If the verification result is OK (OK), the process proceeds to step st3. On the other hand, a net exceeding the load allowable value is automatically detected (extracted) from the netlist according to the netlist and the load allowable value (step st4), and the detected net is a net in which a plurality of via holes are arranged (net information). ) As file 33
To be stored.

At step st3, the designated net is wired based on the net list, the layout library, the layout rule, and the net information. Then, during automatic wiring, a plurality of via holes are arranged when the wiring layers are replaced in the net specified by the net information. That is, the wiring of the designated net in which a plurality of via holes are to be arranged is performed. After that, the automatic layout apparatus performs normal net wiring (wiring of nets other than the designated net: step st5). Then, the automatic wiring is verified (step st6). If the verification result is OK, it is stored in the file 14 as layout data.

Another example of the automatic layout apparatus according to the present invention will be described with reference to FIG.

This automatic layout apparatus includes a netlist file 11, a layout library 12, and a layout rule file 13 as well as an allowable load value file 3.
2, the cell placement is performed based on the netlist, the layout library, and the layout rule (step su1), and the cell placement is verified (step s).
u2). If the verification result is OK, wiring is automatically performed based on the netlist, layout library, and layout rule to obtain wiring data (step su3).

On the other hand, the automatic layout apparatus checks the load value of each net in the wiring data and detects (extracts) a net having a load value exceeding the load allowable value (step su4). Then, this detected net is stored in the file 33 as a net (net information) in which a plurality of via holes are arranged.

After obtaining the net information as described above,
The automatic layout device rearranges the via holes according to the wiring data and the net information (step su).
5). That is, the automatic layout device rearranges a plurality of via holes for the net specified by the net information.

After that, the automatic layout apparatus corrects the wiring according to the net list, the layout library, and the layout rule (step su6). That is, when a layout rule violation (error) occurs between adjacent wiring due to the rearrangement of a plurality of via holes, the wiring is corrected in that portion.

Next, the automatic layout apparatus verifies the automatic wiring (corrected wiring) (step su7). If the verification result is OK, it is stored in the file 14 as layout data.

Another example of the automatic layout apparatus according to the present invention will be described with reference to FIG.

This automatic layout apparatus includes a netlist file 11, a layout library 12, and a layout rule file 13 as well as an allowable load value file 3.
2, the cell placement is performed based on the netlist, the layout library, and the layout rule (step sv1), and the cell placement is verified (step s).
v2).

On the other hand, the automatic layout apparatus detects (extracts) a net exceeding the load allowable value from the net list (step sv3). Then, the detected net is stored in the file 33 as a net (first net information) in which a plurality of via holes are arranged.

After obtaining the first net information as described above, the automatic layout apparatus routes the designated net based on the net list, the layout library, the layout rule, and the first net information ( Step sv
4). During automatic wiring, a plurality of via holes are arranged when the wiring layers are replaced in the net designated by the first net information. That is, the wiring of the designated net in which a plurality of via holes are to be arranged is performed. After that, the automatic layout device performs normal net wiring (wiring of nets other than the designated net: step sv5).

After all the wiring data are obtained as described above, the automatic layout apparatus checks the load value of each net in the wiring data and detects (extracts) a net having a load value exceeding the load allowable value. ) (Step s
v6). Then, this detection net is file 3 as a net (second net information) in which a plurality of via holes are arranged.
Store in 4. Then, the via holes are rearranged according to the wiring data and the second net information (step sv7). That is, the automatic layout device rearranges a plurality of via holes for the net designated by the second net information.

After that, the automatic layout device corrects the wiring according to the netlist, the layout library, and the layout rule (step sv8). That is, when a layout rule violation (error) occurs between adjacent wiring due to the rearrangement of a plurality of via holes, the wiring is corrected in that portion.

Next, the automatic layout apparatus verifies the automatic wiring (corrected wiring) (step sv9). If the verification result is OK, it is stored in the file 14 as layout data.

[0036]

As described above, according to the present invention, when the automatic layout of the semiconductor integrated circuit is performed, the via hole when the wiring layer is transferred is automatically set only to the specific net having a heavy load among the nets having the minimum line width. Since a plurality of via holes are arranged, the current flowing per via hole is divided when N via holes (N is an integer of 2 or more) are arranged, resulting in a single via hole as compared with the case of a single via hole. The flowing current is 1 / N. Since the electromigration resistance is inversely proportional to the square of the current density, the electromigration resistance is N times the square of the present invention. For example, when two via holes are arranged, the electromigration resistance becomes four times. further,
Since the plurality of via holes are arranged only in the specific net having a heavy load, there is also an effect that an increase in the area due to the deterioration of the wiring property can be suppressed to the minimum.

[Brief description of drawings]

FIG. 1 is a flowchart for explaining a first embodiment of an automatic layout device according to the present invention.

FIG. 2 is a diagram showing a semiconductor integrated circuit laid out by an automatic layout device according to the present invention.

FIG. 3 is a flow chart for explaining a second embodiment of the automatic layout device according to the present invention.

FIG. 4 is a flow chart for explaining a third embodiment of the automatic layout device according to the present invention.

FIG. 5 is a flow chart for explaining a fourth embodiment of the automatic layout device according to the present invention.

FIG. 6 is a flowchart for explaining a conventional automatic layout device.

FIG. 7 is a diagram showing a semiconductor integrated circuit laid out by a conventional automatic layout apparatus.

FIG. 8 is a view showing a cross section of a via hole.

[Explanation of symbols]

 11 Netlist File 12 Layout Library 13 Layout Rule File 21 First Wiring 22 Second Wiring 23 Via Hole 24 Interlayer Insulation Layer 31 Net Information File 32 Load Allowance Value File

Claims (5)

[Claims] 1. An automatic layout device used when automatically laying out a semiconductor integrated circuit, wherein a plurality of via holes are provided when a wiring layer is transferred to a specific net having a heavy load among nets wired with a minimum line width. An automatic layout apparatus comprising first means for individually arranging. 2. The automatic layout apparatus according to claim 1, further comprising a file in which net information representing a net in which a plurality of via holes are to be arranged is stored, and the first means is designated by the net information. An automatic layout apparatus is characterized in that wiring is performed for a specific net based on a netlist, a layout library, and a layout rule, and a plurality of via holes are arranged when the wiring layers are replaced. 3. The automatic layout apparatus according to claim 1, wherein the first means detects a net exceeding a predetermined load allowable value from a net list to obtain net information, and Wiring is performed based on the netlist, layout library, and layout rule for a specific net specified by net information,
An automatic layout apparatus comprising: a designated net wiring unit that arranges a plurality of the via holes when the wiring layers are replaced. 4. The automatic layout device according to claim 1, wherein the first means is wiring means for automatically performing wiring according to a netlist, a layout library, and a layout rule, and A detection means for checking the load value of each net in the wiring data to detect a net having a load value exceeding a predetermined load allowable value to obtain net information, and for the specific net designated by the net information, Via hole arranging means for arranging a plurality of via holes at the time of transferring the wiring layer based on wiring data, and the netlist and the layout live when an interval error occurs between the specific net and a net adjacent to the specific net. Rally and rewiring means for rewiring the adjacent nets based on the layout rule. An automatic layout device characterized by: 5. The automatic layout apparatus according to claim 1, wherein the first means detects a net exceeding a predetermined load allowable value from a net list to obtain first net information. Detecting means and wiring for the specific net designated by the first net information based on the netlist, layout library, and layout rule, and a plurality of via holes are arranged when the wiring layers are replaced. Designated net wiring means, wiring means for laying out all the wirings to obtain wiring data, and checking the load value of each net in the wiring data to find a net having a load value exceeding a predetermined load allowable value. Detecting means for detecting and obtaining second net information, and the distribution means for the specific net designated by the second net information based on the wiring data. Via hole arranging means for arranging a plurality of the via holes at the time of line layer transfer, and the net list, the layout library, and the layout rule when an interval error occurs between the specific net and the net adjacent to the specific net. And a rewiring means for rewiring the adjacent net based on the above.