JPH0962567A - Memory for recording and reproducing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory which is operated at a high speed regardless of extension of the memory scale and can constitute a system which has low power consumption and low noise and is inexpensive as the whole of the system. SOLUTION: A memory 2 is provided with registers 5.1 to 5.2 where the start address of the memory 2 can be stored; and at the time of data write to the data memory 2, data write is started from the start address, and the address of the memory 2 at the time of the end of write is stored in a register 6.1 or 6.2 for end address storage by an external write end signal. At the time of read of the data memory 2, data between the address in the register where the start address of the memory 2 is stored and the address in the register where the corresponding end address is stored is read out from the data memory 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing memory having a data recording / reproducing function, and particularly realizes an inexpensive recording / reproducing function in a portable device or the like.

[0002]

2. Description of the Related Art Due to the progress of semiconductor process technology in recent years,
Data recording is moving from analog to digital. There is also a demand for a semiconductor memory that realizes an inexpensive recording / reproducing function even in a mobile device.

Conventionally, as a data recording / reproducing means, a system configuration as shown in FIG. 15 has been adopted. FIG.
In the figure, 1 is a microcomputer and 2 is a memory. Conventionally, the recording and reproducing functions to and from the memory have been realized by the software of the microcomputer 1. For example, during recording, the microcomputer 1 calculates the address and data of the memory 2,
Write to the memory 2 sequentially. The microcomputer 1 stores the address at the start of recording and the address at the end of recording at that time, and at the time of reproduction, the microcomputer 1 sequentially reads the stored recording start address to the recording end address from the memory 2. The recording / reproducing function is realized by the above operation.

[0004]

The system configuration shown in the conventional example is a very efficient system that can be managed entirely by software when the memory 2 is small in scale.
The efficiency becomes worse as the memory scale increases. That is, it is assumed that the address space of the memory 2 is 1M, and SR
Assuming AM, the number of interface lines for addressing the microcomputer 1 and the memory 2 is 20. As the number of address interface lines between the microcomputer 1 and the memory 2 increases, the address interface lines of the microcomputer 1 become insufficient and it becomes impossible to directly control the address of the memory 2. Therefore, normally, the address interface line between the microcomputer 1 and the memory 2 is not provided. , A conversion circuit for generating the real address of the memory 2 is required. This real address generation circuit is
It may be a serial-to-parallel converter for converting 1-bit serial data from the above into 20-bit parallel data, or a bank switching system for inputting a high-order address and a low-order address separately twice and outputting as parallel data.
In this way, as the memory scale increases, the system becomes complicated, and whichever method is adopted, the access speed of the memory 2 depends on the circuit that generates the real address.

However, the biggest problem is that an increase in memory address lines leads to an increase in power consumption and noise in the system. That is, high-speed access to the memory drives the wiring capacity of the address line in the system at high speed, resulting in increase in power consumption. Further, high-speed driving of the wiring capacitance causes noise in the power supply line, which causes SN deterioration of the source signal in other peripheral devices, particularly in a system handling analog signals.

It is an object of the present invention to provide a memory which operates at high speed even if the scale of the memory is increased, and has a low power consumption, low noise, and an inexpensive system as a whole system.

[0007]

[Means for Solving the Problems] To achieve the above object,
In the present invention, the memory has a register capable of storing the start and end addresses of the read and write addresses, and the data between the start and end addresses has a readable and writable memory configuration.

That is, the invention according to claim 1 is a data memory for storing data, a plurality of registers (hereinafter referred to as register S group) for storing a start address of the data memory, and a plurality of registers for storing the start address. There are provided a plurality of registers (hereinafter referred to as register E group) for storing the end address of the data memory corresponding to each register, and an interface circuit capable of storing data in the register S group and the register E group. Then, a memory having means for reading data from the data memory from a start address to an end address stored in a pair of the register S group and the register E group is configured.

The invention of claim 2 is the same as that of claim 1.
A memory having means for writing data to the data memory from a start address to an end address stored in a pair of a register S group and a register E group is configured.

The invention of claim 3 is the same as that of claim 1.
A means for writing data from the start address stored in the register S group to the data memory, and a write end signal from the outside to stop writing to the data memory, and an address to the data memory at the time of the stop. Is configured in a register E group register corresponding to the register S group start address register.

According to a fourth aspect of the present invention, there is provided a memory having the memory writing means according to the second aspect and the memory writing means according to the third aspect.

According to a fifth aspect of the present invention, there is provided a memory according to the third or fourth aspect, which has a unit for reading the data in the register stored in the register E group according to the third aspect.

According to a sixth aspect of the present invention, the address space of the data memory is divided into a plurality of memory areas, flag data is set for each memory area, and when the data memory is read, the flag data is true. In the case of, the memory according to any one of claims 1 to 5 is configured to have means for skipping and reading the corresponding memory area.

According to a seventh aspect of the present invention, there is provided an interface circuit capable of setting a data word length at the time of reading and writing the data memory, and a reading and writing means of the data memory at the set data word length. The memory according to any one of claims 1 to 6 is configured.

According to the present invention, there is provided a write mask input signal from the outside, and when the write mask signal is true, writing to the data memory is prohibited.
The memory according to any one of claims 2 to 7, comprising means for maintaining an address to the data memory, and means for sequentially writing data when the write mask signal is false.

[0016]

The memory according to claim 1 has a register capable of storing a start address and an end address of the memory, and has a memory configuration capable of reading data between the start address and the end address. It is possible to read sequentially without having to directly access the memory address from the outside.

According to another aspect of the present invention, there is provided a memory having a register capable of storing a start address and an end address of the memory.
The data structure between the start and end addresses has a readable and writable memory structure, so that it is possible to sequentially read and write the data without the need to directly access the memory address from the outside.

According to another aspect of the present invention, there is provided a memory having a register capable of storing a start address and an end address of the memory.
The address of the memory at the end of the write is stored in the register for storing the end address according to the write end signal from the outside. Also, it becomes possible to write efficiently.

Since the memory according to claim 4 has both write functions of the memory according to claim 2 and claim 3, writing to the memory when the write data amount is previously determined, and Both functions of writing to the memory can be realized when the amount of write data is not defined in advance.

In the memory according to the fifth aspect, since the stored end address can be read through the interface circuit, the address space of the already written memory can be managed by the external host, and the effective memory capacity can be obtained. It can be used.

In the memory according to the sixth aspect, the memory is divided into a plurality of areas, and for each area, flag data indicating whether the area data is valid or invalid can be written into the memory, and at the time of reading, the invalid flag. It is possible to skip the memory area in which is written and read. Therefore, for example, in the case of voice, by setting an invalid flag in the area when there is no sound, it is possible to read only the voiced section and realize a high-speed playback function.

In the memory according to the seventh aspect, it is possible to set the data word length (data width) at the time of reading and writing of the memory, and it is possible to flexibly deal with input data of various data widths. .

In the memory according to the eighth aspect, write is prohibited by a write mask signal from the outside, and
Since it has a function to hold the address to the data memory, if you control not to write invalid data by this write mask signal, only valid data can be written, and more effective use of memory capacity is possible. Is possible.

[0024]

1 shows a memory configuration according to claim 1 of the present invention. 1, 2 is a memory, 3 is an address counter, 4 is a control and interface circuit, and 5.1 to 1.
6.2 is a register and 7 to 8 are selectors. Each of the registers 5.1 to 6.2 can store an arbitrary value by the control and interface circuit 4.

First Embodiment In FIG. 1, the register 5.1 and the register 5.2 store the start address of the address counter 3, and the register 6.1 and the register 6.2 are
The ending address of the address counter 3 is stored. Register 5.1 and register 6.1 are paired with each other, and register 5.2 and register 6.2 are paired with each other.

In this embodiment, when reading data from the data memory 2, the control and interface circuit 4 is used.
Through, follow the steps below. 1 Specify a register pair. (In this case, register 5.
1 and 6.1) 2 Write the start and end addresses to the specified pair of registers 5.1 and 6.1. 3 Start reading from the data memory 2.

By the above operation, the data in the data memory 2 between the designated addresses (between the start address and the end address) are sequentially read.

FIG. 2 shows a memory configuration according to claim 2 of the present invention. 2, the same components as those in FIG. 1 are given the same numbers. Similar to the configuration example shown in FIG. 1, each of the registers 5.1 to 6.2 can store an arbitrary value by the control and interface circuit 4.

In this embodiment, the start addresses of the address counter 3 are stored in the registers 5.1 and 5.2, and the registers 6.1 and 6.2 are
The ending address of the address counter 3 is stored. Register 5.1 and register 6.1 are paired with each other, and register 5.2 and register 6.2 are paired with each other.

In FIG. 2 of the present embodiment, when reading data from the data memory 2, the same operation as in FIG. 1 of the present embodiment can be performed. When data is written in the data memory 2, the control and interface circuit 4 is used to perform the following procedure. 1 Specify a register pair. (In this case, register 5.
1 and 6.1) 2 Write the start and end addresses to the specified pair of registers 5.1 and 6.1. 3 Start writing to the data memory 2.

After the above operation, the input data is sequentially supplied to the data memory 2, so that the data is sequentially written in the data memory 2 between the designated addresses (between the start address and the end address).

FIG. 3 shows a memory configuration according to claim 3 of the present invention. In FIG. 3, the same components as those in FIGS. 1 and 2 are given the same numbers. As in the configuration example shown in FIG. 1, each of the registers 5.1 to 5.2 has
An arbitrary value can be stored by the control and interface circuit 4.

Embodiment 3 In FIG. 3, the register 5.1 and the register 5.2 store the start address of the address counter 3, and the register 6.1 and the register 6.2 are
The ending address of the address counter 3 is stored. Register 5.1 and register 6.1 are paired with each other, and register 5.2 and register 6.2 are paired with each other.

This embodiment is different from FIG. 3 in that in FIG.
The data stored in the registers 6.1 and 6.2 could directly store an arbitrary value by the control and interface circuit 4, whereas in FIG.
The output value of the address counter 3 when the write end signal is generated is the data stored in the register 6.1 or 6.2.

In this embodiment, also in FIG. 3, the data memory 2
When the data is read, it can be executed in the same manner as in FIG. 1 of the present embodiment. When data is written in the data memory 2, the control and interface circuit 4 is used to perform the following procedure. 1 Specify a register pair. (In this case, register 5.
1 and 6.1) 2 Write the start address to the specified pair of registers 5.1. 3 Start writing to the data memory 2. 4 Finish writing to the data memory 2.

After the above operation, by inputting the input data to the data memory 2 sequentially, the data is sequentially written to the data memory 2 from the start address stored in the register 5.1. At the end of writing to the data memory 2, the output of the address counter 3 at that time is stored in the register 6.1.

Although the respective embodiments based on claims 1 to 3 have been shown in FIGS. 1 to 3 and the respective operations have been described, the respective embodiments are effective when used for the following purposes. Claim 1
In an embodiment based on, a plurality of basic voice patterns and melody patterns are stored in a memory such as a ROM in advance, and if the stored start address and end address are known in advance, the address setting will be used to adapt to the situation. , Any pattern can be read.

In the embodiment according to the second aspect, it is possible to sequentially record the data having the predetermined recording time in the memory.

According to the third aspect of the present invention, it is possible to sequentially record the data for which the recording time is not predetermined in the memory and read the data between the recorded addresses.

As described in claim 4 (not shown), if the recording means of FIG. 2 and the recording means of FIG. 3 are held together, the recording means can be used properly according to the application. .

FIG. 4 shows a memory configuration according to claim 5 of the present invention. 4, the same components as those in FIG. 3 are given the same numbers. 4 is different from FIG. 3 in that
The stored data in the register group that stores the end addresses of the registers 6.1 and 6.2 can be read out to the outside through the control and interface circuit 4. Thereby, for example, as described in the section of the embodiment (FIG. 3) based on claim 3, after performing the write operation to the data memory 2 using the pair of the register 5.1 and the register 6.1, The end address stored in the register 6.1 can be read out, and at the time of the next recording, the address next to the address of the register 6.1 can be stored in the start address of the register 5.2. As a result, the second recording can be performed without destroying the previously recorded data in the data memory. In addition, the memory area can be effectively used without wasting it.

The address counter 3 of FIGS. 1 to 4 described above performs an operation of sequentially incrementing from the start address to the end address, but this circuit can be configured as shown in FIG. In FIG. 5, 10 is an adder, 11 is a register, 12 is a match detection circuit, and 13 is a selector.

The address counter shown in FIG. 5 operates as follows. At the start of operation, the selector 13
The start address is selected and the start address is stored in the register 11. After that, the selector 13 is switched to select the output side of the adder 10, and the value obtained by adding 1 to the current value of the register 11 is stored in the register 11. When the output of the register 11, that is, the address to the data memory matches the end address, the match detection circuit 12 generates an end signal. This end signal can be notified to the outside through the control and interface circuit 4. Further, at the time of reading the data memory of FIGS. 1 to 4 and at the time of writing to the data memory of FIG. 2, the clock supply to the register 11 is stopped by the end signal from the coincidence detection circuit. This enables reading or writing of memory data between the start address and the end address. At the time of writing to the data memory of FIGS. 3 to 4, the clock supply to the register 11 is stopped by the write end signal notified from the outside. In this case, data can be written in the memory from the start address to the address at the time when the external write end signal is generated.

FIG. 12 shows the control and interface circuit 4
An example of a control register mapped to the IO address space of Each control register is an IO in this memory chip.
It is mapped in the address space, and various operations can be realized by setting this register through the interface pin.

In FIG. 12, 101 is a register number designation register, 102 is a start address designation register,
Reference numeral 104 is a read execution start register, and 103 is a write execution start register.

In the embodiment described with reference to FIG. 3, FIG.
All operations are possible by preparing the control register shown in FIG. 2 and setting this control register from the external interface pin. FIG. 13 shows the order of setting the control registers 101 to 104 at the time of writing to and reading from the data memory in the embodiment of FIG. As described above, in this memory chip, all operations can be realized by setting the control register mapped in the IO address space in the memory chip by the interface pin.

FIG. 14 shows an example of system configuration when the memory chip of this embodiment is used. IO pins between the host microcomputer and this memory consist of memory interface pins, memory input data pins, and memory output data pins. Through the memory interface pins, all control registers as shown in FIG. 12 can be set.

Compared with the conventional system configuration shown in FIG. 15, the increase in the address lines caused by the increase in the conventional memory scale does not pose a problem here. Therefore, the memory configuration of the present invention has an excellent effect that it operates at high speed even if the memory scale increases, and that an inexpensive system with low power consumption and low noise can be constructed as a whole system.

Next, an embodiment based on claim 6 is shown in FIG. 6, the same components as those in FIG. 3 are given the same numbers. 6 is different from FIG. 3 in that the output result of the data memory 2 is fed back to the address counter 3.

The purpose of this embodiment is to skip a region that is meaningless in terms of data and read it at high speed. As an implementation method, the address space of the data memory is divided into a plurality of memory areas in advance, and a flag area is set for each memory area. This flag is a flag that means that the area can be skipped. FIG. 8 shows an example of area division of the data memory in this embodiment. In FIG.
S1 and E1 are the register 5.1 and the register 6.
Represents the address value stored in 1. Also S2, E2
Represents the address values stored in the registers 5.2 and 6.2 in FIG. 2.1 represents the area from the addresses S1 to E1 of the data memory, and 2.2
Represents an area from the address S2 to E2 of the data memory. Apart from this, the data memory is 20.1-2
It is divided into a plurality of areas as represented by 0.10. The data structure of each area is BANK HE as shown by 20.
It is composed of an ADER area and a data area. BANK H
A flag signal is recorded in the EADER area, and this flag signal indicates whether or not the data in the area in charge can be skipped. This flag signal is written from the host microcomputer when writing to the data memory.

FIG. 7 shows a configuration example of the address counter 3 in the embodiment shown in FIG. In FIG. 7, 10 is an adder,
11 is a register, 12 is a match detection and comparison circuit, 13-
Reference numeral 14 is a selector, and 15 is an address skip control circuit.

The address counter shown in FIG. 7 operates as follows. At the start of operation, the selector 13
The start address is selected and the start address is stored in the register 11. In addition, the selector 14 selects +1 and then the selector 13 is switched to select the output side of the adder 10, and the value obtained by adding 1 to the current value of the register 11 is stored in the register 11. It

The operation up to this point is similar to that described with reference to FIG. In the address skip control circuit 15, BA
The address where the NK HEADER exists and the flag data are detected. When both are true, the selector 14 is set to +12.
Switch to 8 side. Here, BANK HEADER
It is assumed that the area is taken every 128 addresses.
As a result, the data memory can be read while skipping the area to which the flag is added. The match detection and comparison circuit 12 detects whether the output value of the register 11 is equal to the end address value or the register 11 is larger,
When either is true, the end signal is generated and
The clock supply to the register 11 is stopped. This end signal can be notified to the outside through the control and the interface.

In the embodiment shown in FIG. 6 according to claim 6,
It is possible to use, for example, if a voice is recorded at the time of recording in advance, a flag is added to the bank header portion of a portion where the voice is low to some extent, and only meaningful sounds to which the flag is not added are read out.

Next, an embodiment based on claim 7 will be described.
In claim 7, the data width to be stored in the data memory in FIGS. 1 to 4 and 6 is provided with an interface capable of being arbitrarily set, and writing to and reading from the data memory with an arbitrary data width are possible. . FIG. 9 shows an embodiment of an address counter that realizes this function. In FIG. 9, 10.1 to 10.2 are adders, 11.1 to 11.2
Is a register, 12.1 to 12.2 is a match detection circuit, 1
3.1 to 13.2 are selectors.

The address counter shown in FIG. 9 operates as follows. At the start of operation, the selector 13.1
Indicates that the start address has been selected and the selector 13.2 has selected 0. The register 11.1 stores the start address, and the register 11.2 stores the value 0. After that, the selector 13.1 changes the output side of the adder 10.1 to
The selector 13.2 is switched to select the output of the adder 10.2, and the value obtained by adding 1 to the current value of the register 11.2 is stored in the register 11.2.
Stored in 1.2. The match detection circuit 12.2 compares the memory data width with the value of the register 11.2 and outputs 1 if they match and 0 if they do not match. When they further match, the selector 13.2 is switched to the 0 side and the register 1
Enter 0 in 1.2. In other words, 10.2 of the components,
11.2, 12.2, 13.2 form a counter for the memory data width. For example, when 3 is given to the memory data width, the above-mentioned constituent elements constitute a quaternary counter of 0 to 3, and the coincidence detection circuit 12.2 coincides with each increment of the quaternary counter by 4, Adder 10.1
Is added to.

The output of the register 11.1 is compared with the end address by the match detection circuit 12.1, and if they match, an end signal is generated and the operation of the address counter is stopped. That is, the register 11.
The output of 2 is output as the lower address of the memory and performs the counter operation for the memory data width.
The output of 1.1 is output as the memory upper address,
Count from the start address to the end address.

FIG. 10 shows an example of data storage in the data memory when the data width is 4 bits. The memory upper address of the address counter shown in FIG. 9 shows the head address of each data in the data memory 2 shown in FIG. 10, and the lower address shows the position in the middle of the data width.

At the time of writing to the data memory 2, 1-bit data decomposed by a parallel-serial converter (not shown) for converting 4-bit parallel input data from the outside into serial data is written to the data memory, and the data memory 2 is read. At the time of reading, the output serial data can be output as 4-bit parallel data by a serial-parallel converter (not shown) that converts 4-bit parallel data.

If the address counter shown in FIG. 9, the parallel-serial converter, and the serial-parallel converter are provided,
It is possible to adopt a memory configuration that supports any data width,
Since the system can be flexibly constructed, its practical effect is great.

Next, an embodiment based on claim 8 is shown in FIG. 11, the same components as those in FIG. 3 are given the same numbers. 11 is different from FIG. 3 in that a write mask signal for inhibiting writing of input data to the data memory 2 is directly supplied from an external pin, and when this signal is true, the memory write control circuit 9
Therefore, writing to the memory is prohibited. The write mask signal is also input to the address counter 3 and has a means for stopping the address counter when this signal is true.

The purpose of this embodiment is to inhibit the writing of the data of the area having no meaning in terms of data to the data memory 2 by the write mask signal.

In the embodiment described in the description of claim 6, a flag is provided for the data of the area that is meaningless in terms of data,
At the time of reading, it is possible to read at high speed by skipping the area with the flag, and it is also possible to read all the data without using this function. However, the data memory of the invention of claim 6 stores all data. On the other hand, according to the invention of claim 8, only high-speed reading can be performed, but since meaningless data is not stored, the memory area can be effectively used.

[0064]

According to the present invention, the increase in the number of address lines caused by the increase in the memory scale in the related art does not pose a problem as compared with the conventional system configuration. Therefore, the memory configuration of the present invention has an excellent effect that it operates at high speed even if the memory scale increases, and that a low-power-consumption, low-noise system can be constructed as a whole system.

The memory according to any one of claims 1 to 2 has a register capable of storing a start address and an end address of the memory, and has a memory configuration capable of reading and writing data between the start and end addresses. Since this is done, it is possible to read and write sequentially without having to directly access the memory address from the outside.

In the memory according to the third aspect, the address of the memory at the end of writing is stored in the register for storing the end address in response to the write end signal from the outside. Data can be efficiently written.

Since the memory according to claim 4 has both the write functions of the memory according to claim 2 and the memory according to claim 3, writing to the memory when the write data amount is determined in advance, and Both functions of writing to the memory can be realized when the amount of write data is not defined in advance.

In the memory according to the fifth aspect, since the stored end address can be read out through the interface circuit, the address space of the already written memory can be managed by the external host, and the memory capacity can be reduced. Effective utilization becomes possible.

In the memory according to the sixth aspect, the memory is divided into a plurality of areas, and for each area, flag data indicating whether the area data is valid or invalid can be written in the memory, and at the time of reading, the invalid flag. It is possible to read by skipping the memory area in which is written. For that reason,
For example, in the case of voice, by setting an invalid flag in the area when there is no sound, only the voiced section can be read out, and a high-speed playback function can be realized.

In the memory according to claim 7, it is possible to set the data word length (data width) at the time of reading and writing of the memory, and it is possible to flexibly deal with input data of various data widths. .

In the memory according to claim 8, writing is prohibited by a write mask signal from the outside, and
Since it has a function to hold the address to the data memory, if you control not to write invalid data by this write mask signal, only valid data can be written, and more effective use of memory capacity is possible. Is possible.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory according to the present embodiment.

FIG. 2 is a configuration diagram of a memory according to this embodiment.

FIG. 3 is a block diagram of a memory according to the present embodiment.

FIG. 4 is a configuration diagram of a memory according to this embodiment.

FIG. 5 is an address counter circuit diagram of the memory shown in FIGS.

FIG. 6 is a configuration diagram of a memory according to this embodiment.

FIG. 7 is an address counter circuit diagram of the memory shown in FIG.

FIG. 8 is a memory map diagram of a memory configuration example of the present embodiment.

FIG. 9 is an address counter circuit diagram of the memory shown in FIGS. 1 to 4 and 6;

FIG. 10 is a diagram showing an example of storage in a memory when the data width is 4 bits.

FIG. 11 is a configuration diagram of a memory according to the present embodiment.

FIG. 12 is a diagram showing an interface control register in a memory configuration example of this embodiment.

FIG. 13 is a diagram showing an operation example using the interface control register of the present embodiment.

FIG. 14 is a system configuration diagram of this embodiment.

FIG. 15 is a system configuration diagram of a conventional example.

[Explanation of symbols]

 1 Microcomputer 2 Data Memory 3 Address Counter 4 Control and Interface Circuit 5.1-5.2, 6.1-6.2 Register 7-8, 13-14, 13.1-13.2 Selector 9 Memory Write Control Circuit 10,10.1-10.2 Adder 11,11.1-11.2 Register 12,12.1-12.2 Match detection circuit 15 Address skip control circuit 20.1-20.10 Divided memory area 2.1 First Recorded Area 2.2 Second Recorded Area 20 Data Structure of Memory Area

Claims (8)

[Claims] 1. A data memory for storing data, and a register S for storing a start address of the data memory.
Group, a register E group for storing the end address of the data memory corresponding to each of the plurality of registers for storing the start address, and an interface capable of storing data in the register S group and the register E group A recording / reproducing memory provided with a circuit, and means for reading data from the data memory from a start address to an end address stored in a pair of a group of the register S and a group of the register E. 2. From a start address to an end address stored in a pair of a register S group and a register E group,
The recording / reproducing memory according to claim 1, further comprising means for writing data in the data memory. 3. A means for writing data to the data memory from a start address stored in a register S group, and writing to the data memory is stopped by a write end signal from the outside, and at the time of the stop. 2. The recording / reproducing memory according to claim 1, further comprising means for storing an address to the data memory in a register of a register E group corresponding to a register of a start address of the register S group. 4. A recording / reproducing memory comprising the memory writing means according to claim 2 and the memory writing means according to claim 3. 5. The recording / reproducing memory according to claim 3 or 4, further comprising means for reading the data of the registers stored in the register E group. 6. An address space of the data memory is divided into a plurality of memory areas, flag data is set for each of the memory areas, and when the data memory is read, the flag data is true. The recording / reproducing memory according to any one of claims 1 to 5, further comprising means for skipping and reading the memory area. 7. An interface circuit capable of setting a data word length when reading and writing the data memory, and a reading and writing means for the data memory with the set data word length. Item 7. The recording / reproducing memory according to any one of items 6. 8. A means for inhibiting writing to a data memory when an external write mask signal is true, and a means for maintaining an address to the data memory, and sequentially when the write mask signal is false. The recording / reproducing memory according to claim 2, further comprising a unit for writing data.