JPH0962239A - Display control device and method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display control device in which the image of a display device is made clear by enabling a sampling clock and image data to be adjusted in phase and in a phase time corresponding to a display mode. SOLUTION: This display control device is provided with a clock generating part 1.04 inputting a horizontal synchronous signal of synchronous signal so as to generate a picture element synchronous clock signal, a system control part 1.91 controlling the clock generating part 1.04, an A/D converter 1.03 converting an image signal of input video signal to a corresponding digital signal synchronizing with the picture element synchronous clock generated from the clock generating part 1.04, and an output means 1.4 inputting the synchronous signal, the picture element synchronous clock and the above-stated digital signal so as to output them to a display device 1.05, and the clock generating part 1.04 includs a delay means adjusting delay of the horizontal synchronous signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for inputting a video signal including an image signal and a synchronizing signal and displaying the video signal on a display.

[0002]

2. Description of the Related Art In recent years, personal computers have come into widespread use not only for chemical technology data processing but also for applications requiring graphic display such as CAD and design. Along with this, there is a demand for improving the image quality and quality of the graphic display of computer displays.

As a method of satisfying such a demand, a method of increasing the display resolution and a frame (field)
There is a method of increasing the frequency, etc. By the former method,
A fine image can be obtained, and the latter method enables display with less flicker. Therefore, in addition to the VGA mode with a resolution of 640x480, which was the mainstream in the past, 800x600, 102
High resolution S of 4 x 768 and even 1280 x 1024
Displays that can display VGA mode are becoming common, and the vertical synchronizing frequency is 60 Hz to 70H.
It tends to increase to z. In this way, personal
The display capabilities of computers are improving as well as those of workstations. On the other hand, the display
As a device technology, flat panel displays using liquid crystal have been attracting attention in recent years. The flat panel display is widely used in the future as a monitor for not only a laptop computer or a notebook computer but also a desktop computer because of its compactness and extremely low emission of electromagnetic waves. It is expected that

As one of such flat panel displays, a dot matrix type display using a ferroelectric liquid crystal (FLC) (hereinafter referred to as "FLCD").
Abbreviated. ) Has been put to practical use. FLC has a property called memory property (the property that the ON / OFF state of the liquid crystal is maintained even if the electric field required for switching is removed), and it is very difficult for conventional liquid crystal technology to utilize this. A large flat screen display can be realized.

That is, by using the partial rewriting scanning in which a line having a change in the image data to be displayed is selected and scanning is preferentially performed on the display, it is possible to perform an efficient screen refresh operation. Even if the upper limit frequency for full frame rewriting (hereinafter simply referred to as the frame frequency for simplicity) tends to decrease due to the increase in the number of display lines accompanying the increase in size / high definition of the display, a sufficient response speed is realized as a computer screen. You can do it. In the current FLCD technology, each pixel of the display can be in either an ON state or an OFF state, so that it is basically a binary display. Therefore, in order to obtain a larger number of display colors, it is necessary to take the following methods. (1) A method of performing pixel division and performing area gradation by combining sub-pixels. (2) A method of performing pseudo halftone expression by performing digital halftone processing such as “dither method” and “error diffusion method”.

It is necessary to use the above methods individually or in combination.

In the case of a display whose display changes in real time, high-speed processing speed comparable to that for driving sub-pixels and digital halftone processing is required. However, it is necessary to integrate these methods into LSI using advanced semiconductor technology. You can

Up to now, displaying the video signal of the workstation on the high-definition FLCD has been realized by the following procedure. That is, the image / sync signal from the computer is input to first separate the horizontal and vertical sync signals from the sync signal. Next, using the separated horizontal synchronizing signal, the FLCD dot clock synchronized with the workstation dot clock is reproduced,
Output as a sampling clock for A / D conversion.

On the other hand, the synchronously separated image signals are directly input to the A / D converter and digitally converted. Displaying is possible by subjecting the digital data thus obtained to γ characteristic adjustment and halftone processing, and transferring the digital image data to the output control of the FLCD.

[0010]

However, when an image is displayed on the FLCD by the above method, the following problems will occur.

(1) Since the dot clock and the image signal input to the A / D converter pass through different processing systems,
There is a phase time difference between them. for that reason,
The sampling point deviates from the generation point of analog image data by D / A conversion of each pixel value in the host computer machine, and faithful reproduction of digital image data by A / D conversion becomes impossible.
The image on the LCD becomes unclear.

(2) F video signals from a personal computer having a plurality of display modes such as VGA and SVGA
When displayed on the LCD, the horizontal and vertical synchronizing signals and the timing of the dot clock are unique to each machine. Therefore, it is necessary to adjust the phase time corresponding to each display mode.

[0013]

The present invention has been made for the purpose of solving the above-mentioned problems, and has the following structure as one means for achieving the above-mentioned object.

That is, a display control device for inputting a video signal including an image signal and a synchronizing signal to display on a display, a clock for inputting a horizontal synchronizing signal of the synchronizing signal to generate a pixel synchronizing clock signal. Generating means, control means for controlling the clock generating means, and A / A for converting the image signal of the video signal into a corresponding digital signal in synchronization with the pixel synchronization clock generated by the clock generating means.
The clock generating means includes a D converting means, an output means for inputting the synchronizing signal, the pixel synchronizing clock, and the digital signal to output to the display, and the clock generating means includes a delay means for adjusting a delay of the horizontal synchronizing signal. It is characterized by including.

Further, for example, the clock generating means is
Frequency dividing means for dividing the pixel synchronizing clock signal, and locking the phase of the clock signal divided by the dividing means and the horizontal synchronizing signal delayed adjusted by the delay means to lock the pixel synchronizing clock. It is characterized by outputting a signal. The oscillating means is a voltage controlled oscillator, and the frequency dividing means is characterized in that the frequency dividing ratio can be arbitrarily controlled by the control means.

Further, for example, the delay means can control the delay time arbitrarily by the control means, and the A / D conversion means synchronizes the video signal with the pixel synchronization clock. It is characterized by sampling and converting into a corresponding digital signal.

In the above configuration, the sampling clock and the phase of the image data can be adjusted, so that the image on the display becomes clear. Furthermore, by adjusting the phase time corresponding to various display modes, the personal computer can be adjusted. First, it becomes possible to clearly display various image data on the display.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a display controller according to an embodiment of the present invention. The display control device of this embodiment is
It can receive composite video signals such as NTSC, PAL, SECAM, YC (luminance, color difference) separation signals, and analog computer input signals such as PC (personal computer) and WS (workstation).

First, a composite analog image signal of NTSC, PAL, SECAM or the like, which is input through the tuner section 1.21 or directly, is input to the color decoder section 1.
22 performs A / D conversion, color difference demodulation, and matrix conversion into RGB signals. The YC separated image signal is subjected to A / D conversion and RG conversion by the color decoder unit 1.22.
Matrix conversion to B signal is performed.

The RGB field data is converted from 60 Hz field data to 60 Hz frame data in the field / frame conversion section 1.24. The frame data is processed by the horizontal interpolation processing unit 1.25 to FL
Interpolation processing is performed to a horizontal resolution equal to the horizontal resolution of the display device 1.5 which is a CD. However, since the interpolation processing performed here is interpolation processing with double the resolution in the horizontal direction, the same data is read twice.

Next, the voice processing unit 1.7 will be described. The delay adjustment unit 1.71 of the audio processing unit 1.7 is controlled by the system control unit 1.91, and adjusts the deviation between the image display on the display device 1.5 and the sound output from the speaker 1.73. To do.

In the display device 1.5, a slight delay occurs in image display in the upper left and right corners of the display screen depending on the operating temperature of the display device main body. Therefore, when it is necessary to synchronize the moving image with the sound like a TV signal, a temporal disagreement occurs between the image affected by the temperature and the sound not affected by the temperature. In order to eliminate this phenomenon, the temperature information of the display device 1.5 is fed back to the system control unit 1.91, and the delay adjustment unit 1.71 is controlled based on the information to synchronize the image and the sound. Such an audio delay time is generated. That is, when there is no image display delay, no audio delay is generated, and when there is image display delay, an audio delay is generated. However, the audio delay time to be generated is derived by referring to the correlation table of the temperature of the display device 1.5 and the image display delay time which is prepared in advance. By performing this delay adjustment, the image and the sound can be synchronized without depending on the temperature of the display device 1.5.

The audio signal whose delay has been adjusted by the delay adjusting unit 1.71 is sent to the audio processing unit 1.72. The voice processing unit 1.72 is composed of a sound processor, an audio amplifier, and the like. The sound processor performs volume control of audio input, stereo / monaural switching, left / right speaker balance adjustment, tone control, surround processing, and the like under the control of the system control unit 1.91.

The audio signal output from the sound processor is sent to the audio amplifier and is amplified for the speaker 1.73. The amplified audio signal is sent to the speaker 1.73 and is output as audio.

On the other hand, an analog computer image signal of PC, WS, etc. is separated into a horizontal / vertical synchronizing signal and an analog RGB signal in a synchronizing signal separating section 1.01.
The sync signal separation unit 1.01 will be described in detail below.

The sync signal separation unit 1.01 inputs a video signal s1.01 which is an RGB image signal from a computer or the like and a sync signal such as a composite sync, a separate sync or sync on green, and the image signal s.
1.02, a sync signal cs1.01, and a sync signal polarity determination signal cs1.02 are output.

The image signal s1.02 is supplied to the A / D converter 1.
It is output to 03. The sync signal cs1.01 separates the input sync signal, converts it into a negative sync signal, and outputs the sync signal measurement unit 1.02, clock generation unit 1.04, interpolation processing unit 1.05, and system control unit 1. .91 is output. The sync signal polarity determination signal cs1.02 indicates the polarity of the input sync signal s1.01 and is output to the system control unit 1.91.

The horizontal and vertical synchronizing signals separated by the synchronizing signal separating unit 1.01 are input to the synchronizing signal measuring unit 1.02, and the horizontal and vertical frequencies and the horizontal and vertical synchronizing signal polarities are measured. Here, the synchronization signal measuring unit 1.02
The processing performed in step 2 will be described in detail with reference to FIGS.

FIG. 2 is a block diagram showing the detailed structure of the sync signal separation unit 1.01. In FIG. 2, 2.01 is
A clock generator, which is sufficiently higher than the above period for measuring the period of a horizontal synchronizing signal (hereinafter referred to as “HD”) cs2.01 and a vertical synchronizing signal (hereinafter referred to as “VD”) cs2.02. Frequency, clock with a predetermined frequency, cs2.03, and cs
Generates 2.04.

2.02 is a horizontal synchronizing signal HDcs2.0
A counter for measuring the period of 1, which is a horizontal synchronization signal cs
At the falling edge of 2.01, the clock generator 2.0 is reset in one cycle from the reset to the next falling edge.
The clock cs2.03 having a frequency of 1 is counted.
The measurement count value “THD1” c that is the count result
s2.05 is written in FIFO 2.05 described later in synchronization with the rising edge of HDcs2.01.

2.03 is a horizontal synchronizing signal HDcs2.0
A counter for measuring the period of 1, which is a horizontal synchronization signal cs
The clock generator 2.01 is reset at the rising edge of 2.01 and is one cycle from the rising edge to the next rising edge.
The higher frequency clock cs2.03 is counted. The measured count value “THD2” cs which is the count result
2.06 is written in FIFO 2.05 described later in synchronization with the rising edge of HDcs 2.01.

2.04 is a horizontal synchronizing signal HDcs2.0
A counter for measuring the blanking time TH Blank of 1 (the level of the vertical synchronizing signal HD is “0”), which is reset at the falling edge of the horizontal synchronizing signal cs2.01 and continues from there until the next rising edge. .01
The higher frequency clock cs2.03 is counted, and the result is the measured count value "THBlank" cs2.
07 is written in FIFO 2.05 described later in synchronization with the rising edge of HDcs 2.01.

2.05 is a FIFO, THD1c
s2.05, THD2cs 2.06, THBlankc
The data of s2.07 is stored for 1 VD cycle.
This stored data can be read from cs1.19 through the R / W control unit 2.30 described later.

Reference numeral 2.11 is a counter for measuring the number of horizontal synchronizing signals HD in one cycle of the vertical synchronizing signal VD1, which is reset at the rising of the vertical synchronizing signal VDcs2.02 and from there to the next rising. The horizontal synchronization signal is counted as the clock cs2.01 for one cycle, and the result is the measured count value "NHD" cs2.11.
Is written in the register 2.14 described later in synchronization with the rising edge of VDcs2.02.

2.12 is a vertical synchronizing signal VDcs2.0.
2 is a counter for measuring the cycle of the vertical synchronizing signal cs
It is reset at the rising edge of 2.02, and the clock generator 2.0
The clock cs2.04 having a frequency higher than 1 is counted, and as a result, the measured count value "TVD" cs2.12
Are written in the register 2.14 in synchronization with the rising edge of VDcs2.02.

2.13 is a vertical synchronizing signal VDcs2.0.
2 is a counter for measuring the blanking time VBlank (the level of the vertical synchronizing signal VD is “0”), which is reset at the falling edge of the vertical synchronizing signal VDcs2.02 and the clock generator 2. 01
The higher frequency clock cs2.04 is counted, and the measurement count value “TVBlank” cs2.
13 in synchronization with the rising edge of VD and register 2.1.
Write in 4

2.14 is a register, NHDcs
2.11, TVDcs 2.12, TVBlanks
2.13, and VD / HD polarity cs1.02, VDc
The data is stored in synchronization with s2.02, and upon completion of writing of the stored value, the bus cs is passed through the R / W control unit 2.30.
The control signal is output to 1.19.

2.21 is a HD number comparison register,
The number of HDs (horizontal synchronization signals) to be compared is set in the comparison register through cs1.19. 2.22 is a comparator, which outputs 1HD number counter cs2.11
And the comparison register output cs2.21 are compared with each other, and when the comparison result is in agreement, the control signal cs2.22 is activated, and the control signal is output through the R / W control unit 2.30 described later. 2.30 is an R / W controller, which is a FIF
O2.05, register 2.14, HD comparison register 2.
21, comparator output cs2.22 and control bus cs
Control data transfer with 1.19.

The sync signal measuring section 1.02 determines the display mode of the input signal from the measured value.
The system control unit 1.91 determines the display mode of the input signal from this measured value. The system control unit 1.9
Based on the specified display mode, the No. 1 performs desired settings for the clock generation unit 1.04, the vertical interpolation processing unit 1.05, and the OSD (on-screen display) control unit 1.93.

Here, the display mode determination will be described in detail with reference to the flowchart of FIG.

The system control unit 1.91 uses step 100.
At 1, it is checked whether an unlock signal has been received from the clock generator 1.04. Here, when the clock generator 1.04 is outputting the lock signal, the process ends without doing anything.

On the other hand, when the unlock signal is received from the clock generator 1.04 in step 1001, it is determined that the display mode of the input signal is changed or the host computer itself is changed to another signal specification. Then, the process proceeds to step 1002, and the synchronization signal measuring unit 1.02 is newly added.
Receive horizontal and vertical sync signal frequencies from. Then, in step 1003, it is determined whether or not the horizontal synchronizing signal frequency is between the lowest corresponding frequency (H_bottom) and AHz and the vertical synchronizing signal frequency is between the lowest corresponding frequency (V_bottom) and BHz. To do. If so, in step 1004, the system controller 1.91 causes the clock generator 1.04.
Set MODE0 to 0.

Then, in step 1005, the system controller 1.91 receives a lock or unlock signal from the clock generator 1.04. If the lock signal is received here, the process proceeds to step 1006, and it is determined that the display mode of the current input signal is MODE0. Then, the process ends.

On the other hand, if the unlock signal is received in step 1005, it is determined that the display mode of the current input signal is not MODE0, and the step 10 is continued.
From 07 to step 1010, the determination process of MODE1 is performed. Thereafter, the same processing is performed in MODE2, ..., MODE
Do up to M. When the input signal is not specified in MODE 0 to MODE M, it is determined that the current input signal is the non-correspondence signal, and the non-correspondence signal processing is performed in step 1015.

Then, the analog R after this synchronization signal separation
The GB signal s1.02 is converted by the A / D converter 1.03 into
Sampling is performed with a sampling clock so that the horizontal resolution becomes equal to that of the dot matrix display. The sampling clock is obtained by the clock generator 1.04.

The function of the clock generator 1.04 will be described in detail with reference to FIG. FIG. 6 shows the detailed configuration of the clock generator 1.04 shown in FIG. 1 described above. The clock generator 1.04 of this embodiment includes a phase comparator 3.05 and a charge pump type low-pass filter 3. .06
~ 3.08, VCO (Voltage-controlled Oscillato
r) P based on 3.10 and 3.04 division period
It has a configuration of an LL (Phase Locked Loop) clock generator.

3.17 is a clock generator 1.0
Interface control unit with the data bus cs1.19 connected to the system control unit 1.91 to control the clock generation module 3.
It is a register group for controlling 01 to 3.16.

The horizontal synchronizing signal of the video is transmitted through the signal lines cs1.
01 to the i / F level selection unit 3.01. i /
In the F level selection unit 3.01, the synchronization signal separation unit 1.01
The i / F signal interface is switched according to the control signal cs3.01 defined by the control register 3.17 in order to correspond to the signal interface output from, for example, TTL or PECL.

The polarity reversing unit 3.02 is provided to enable phase comparison at both the rising and falling edges of the horizontal synchronizing signal when performing phase comparison, and it corresponds to the polarity switching control line cs3.02. Switch the polarity.

Delay line (DERAY LINE)
In 3.03, the horizontal synchronizing signal cs3.01 and the dot clock signal s3.03 are input, and the horizontal synchronizing signal cs3.01 is input.
In contrast, the delay control of one dot clock cycle or more is performed in a programmable manner, and the delay control line cs3.03
Adjust the delay time accordingly. The video signal input at s1.01 is separated into a sync signal and an image signal by the sync signal separation unit 1.01.

Since they are input to different processing systems, the image data s input to the A / D converter 1.03 is input.
1.02 and A / generated by the clock generator 1.04
A phase difference occurs in the D conversion sampling clock cs1.03. So this delay line (DELAY
LINE) 3.03 adjusts the phases of the image data s1.02 and the sampling clock cs1.03. The delay-adjusted horizontal synchronization signal is output to the signal line s3.02 as the reference horizontal synchronization signal.

The frequency divider 3.04 has a dot clock signal s3.0 output from the programmable counter 3.12.
3 is divided by the frequency division value set in the register 3.17 by the system control unit 1.91. The frequency divider control line cs
A dividing value is set in the counter of the divider by 3.04.

FIG. 7 shows the detailed structure of the counter section of the frequency divider 3.04. As shown in FIG. 7, the division control line cs3.04 is composed of CLOCK, DATA, and LATCH signals, and DATA is serially transferred to the shift register 3.20 in synchronization with the CLOCK signal. And D
After the ATA transfer is completed, the data of the shift register 3.20 is transferred by the LATCH signal to the register 3.
21.

The circuit 3.23 in FIG. 7 is a circuit for determining that the value of the main divider 3.22 becomes 0, and when it becomes 0, the LOAD signal CS3.20 is sent to the main divider 3.2.
22. Main divider 3.22 is LOAD
Upon receiving the signal CS3.20, the data in the register 3.21 is transferred to the main divider 3.22.

The phase comparator 3.05 inputs the delay-adjusted reference horizontal synchronizing signal s3.02 and the output signal s3.04 from the division period 3.04, and compares the phases of these signals. , Generates a voltage or pulse signal according to the phase difference. Phase comparison enable control signal cs3.05
Indicates that the phase comparator 3.05 has the reference horizontal synchronization signal s3.02.
Is a signal for controlling whether or not to perform a phase comparison of the output signal s3.04 from the frequency divider 3.04.

The charge pump type low pass filter is composed of a charge pump 3.06 and a low pass filter 3.07 or 3.08 defined by the low pass filter switching control signal cs3.06. This is a phase comparator 3.05
High-frequency components and noise are removed from the output voltage from the VCO, and a DC voltage is supplied to the VCO 3.10. The phase comparison detection gain of the PLL can be adjusted by changing the charge pump current as follows. It is something.

That is, the digital value of the register 3.17 set by the system control unit 1.91 is sent to the D / A converter 3.09 via the gain control signal cs3.07,
The charge pump current is controlled by converting and supplying the current corresponding to the value. Also, the response characteristic of the PLL is a filter constant of 3.0 which is composed of a resistor and a capacitor.
7 or 3.08. Therefore, the damping factor of the PLL in this embodiment can be changed by adjusting the phase comparison detection gain and the filter constant.

The VCO 3.10 generates a signal having a frequency obtained by multiplying the reference horizontal synchronizing signal S3.02 according to the output signals from the D / A converter 3.11 and the charge pump 3.06 by the following method. That is, the digital value of the register 3.17 set by the system control unit 1.91 is sent to the D / A converter 3.11 via the oscillation frequency control signal cs3.08, and the D / A converter 3.11 corresponds to the value. Supply current to VCO 3.10.

Further, in the VCO 3.10, the oscillation frequency during free run is determined by the output current of the D / A converter 3.11. This allows the VCO 3.10 to oscillate in a frequency range centered on its free-run frequency. On the other hand, in the frequency range, a signal corresponding to the difference between the free-run frequency and the oscillation frequency set in the frequency divider 3.04 is output from the charge pump 3.06, and this output signal causes the output signal of the VCO 3.10. The oscillation frequency of is controlled.

The programmable counter 3.12 has a VC
The system control unit 1.91 divides the output signal of O3.10 by the division value set in the register 3.17, and the division value is set in the counter by the programmable counter control line cs3.09. . This counter 3.1
The presence of 2 makes it possible to obtain a low-frequency signal output that is lower than the variable frequency range of the VCO 3.10, and as a result the variable frequency range can be expanded. Conversely, VCO
Since the variable frequency range of 3.10 can be narrowed, VCO
The stability of the oscillation frequency of 3.10 is improved. The output signal of the programmable counter 3.12 is used as a dot clock s3.03 by the frequency divider 3.04 and DELAY.
Input to LINE 3.03 and 3.13.

The DELAY LINE 3.13 adjusts the phase of the dot clock s3.03 and the reference horizontal synchronizing signal s3.02 for the following reasons. That is, the PLL, which is the basic configuration of the clock generation unit 1.04, includes a reference horizontal synchronization signal s3.02 and a frequency divider output signal s3.04.
The phase difference is locked, but the phase difference is not adjusted.

Therefore, since there is a phase difference between the reference horizontal synchronizing signal s3.02 and the dot clock s3.03,
DELAY LINE 3.13 is a delay control line cs3.
By adjusting the delay time according to 10, the phase difference between those signals is adjusted. A more detailed description will be given in the functional description of the 1/2 frequency division output level switching unit 3.15.

The output level switching units 3.14 to 3.16 are
The output level is converted according to the signal interface level of the connection destination such as TTL, ECL, and PECL and the output signal frequency.
The level is switched according to s3.13. The output level switching unit 3.14 inputs the dot clock s3.03 from the DELAY LINE 3.13 and converts it to the ECL level, and the complementary signal cs1.03 is A / D.
Output to converter 1.03. The 1/2 frequency-divided output level switching 3.15 inputs the dot clock s3.03 from the DELAY LINE 3.13 and the reference horizontal synchronizing signal s3.02 as a reset signal, and converts the level into ECL and TTL. Output the divided signal.

FIG. 8 shows a 1/2 frequency division output level switching section 3.1.
5 shows an operation timing chart of No. 5. Reset signal s
The Low state of 3.02 is detected at the rising edge b of the clock s3.03, and the signals cs1.04 and cs1.06 are detected.
Is set to the reset state for the period of 4 cycles of the clock s3.03. At this time, in order to reliably latch the Low state at the rising edge b, it is necessary to satisfy the setup time for b. So DELAY LINE
3.13 adjusts the phase of the reset signal s3.02 and the dot clock s3.03 to satisfy the setup time.

After that, the signals cs1.04 and cs1.06 are activated at the rising edge d of the clock s3.03. ECL complementary signal cs1.04
Is output as a demultiplexer signal for A / D conversion 1.03, and the TTL single-ended signal cs1.06 is
It is output as the master clock of the interpolation processing 1.05. The output level switch 3.16 is the reference horizontal synchronization signal s.
3.02 is input, converted to a TTL level, and the single end output signal cs1.05 is output to the interpolation processing 1.05.

Then, the RGB signal s1.0 after A / D conversion
3 is interpolated by the interpolation processing unit 1.05 to a resolution that matches the vertical resolution of the display unit 1.5.

Interpolation processing performed by the interpolation processing unit 1.05 will be described in detail with reference to FIGS. 9, 10 and 11.

As the interpolation processing method, the most commonly used methods are the nearest neighbor interpolation method and the linear interpolation method (1
Next-order interpolation method), third-order convolutional interpolation method, and the like. The nearest neighbor interpolation method is a method in which a pixel before interpolation closest to a pixel to be interpolated is used as an interpolation pixel. The linear interpolation method is a method of obtaining pixel data of a pixel to be interpolated using pixel data of pixels on both sides of a pixel to be interpolated.

For example, as shown in FIG. 9, when the pixel b is interpolated at the positions (between the pixels a1 and a2) at the distances u and v from the pixels a1 and a2 arranged at the distance interval 1, The pixel data of b is calculated by the following equation (1).

[0071]

(Equation 1)

B = a1 * v / (u + v) + a2 * u / (u + v) (1) On the other hand, the cubic convolutional interpolation method uses pixel data of two pixels on each side of the pixel to be interpolated and cubic data. This is a method of obtaining pixel data of pixels to be interpolated using a convolution function. The cubic convolution function f is given by the equation (2), where t is the distance between the pixel to be interpolated and two pixels on both sides arranged at the distance interval 1.

[0073]

(Equation 2)

F (t) = sin (πt) / (πt) (2) Formula (2) is defined by formulas (3), (4), and (5) depending on the range of t.
It is deployed like.

[0075]

[Equation 3]

F (t) = 1-2 * | t | ^ 2 + | t | ^ 3 (0 ≦ | t | <1) (3) f (t) = 4-8 * | t | + 5 * | t | ^ 2- | t | ^ 3 (1≤ | t | <2) (4) f (t) = 0 (2≤ | t |) (5) where A ^ 2 is A * A Indicates. For example, as shown in FIG. 10, pixels a1, a2, a arranged at a distance of 1 are arranged.
When the pixel b is interpolated at positions (between the pixels a2 and a3) located at the distances of 3, a4 to u1, u2, u3, u4, the pixel data of the pixel b is calculated by using the cubic convolution function f. It is calculated by the equation (6).

[0077]

(Equation 4)

B = a1 * (4-8 * u1 + 5 * u1 ^ 2-u1 ^ 3) + a2 * (1-2 * u2 ^ 2 + u2 ^ 3) + a3 * (1-2 * u3 ^ 2 + u3 ^ 3) + A4 * (4-8 * u4 + 5 * u4 ^ 2-u4 ^ 3) (6) Here, using Equations (1) and (6), for example, from 768 pixels to 960 pixels, a linear interpolation method (1 For the case of performing the interpolation processing by the second interpolation method) and the cubic convolution interpolation method,
This will be described with reference to FIG. In the case of this example, the interpolation data of 8 pixels is created from the data before interpolation of 5 pixels. Therefore, the pixel data bn after the linear interpolation and the pixel data bn after the interpolation by the cubic convolution interpolation method are given by the equations (7) and (8) using the pixel data an before the interpolation, respectively.

[0079]

(Equation 5)

B (5n + 1) = a (4n) +1 (n = 0,1,2 ...) b (5n + 2) (4/5) * a (4n) + (1/5) * a (4n) +2 b (5n + 3) = (3/5) * a (4n + 2) + (2/5) * a (4n) +3 b (5n + 4) = (2/5) * a (4n + 3) + (3/5) * a ( 4 (n + 1)) b (5n + 5) = (1/5) * a (4 (n + 1)) + (4/5) * a (4 (n + 1) +1) (7) b (5n + 1) = a4n + 1 ( n = 0,1,2 ...) b (5n + 2) = (-4/125) * a (4n) + (29/125) * a (4n + 1) + (116/125) * a (4n + 2) + (- 16/125) * a (4n + 3) b (5n + 3) = (-12/125) * a (4n + 1) + (62/125) * a (4n + 2) + (93/125) * a (4n + 3) + (- 18/125) * a (4 (n + 1)) b (5n + 4) = (-18/125) * a (4n + 2) + (93/125) * a (4n + 3) + (62/125) * a (4 (n + 1)) + (-12/125) * a (4 (n + 1)) + 1 b (5 (n + 1)) = (- 16/125) * a (4n + 3) + (116/125) * a (4 (n + 1)) + (29/125) * a (4 (n + 1) +1) + (-4/125) * a (4 ( n + 1)) +2 (8) However, if the interpolation processing by the linear interpolation method or the cubic convolutional interpolation method is configured by hardware (ASIC) using the equations (7) and (8), it becomes complicated. It requires an arithmetic operation of fractions, resulting in an unrealistic scale.

In view of the above problems, in the display control device according to the present invention, in order to realize the interpolation processing by the linear interpolation method or the cubic convolution interpolation method with the small-scale hardware (ASIC), the equation (7) ) And equation (8) are approximated by the sum of the exponents of 2. The approximation results of equations (7) and (8) are shown in equations (9) and (10), respectively.

[0082]

(Equation 6)

B (5n + 1) = a (4n + 1) (n = 0,1,2 ...) b (5n + 2) = (1/2 + 1/4) * a (4n + 1) + (1/4) * a (4n + 2) ) b (5n + 3) = (1/2 + 1/8) * a (4n + 2) + (1/4 + 1/8) * a (4n + 3) b (5n + 4) = (1/4 + 1/8) * a (4n + 3) + (1/2 + 1/8) * a (4 (n + 1)) b (5n + 5) = (1/4) * a (4 (n + 1)) + (1/2 + 1/4) * a (4 (n + 1) +1) (9) b (5n + 1) = a (4n + 1) (n = 0,1,2 ...) b (5n + 2) = (-1/16) * a (4n) + (1/4) * a (4n + 1) + (1/2 + 1/4 + 1/8 + 1/16) * a (4n + 2) + (-1/8) * a (4n + 3) b (5n + 2) = (-1/8) * a (4n + 1) + (1 / 2) * a (4n + 2) + (1/2 + 1/4) * a (4n + 3) + (-1/8) * a (4 (n + 1)) b (5n + 3) = (-1/8) * a (4n + 1) ) + (1/2) * A (4n + 2) + (1/2 + 1/4) * a (4n + 3) + (-1/8) * a (4 (n + 1)) b (5n + 4) = (-1/8) * a (4n + 2) + (1/2 + 1/4) * a (4n + 3) + (1/2) * a (4 (n + 1)) + (-1/8) * a (4 (n + 1)) + 1 b (5 (n + 1)) = (-1/8) * a (4n + 3) + (1/2 + 1/4 + 1/8 + 1/16) * a (4 (n + 1)) + (1/4) * a (4 (n + 1) +1) + (-1 / 16) * a (4 (n + 1) +2) (10) The approximation from equation (7) to equation (9) should be such that the number of coefficient terms is as small as possible and the maximum approximation error is within 1/20. went. Further, the approximation from the equation (8) to the equation (10) is also performed so that the number of coefficient terms is as small as possible and the maximum approximation error is within 1/32. If it is desired to reduce the deterioration of the image quality due to the interpolation processing, the maximum approximation error is further reduced by adding a term smaller than 1/64. On the contrary, when it is desired to make the hardware (ASIC) smaller, the approximation error is increased by applying a small term such as 1/64 or 1/32, but the hardware (ASIC) is increased.
IC) scale can be reduced.

Similarly, the approximation result when storing from 480 pixels to 960 pixels is expressed by equation (11) for linear interpolation and equation (1) for cubic convolution interpolation.
See 2).

[0085]

(Equation 7)

B (2n + 1) = a (n + 1) (n = 0,1,2 ...) b (2 (n + 1)) = (1/2) * a (n + 1) + (1/2) * a (n + 2) ) (11) b (2n + 1) = an + 1 (n = 0,1,2 ...) b (2 (n + 1)) = (-1/8) * a (n) + (1/2 + 1/8) * a (n + 1) + (1/2 + 1/8) * a (n + 2) + (-1/8) * a (n + 3) (12) Further, in the same manner, approximation when storing from 600 pixels to 960 pixels The result is expressed by equation (1
3) The cubic convolutional interpolation is shown in Expression (14).

[0087]

(Equation 8)

B (8n + 1) = a (5n + 1) (n = 0,1,2 ...) b (8n + 2) = (1/2 + 1/8) * a (5n + 1) + (1/4 + 1/8) * a ( 5n + 2) b (8n + 3) = (1/4) * a (5n + 2) + (1/2 + 1/4) * a (5n + 3) b (8n + 4) = (1/2 + 1/4 + 1/8) * a (5n + 2) ) + (1/8) * a (5 n + 3) b (8n + 5) = (1/2) * a (5n + 3) + (1/2) * a (5n + 4) b (8n + 6) = (1/8) * a (5n + 4) + (1/2 + 1/4 + 1/8) * a (5 (n + 1)) b (8n + 7) = (1/2 + 1/4) * a (5n + 4) + (1/4) * a (5 ( n + 1)) b (8 (n + 1)) = (1/4 + 1/8) * a (5 (n + 1)) + (1/2 + 1/8) * a (5 (n + 1)) + 1 (13) b ( 8n + 1) = a (5n + 1) (n = 0,1,2 ...) b (8n + 2) = (-1/16 + -1 / 32) * a (5n) + (1 / 4 + 1/8 + 1/16 + 1/32) * a (5n + 1) + (1/2 + 1/4) * a (5n + 2) (-1/8) * a (5n + 3) b (8n + 3) = (-1/8) * a (5n + 1) + (1/2 + 1/4 + 1/8) * a (5n + 2) + (1/4 + 1/32) * a (5n + 3) (-1/32) * a (5n + 4) b (8n + 4) = (-1 / 64) * a (5n + 1) + (1/8 + 1/64) * a (5n + 2) + (1/2 + 1/4 + 1/8 + 1/16/16/32) * a (5n + 3) + (-1 / 16 + -1 / 32 ) * A (5n + 4) b (8n + 5) = (-1/8) * a (5n + 2) + (1/2 + 1/8) * a (5n + 3) (1/2 + 1/8) * a (5n + 4) + (- 1/8) * a (5 (n + 1)) b (8n + 6) = (-1/16 + -1 / 32) * a (5n + 3) + (1/2 + 1/4 + 1/8 + 1/16 + 1/32) * a (5n + 4 ) + (1/8 + 1/64) * a (5 (n + 1)) + (-1/64) * a (5 (n + 1)) + 1 b (8n + 7) = (-1/32) * a (5n + 3) + (1/4 + 1/32) * a (5n + 4) + (1/2 + 1/4 + 1 / 8) * a (5 (n + 1)) + (-1/8) * a (5 (n + 1)) + 1 b (8 (n + 1)) = (-1/8) * a (5n + 4) + (1/2 + 1 / 4) * a (5 (n + 1)) + (1/4 + 1/8 + 1/16/16/1/32) * a (5 (n + 1) +1) + (-1 / 16 + -1 / 32) * a (5 (n + 1) +2) (14) Next, the detailed configuration of the interpolation processing unit 1.05 will be described in detail with reference to FIG. FIG. 12 is a detailed block diagram of a vertical interpolation device that vertically interpolates the input effective display image data and enlarges and displays it on the dot matrix display.

In FIG. 12, 4.01 is an input unit for inputting the digital image data output from the AD converter, and 4.02 is a control input unit for controlling the vertical interpolation device from the system control unit 1.91. 4.02.01 is
A memory device for storing the setting data set by the system control unit 1.91, 4.02.02 is a setting supply device for supplying the stored setting data to another processing device.

Further, 4.03 is a synchronization input section for inputting a clock and a synchronization signal, 4.04 is an output section for outputting image data and a synchronization signal to the digital processing section, and 4.05 is an output for the image data. The output clock supply unit for determining the transfer rate for outputting 0.4.0 is a vertical interpolation processing unit for performing digital processing using the input image data to increase horizontal lines, and 4.07 is a vertical interpolation processing unit. This is an interpolation control unit that performs control of 06.

In the above structure, the interpolation control section operates as follows. The input section 4.01 is the A / D conversion section 1.0.
The image data output from No. 3 and input via the data signal line S1.03 is synchronized with each signal input to the synchronization input unit 4.03, and is passed to the vertical interpolation processing unit 4.06. The clock supplied from the output clock supply unit 4.05, which is stored in the memory device 4.02.01 of the control input unit 4.02, is processed based on the setting data supplied by the setting supply unit 4.02.02. Output section in synchronization with 4.
Image data is sent from 04 to the switch unit 1.06.

When the vertical interpolation process is not performed, the clock supplied from the synchronization input unit 4.03 is used to output the image data from the output unit 4.04 to the switch unit 1.06. It operates as described above.

FIG. 13 is a diagram showing a detailed configuration of the vertical interpolation processing unit 4.06 and the interpolation control unit 4.07 shown in FIG.

In FIG. 13, reference numeral 4.06.01 is a flip-flop (F / F) circuit for synchronizing the image data and the synchronizing signal, and 4.06.02 is an input Fast for storing one horizontal line. In Fast Out (FIFO) memory,
Reference numeral 4.06.03 denotes an arithmetic unit for performing arithmetic processing with the image data input by the interpolation coefficient, and 4.06.04 denotes an output Fast In for storing the image data after performing the interpolation operation.
Fast Out (FIFO) memory, 4.06.05 is an output FIFO for selecting the output of the output FIFO memory 4.06.04 and transferring it to the switch unit 4.06.06 described later.
A switch unit for selecting the output of the memory.

Further, 4.06.06 is a switch unit for selecting a through path when there is one interpolation coefficient, that is, when no interpolation is performed, and 4.07.01 is an input timing of the image data and an input FIFO memory 4. An input FIFO control unit for controlling data write timing and read timing to 06.02, 4.07.02 is an output FIFO write control unit for controlling timing of the arithmetic unit and write timing of the output FIFO memory 4.06.02. Is.

Further, 4.07.03 is an output FIFO control unit for controlling the read timing of the output FIFO memory 4.06.04, 4.07.04 is a display position detecting unit for detecting the display start position, and 4. 07.05 is an output display position correction device for adjusting the timing of the image data and the synchronizing signal output from the vertical interpolation processing unit 4.06, and 4.07.0.
Reference numeral 6 is an arithmetic control unit that controls the index for each nuclear line.

In the above structure, the input image data is input to the F / F circuit 4.06.01 in the input FIFO.
Image data is transferred to the input FIFO memory 4.06.02 after being synchronized with the signal from the control unit 4.07.01. Each input FIFO memory 4.06.02 is controlled by the input FIFO control unit 4.07.01 so that the image data delayed by one horizontal line is sequentially transferred.

The calculation unit 4.06.03 is a calculation control unit 4.3.0.
The image data of the same horizontal column is input to the operation unit 4.06.03 by the control signal from 07.06, the vertical interpolation line is generated, and the output FIFO memory 4.06.0 is output.
4 is stored under the control of the output FIFO control unit 4.07.03. The stored image data is read by a signal from the output FIFO control unit 4.07.03, and is output to the switch unit 1.06 via the switch unit 4.06.05 and the switch unit 4.06.06. Transfer data.
A signal synchronized with the image data at the time of transfer is generated by the output display position correction device 4.07.05.

FIG. 14 is a diagram showing an internal block configuration of the arithmetic unit 4.06.03 for the input image data shown in FIG.

In FIG. 14, the exponent calculation unit 4.06.0.
3.01 is an F / F circuit 4.06.01 or an input FIF
The image data of each line is received from the O memory 4.06.02, multiplied by a predetermined index, and the image data is transferred to a 4-input adder 4.06.03.02 to perform addition. The image data of the addition result is processed by the code processing device 4.
If the feed calculation result is negative at 06.03.03, change it to the minimum value "00" (6 bits, hexadecimal), and if it exceeds the maximum value, maximum value "3F" (6 bits, 1
Hexadecimal number).

FIG. 15 shows the exponent calculation unit 4.06.03.0.
It is a detailed block diagram of 1.

In the figure, the exponential calculation unit 4.06.0.
3.01 shows the input image data from 1/32 to 32.
A value of up to / 32 is created, and the two's complement arithmetic unit converts the image data of the preceding stage into a negative number. The selector selects the image data and the image data that does not pass through the two complement calculator, and
The image data is transferred to the input adder 4.06.03.02.

Hereinafter, a schematic operation for performing vertical interpolation processing in various display modes using a known graphic card will be described.

FIG. 16 is a diagram for explaining a display mode of a VGA, which is a well-known general-purpose IBM graphic card. Hereinafter, a schematic operation for performing vertical interpolation processing in the case of horizontal 640 dots and vertical 350 lines in the VGA display mode will be described with reference to FIG.

In this case, the input image signal is obtained by sampling 640 horizontal dots twice per dot,
The dots are enlarged. Further, the vertical 350 lines are increased to 490 lines by the vertical interpolation processing of the interpolation processing unit 1.05, and further expanded by 2 lines in the dot matrix display 1.5 to be increased to vertical 980 lines with an approximate aspect ratio. .

As a result, in the dot matrix display 1.5, the display is performed in the effective display area of 1280 horizontal dots and 980 vertical lines.

In the interpolation process, image data is input at the timing shown in the figure. In this example, the time for one horizontal line is 31.778 μS, of which 25.422 μS.
S contains valid image data. Also, in the case of this vertical interpolation processing, 7 lines of output must be created for the input line 5.

Therefore, the equation of the input cycle period / output cycle period in the figure is obtained, and the output cycle is 22.69.
It is determined to be 9 μS. Furthermore, the output cycle of the output is determined from the relationship of the valid data period. In the case of this example, 3
Determined from 9.16 MHz to 28.196 MHz. Regarding the relationship between the input timing and the output timing, it is necessary to start output after two lines are input and output seven lines while five lines are input. Next, the relationship between the input line and the output FIFO memory 4.06.04 is described. When the line with the cycle number of the input line on the left is input, the cycle line number shown in the figure is written in each output FIFO memory. The control is performed so that the line of is input.

FIG. 17 is a schematic operation explanation for performing vertical interpolation processing in the case of 800 dots in the horizontal direction and 600 lines in the vertical direction of the VESA standard. In this case, in the input image signal, the effective display period of horizontal 800 dots is sampled at 1280 and enlarged to 1280 dots, and the vertical 600 lines are increased to vertical 960 lines with an approximate aspect ratio by the vertical interpolation processing of the interpolation processing unit 1.05. To do. As a result, in the dot matrix display 1.5, the horizontal 12
Display is performed in an effective display area of 80 dots and 960 vertical lines.

In the interpolation process, image data is input at the timing shown in the figure. In this example, the time for one horizontal line is 28.444 μS, of which 22.222 μS.
S contains valid image data. Also, in the case of this vertical interpolation processing, eight lines of output must be created for the input line 5. Therefore, the formula shown in the figure is obtained and the output cycle is determined to be 17.778 μS. Furthermore, the output cycle of the output is determined from the relationship of the valid data period. In this example, 55.385 MHz to 3
Determined to 6.000 MHz. Regarding the relationship between the input timing and the output timing, it is necessary to start output after two lines are input and output eight lines while five lines are input. Next, input line and output FIFO memory 4.0
The relationship of 6.04 is described, and when the line with the cycle number of the input line on the left is input, each output FIFO
The control is performed so that the lines having the cycle line numbers shown in the figure are input into the memory.

FIG. 18 is a schematic operation explanation for performing vertical interpolation processing in the case of 800 dots in the horizontal direction and 600 lines in the vertical direction of the VESA (60 Hz) standard. In this case, the input image signal has an effective display period of 1280 horizontal for 1280
It is sampled with, enlarged to 1280 dots, and vertically 60
The vertical interpolation process of the interpolation processing unit 1.05 increases the number of lines from 0 line to 960 vertical lines having an approximate aspect ratio. As a result, in the dot matrix display 1.5, the display is performed in the effective display area of 1280 horizontal dots and 960 vertical lines.

In the interpolation processing, the image data is input at the timing shown in the figure. In the case of this example, the time for one horizontal line is 26.400 μS, of which 20.000 μS.
S contains valid image data. Also, in the case of this horizontal interpolation processing, eight lines of output must be created for the input line 5. Therefore, it becomes as shown in the figure and the output cycle is determined to be 16.500 μS. Furthermore, the output cycle of the output is determined from the relationship of the valid data period. In the case of this example, it is determined from 63.3663 MHz to 38.7878 MHz.

Regarding the relationship between the input timing and the output timing, it is necessary to output 8 lines after inputting 2 lines and starting output for 5 lines.

Next, the relationship between the input line and the output FIFO memory 4.06.04 is described. When the line with the cycle number of the input line on the left is input, each output F
Control is performed so that the line having the cycle line number shown in the drawing is input into the IFO memory.

FIG. 19 is a schematic operation diagram for performing vertical interpolation processing in the case of 800 dots in the horizontal direction and 600 lines in the vertical direction of the VESA (72 Hz) standard. In this case, the input image signal has an effective display period of 1280 horizontal for 1280
It is sampled with, enlarged to 1280 dots, and vertically 60
The vertical interpolation process of the interpolation processing unit 1.05 increases the number of lines from 0 line to 960 vertical lines having an approximate aspect ratio. As a result, in the dot matrix display 1.5, the display is performed in the effective display area of 1280 horizontal dots and 960 vertical lines.

In the interpolation processing, the image data is input at the timing shown in the figure. In the case of this example, the time for one horizontal line is 20.800 μS, of which 16.000 μS
S contains valid image data. Also, in the case of this vertical interpolation processing, eight outputs must be created for the input line 5. Therefore, the equation in the figure is used and the output cycle is determined to be 13.000 μS. Furthermore, the output cycle of the output is determined from the relationship of the valid data period. In this example, from 78.048 MHz to 4
It is determined to 9.231 MHz.

Regarding the relationship between the input timing and the output timing, it is necessary to start the output after inputting 2 lines and output for 8 lines while inputting 5 lines.

Next, the relationship between the input line and the output FIFO memory 4.06.04 is described. When the line with the cycle number of the input line on the left is input, each output F
The control is performed so that the line having the cycle line number shown in the figure is input into the IFO memory.

FIG. 20 is a schematic operation diagram for performing vertical interpolation processing in the case of 1024 horizontal dots and 768 vertical lines in the VESA standard. In this case, the input image signal is
The effective display period of 1024 dots in the horizontal direction is sampled at 1280, expanded to 1280 dots, and increased from 768 lines in the vertical direction to 960 lines in the vertical direction having an approximate aspect ratio by the vertical interpolation processing of the interpolation processing unit 1.05. As a result, in the dot matrix display 1.5, the horizontal 1
Display is performed in an effective display area of 280 dots and 960 vertical lines.

In the interpolation processing, the image data is input at the timing shown in the figure. In the case of this example, the time for one horizontal line is 17.707 μS, of which 13.65 μS.
Valid image data is included in 3 μS. In the case of this vertical interpolation processing, the output is 5 for the input line 4.
The line must be created. Therefore, the equation in the figure is used and the output cycle is determined to be 14.165 μS. Furthermore, the output cycle of the output is determined from the relationship of the valid data period. In this example, 63.2 MHz to 4
Determined to 5.2MHz.

Regarding the relationship between the input timing and the output timing, it is necessary to start the output after inputting 2 lines and output for 5 lines while inputting 4 lines.

Next, the relationship between the input line and the output FIFO memory 4.06.04 is described. When the line with the cycle number of the input line on the left is input, each output F
The control is performed so that the line of the cycle line number shown in the figure is input into the IFO memory.

FIG. 21 is a horizontal view of one mode of Macintosh series (MAC) of Apple Computer Inc.
It is a schematic operation description for performing vertical interpolation processing in the case of 24 dots and 768 vertical lines. In this case, the input image signal is sampled at 1280 dots in the effective display period of 1024 horizontal dots and expanded to 1280 dots, and the vertical 768
The number of lines is increased to 960 vertical lines having an approximate aspect ratio by the vertical interpolation processing of the interpolation processing unit 1.05.
As a result, in the dot matrix display 1.5,
Display is performed in an effective display area of horizontal 1280 dots and vertical 960 lines.

In the interpolation process, image data is input at the timing shown in the figure. In the case of this example, the time for one horizontal line is 16.6 μS, of which 12.8 μS contains valid image data. Also, in the case of this vertical interpolation processing, five outputs must be created for the input line 4. Therefore, the formula shown in the figure is obtained and the output cycle is determined to be 13.28 μS. Furthermore, the output cycle of the output is determined from the relationship of the valid data period. In the case of this example, 67.5 MHz to 48.2 MH
It depends on z. Regarding the relationship between the input timing and the output timing, it is necessary to start output after two lines are input and output five lines while four lines are input. next,
The relationship between the input line and the output FIFO memory 4.06.04 is described, and when the line with the cycle number of the input line on the left is input, the line with the cycle line number shown in the figure is input into each output FIFO memory. Control is performed so that it is input.

Next, the key input processing from the operator will be described in detail with reference to the flowchart of FIG. 22 and FIG. 23 showing an example of keys for receiving key input from the user.

When a key input is made, system control unit 1.91 performs a key scan on key matrix unit 1.92 in step 1101 shown in FIG. In step 1102, it is determined whether there is a key input as a result of the key scan. If there is no key input, the key input processing is immediately terminated.

On the other hand, if there is a key input from step 1102, the process proceeds to step 1103. Step 1103
Then, it is determined whether or not the detected key input is the TV / PC switching key (KEY1) shown in FIG. If it is the TV / PC switching key, the process proceeds to step 1104 to perform the TV / PC mode switching process.

The TV / PC switching process is as follows: 1. Switching control of the switch unit 1.3. 2. Setting of TV / PC switching information to the interpolation processing unit 1.05. OSD display of TV / PC switching information.

After the TV / PC switching process is completed, the key input process is completed.

On the other hand, if it is not the TV / PC switching key (KEY1) in step 1103, step 11
In step 05, it is determined whether the detected key input is the volume UP key (KEY2) in FIG. If it is the volume UP key, the volume UP process of step 1106 is performed. The volume UP process is as follows: Volume UP setting to the audio processing unit 1.72, 2. OSD display of update volume. After the voice UP process is completed, the key input process is completed.

On the other hand, if the key input detected in step 1105 is not the volume UP key, the flow proceeds to step 1107, and the detected key input is the volume DOWN shown in FIG.
It is determined whether or not it is the key (KEY3). If it is the volume down key, the volume down process of step 1108 is performed. The volume DOWN processing is as follows: Volume DOWN setting to the audio processing unit 1.72; OSD display of update volume. The voice DOWN
After the processing ends, the key input processing ends.

On the other hand, if the key input detected in step 1107 is not the volume down key, step 110
In step 9, it is determined whether the clear key and the set key shown in FIG. 23 have been simultaneously pressed continuously for a certain period or longer. If so, it is determined that the reset key (KEY9) has been detected, and the reset process of step 1110 is performed. The reset process is as follows: 1. Read the factory default settings from the nonvolatile memory unit 1.94 and set them in the decoder unit 1.22. 2. Read the factory default settings from the non-volatile memory 1.94 and set them in the audio processor 1.72. 3. Read the factory default settings from the non-volatile memory unit 1.94 and set them in the clock generator 1.04. The initial setting values at the time of factory shipment are read from the nonvolatile memory unit 1.94 and set in the interpolation processing unit 1.05. After the reset process ends, the key input process ends.

On the other hand, if the reset key is not detected in step 1109, the flow advances to step 1111 to detect the detected key input. The menu key (KEY) shown in FIG.
4) is determined. If it is the menu key, the process proceeds to step 1112. Otherwise,
Keys other than the above, that is, the set key (KEY5), UP
When any one of the key (KEY6), the DOWN key (KEY7), and the clear key (KEY8) is detected, the key input process is immediately terminated without doing anything.

At step 1112, it is determined whether the present TV mode or the PC mode is selected. Then, in the TV mode, the process proceeds to step 1113, and in the PC mode, the process proceeds to step 1128.

In both step 1113 and step 1128, menu selection processing is performed in which the operator selects a setting item while looking at the menu screen. This step 11
Details of the menu selection processing in step S13 and step 1128 will be described below with reference to the flowchart in FIG.

First, in step 1501, OSD display is performed with the previously selected item selected. This OSD
The display will be described later. Subsequently, in step 1502, wait is performed until there is a key input process from the operator.
If there is a key input, step 1502 to step 150
In step 3, it is determined whether the key input by the operator is the TV / PC switching key, the volume UP key, or the volume DonW key. If these keys are used, the process returns to step 1502 again without doing anything.

On the other hand, if these keys are not found in step 1503, the process proceeds to step 1504, and it is determined whether the key entered by the operator is the menu key. If so, the process ends.

On the other hand, if the key entered by the operator in step 1504 is not the menu key, step 1505
Proceed to. In step 1505, it is determined whether the key input by the operator is the setting key. If so, the setting item is decided and step 1114 or 112 is set.
Proceed to 9.

In step 1506, it is determined whether the key input by the operator is the clear key. If the key entered by the operator is the clear key, step 150
7, the selection item is set to the initial value, and the process returns to step 1501.

On the other hand, if the key input by the operator in step 1506 is not the clear key, the flow advances to step 1508. In step 1508, it is determined whether or not the operator has pressed the clear key and the set key at the same time for a predetermined time or longer. Then, if the operator keeps pressing the clear key and the set key at the same time for a certain period of time or more, it is determined that the reset request has been issued, and the process proceeds to step 1509 to perform the reset process, and the process is finished.

On the other hand, if it is determined in step 1508 that the operator has not pressed the clear key and the set key at the same time for a predetermined time or more, the process proceeds to step 1510. Step 151
At 0, it is determined whether the key input by the operator is the UP key. If so, step 1
After proceeding to step 511 and setting the selection item to the previous item, step 15
Return to 01.

On the other hand, if the key input by the operator in step 1510 is not the UP key, the process proceeds to step 1512. In step 1512, the key entered by the operator is D
It is determined whether or not the key is the OWN key. If the key entered by the operator is the DOWN key, step 1
After proceeding to step 513 and setting the selected item to the next item, step 15
Return to 01.

On the other hand, if the key entered by the operator in step 1512 is not the DOWN key and all the above keys, nothing is done and the process returns to step 1501.

Therefore, the key input process is completed only when the menu key is input in step 1504 or the reset request is issued in step 1508, and only when the key input by the operator in step 1505 is the set key. The processing of step 1113 or step 1128 in FIG. 22 ends.

Returning to the explanation of FIG. 22 again, step 111
When the above menu selection processing in 3 is completed, the process returns to step 1114, and it is determined whether or not the adjustment item selected in step 1113 is language selection.
If it is the language selection, the language selection processing of step 1115 is performed.

On the other hand, if the adjustment item selected in step 1114 is not the language selection, the process proceeds to step 1116, and it is determined whether the selected process is input selection. If the selected process is the input selection, the process proceeds to step 1117 to perform the input selection (composite signal input / YC separated signal input) process.

On the other hand, if the process selected in step 1116 is not the input selection, the process proceeds to step 1118 to determine whether the selected process is the sound quality selection.
Step 1 if the selected process is sound quality selection
The sound quality selection processing of 119 is performed.

On the other hand, if the process selected in step 1118 is not sound quality selection, the process proceeds to step 1120, and it is determined whether the selected process is contrast adjustment. If the selected process is contrast adjustment, the process proceeds to step 1121 to perform contrast adjustment process.

On the other hand, if the process selected in step 1120 is not contrast adjustment, the process proceeds to step 1122, and it is determined whether or not the selected process is brightness adjustment. If the selected other process is the brightness adjustment, the process proceeds to step 1123 to perform the brightness adjustment process.

On the other hand, if the process selected in step 1122 is not brightness adjustment, the process proceeds to step 1124,
It is determined whether the selected process is saturation adjustment. If the selected process is the saturation adjustment, the process proceeds to step 1125 to perform the saturation adjustment process.

On the other hand, in step 1126, it is determined whether or not the selected process is hue adjustment. If the selected process is the hue adjustment, the process proceeds to step 1127 to perform the hue adjustment process. Otherwise, if a process other than the above is selected, the process ends immediately.

Here, step 1115 described above is used.
The language selection processing in will be described with reference to FIG. In step 1601, the language selection screen is displayed by OSD, and in step 1602, the operation waits until the operator inputs a key. Then, when there is a key input from the operator, the process proceeds to step 1603, and the key input from the operator is TV /
PC switch key or volume UP key or volume D
It is determined whether the key is the ONW key. If these are key inputs, the process returns to step 1602.

On the other hand, if it is determined in step 1603 that the key input from the operator is not the TV / PC switching key, the volume UP key, or the volume DonW key, step 16
Go to 04. In step 1604, it is determined whether the key input from the operator is the menu key or the set key. If these keys are key inputs, the process returns to the menu selection process of step 1113 or step 1128.

On the other hand, if the key input from the operator is not the menu key or the set key in step 1604, the process returns to step 1606. In step 1606, it is determined whether the key input from the operator is the clear key. If it is the clear key input, the process proceeds to step 1607, the set value is returned to the set value at the time when the processing is started, and then the process returns to step 1601.

On the other hand, if the key input from the operator is not the clear key in step 1606, the process proceeds to step 1608. In step 1608, it is determined whether or not the operator has pressed the clear key and the set key at the same time for a certain period of time or more. If so, the process proceeds to step 1609 as a reset request, reset processing is performed, and then, The language adjustment process and the key input process are ended.

On the other hand, if it is not the reset request, the process proceeds to step 1610. In step 1610, it is determined whether the key input from the operator is the UP key. If the key input from the operator is the UP key, the process proceeds to step 1611 to set the setting value to the previous item, or
Alternatively, increase the set value. Then, the process returns to step 1601.

On the other hand, if the key input from the operator is not the UP key in step 1610, the process proceeds to step 1612. In step 1612, it is determined whether the key input from the operator is the UP key. When the key input from the operator is the UP key, the process proceeds to step 1613,
Change the setting value to the next item or DOWN the setting value. Then, the process proceeds to step 1601.

On the other hand, if the key input from the operator is not the UP key at step 1612 and the key input from the operator is not any of the above keys, nothing is done and the process returns to step 1601.

Input type selection processing in step 1117, sound quality selection processing in step 1119, step 1 in FIG.
The same processing as above is performed for the contrast adjustment processing of 121, the brightness adjustment processing of step 1123, the saturation adjustment processing of step 1125, and the hue adjustment processing of step 1127.

In the processing of FIG. 22, step 1128
In the menu processing, the processing for selecting a setting item is selected through the menu screen in the PC mode in the same manner as in step 1113. Then, the process proceeds to step 1129. In step 1129, it is determined whether or not the selected process is language selection, and if it is language selection, the language selection process of step 1130 is performed. Otherwise, it proceeds to step 1131.

In step 1131, it is determined whether or not the selected process is the sound quality selection. If it is the sound quality selection, the sound quality selection process of step 1132 is performed. If not, proceed to step 1133.
In step 1133, it is determined whether or not the selected process is γ selection. If it is γ selection, the γ selection process of step 1134 is performed. If not, proceed to step 1135.

In step 1135, it is determined whether or not the selected process is gradation selection. If it is gradation selection, the gradation selection process of step 1136 is executed. If not, proceed to step 1137.
In step 1137, it is determined whether or not the selected process is the phase adjustment. If it is the phase adjustment, the phase adjustment process of step 1138 is performed. If not, proceed to step 1139.

In step 1139, it is determined whether or not the selected process is position adjustment. If not, the process proceeds to step 1141. In step 1141, it is determined whether or not the selected process is DPMS adjustment. If it is DPMS adjustment, the DPMS adjustment process of step 1142 is performed. If not, proceed to step 1143.

In step 1143, it is determined whether or not the selected process is model setting, and if it is model setting, the model setting process of step 1144 is performed. Otherwise, if a process other than the above is selected,
Immediately, the key input processing is ended.

The system control unit 1.91 performs the above-mentioned determination processing, OSD display control, various adjustment selection processing control, and the like.

Next, regarding OSD (on-screen display) display, which displays necessary information on the screen of the display unit 1.5 to facilitate various adjustment processes by the operator,
26 to 29, and FIG. 1 of the present embodiment.
A description will be given with reference to FIG. 30 showing enlargement of the character size by the display control device shown in FIG.

The system control unit 1.91 determines whether the OSD display is requested based on the OSD display request from the key input process by the operator.
The OSD display start position (horizontal,
(Vertical), display pattern, font size, display color, blinking presence / absence, space between fonts, etc. to transfer the OS like the display examples shown in FIGS.
Display D.

26 and 27 are examples of the OSD display of the menu screen in the adjustment item selection process described with reference to FIG. 24 in the description of the key input process described above.
26 and 27 show the case where the language selection is selected as the setting item as an example.

FIG. 26 shows a display example when the background of characters is not a watermark, and the selected language (LA
NGUAGE) has a different color from the background of other items, or by blinking,
Distinguished from other items. Further, FIG. 27 shows a display example in which the background of characters is a watermark. in this case,
Only the background of the selected item is colored instead of the watermark.

FIG. 28 shows an example of the OSD display when the language selection (LANGUAGE) is selected by the adjustment item selection processing shown in the flowchart of FIG. 24 on the menu screens shown in FIGS. 26 and 27. In this case, since it is a two-person selection type, every time the UP and DOWN keys are pressed, English (ENGLISH) and Japanese (JA
PANESE) is selected alternately.

FIG. 29 shows an example of the OSD display when the brightness adjustment is selected in the above menu selection processing. In this case, the adjustment value is changed stepwise by the UP and DOWN keys. For example, if there are 255 setting values and the OSD display level is 10 steps, the OSD display level is also increased / decreased by 1 each time the set value is increased / decreased by about 25.

Next, the font size displayed by the OSD will be described with reference to FIGS. 30 and 31. As shown in FIG. 30, a composite video signal s1.06 and a YC separated video signal s which are TV signals such as NTSC / PAL.
When 1.08 is displayed, OSD display data s1.1
8 is doubled in the vertical direction in the conversion unit 1.24 for converting data in field units into data in frame units.

Further, the interpolating unit 1.25 sets the horizontal direction to 2
It will be doubled in size. When it is finally displayed on the display unit 1.5, the same data is displayed in two lines in the vertical direction, which means that the data is enlarged to twice the size in the vertical direction. , Vertically 4
It is enlarged to double size. Therefore, as the font size used for the OSD display, a font having a size twice as large in the horizontal direction and one size as the vertical direction is used.
Above, a font of 4 times the size can be displayed in both the horizontal and vertical directions.

On the other hand, as shown in FIG. 31, when the computer input signal s1.01 is displayed, the OSD display data s1.18 is switched by the switch section 1.06 to the computer input signal s1.01 and output. At this time, the same data is read four times in order to read at the same clock speed as the computer input signal s1.01.

Therefore, the size is expanded to four times in the horizontal direction. Therefore, as the font size used for OSD display, a font having a size of 1 times in the horizontal direction and a size of 4 times in the vertical direction is used, so that the horizontal and vertical directions on the display device 1.5 are 4 times the same as the above case. The size font can be displayed.

FIG. 35 shows a list of items displayed by the OSD at the time of displaying the video signal and the computer signal. In the display control device of this embodiment,
OS with different contents as shown in Table 1 at each display
Display D.

Therefore, in the display device of this embodiment, OSD display of different font sizes, different read clock speeds, and different display contents is performed during video signal display and computer signal display.

In the case of a video input signal such as NTSC, the OSD control section 1.93 switches the switch section 1.23, and
In case of computer input signal, switch section 1.06
By switching the OSD data s1.18 to the image data s1.10 and s1.04.
0 and s1.04 are switched and output.

The switch section 1.32 uses the key input processing described later to select the system control section 1.9 based on the operator's selection.
Video input signal s such as NTSC which is switched by 1
The computer input signal s1.05 is switched to 1.13 and transferred to the digital processing unit 1.4.

Next, the processing performed by the digital processing section 1.4 will be described with reference to FIG. A video input signal s1.11 and a computer input signal s such as NTSC, which are switched and input in the switch unit 1.3.
1.14 is subjected to γ correction processing and gradation adjustment processing in the contrast adjustment section 5.01.

The gamma correction process in the contrast adjusting section 5.01 will be described with reference to FIG.
FIG. 33 shows the case of γ = 2.2 and 8-bit input and 8-bit output. If the input data is a, for example, γ
= 1.0, the output data is also a, but when γ = 2.2, the output data is b (<a), and an image with higher contrast than that when γ = 1.0 is obtained.

Next, with reference to FIG. 34, the gradation adjusting process in the contrast adjusting section 5.01 of this embodiment will be described. When the gradation adjustment processing is not performed, the value 1 in FIG.
As shown by 00%, it takes a linear output value with respect to the input value, but when 50% gradation adjustment is performed, 0 to 64,
The output values corresponding to the input data of 192 and 255 are pasted to 0 and 255, respectively, and the input data in the meantime changes by twice the change amount of the input data, as shown in FIG.

As described above, as the gradation adjustment value is decreased (the% is decreased), an image with higher contrast can be obtained.

The adjustment values in the γ correction processing and the gradation adjustment are selected by the operator through the above key input processing,
The system controller 1.91 sets the contrast converter 4.01.

Gamma-corrected and tone-adjusted data s
5.01 is sent to the halftone processing unit 5.02, where
For example, halftone processing such as an ED (error diffusion) method or a dither method is performed. Then, the data s subjected to the halftone processing
5.02 is stored in the memory unit 5.03.

The motion detecting section 5.04 steals the display data before the halftone processing, detects a line which has changed by a predetermined value or more, and detects the result as the system control section 1.91.
Transfer to. The system control unit 1.91 includes a memory unit 5.
Of the frame display data stored in 03, only the line display data in which the motion is detected by the motion detecting section 5.04 is read out, and this read data s5.03 is displayed in the display control section 5.05 together with the line address data. Output.

The display control section 5.05 displays the line display data at the vertical position designated by the line address data of the display device 5.06.

Next, the power supply unit 1.8 will be described. The power supply unit 1.8 shown in FIG. 1 supplies power to the TV signal processing unit 1.2, the computer signal processing unit 1.1, the digital processing unit 1.4, and other units.
The power supply unit 1.8 is controlled by the system control unit 1.91, and turns on / off the power supply of the TV signal processing unit 1.2, the computer signal processing unit 1.1, and the digital processing unit 1.4.

As described above, according to this embodiment, the phase time adjustment of the video signal and the sampling clock is set to DE.
Do it in LAYLINE and do the dot matrix type F
It becomes possible to display a clear image on the LCD.

By programmablely adjusting the time of DELAYLINE, the image of a personal computer having various display modes such as VGA and SVGA can be clearly displayed on the FLCD.

Furthermore, by configuring the clock generation unit with a one-chip IC, which is the same process, the temperature characteristics are the same, and a circuit for compensating the temperature characteristics that differ depending on the elements is not required.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Needless to say, the present invention can be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus.

[0193]

As described above, according to the present invention, the phase of the sampling clock and the image data can be adjusted, so that the image on the display becomes clear and the phase time corresponding to various display modes is improved. By adjusting, various image data including a personal computer can be clearly displayed on the display.

[0194]

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration of an embodiment according to the present invention.

FIG. 2 is a diagram showing a detailed policy of the synchronization signal measuring unit shown in FIG.

FIG. 3 is a diagram for explaining the contents of the FIFO of FIG.

FIG. 4 is a diagram illustrating the contents of registers in FIG.

FIG. 5 is a flowchart showing a mode determination operation in this embodiment.

6 is a diagram illustrating a detailed configuration of a PLL clock generation unit shown in FIG.

7 is a diagram illustrating a detailed configuration of the PLL counter of FIG.

FIG. 8 is a timing chart for explaining the operation of FIG. 7;

9 is a diagram illustrating the principle of interpolation processing in the interpolation processing unit shown in FIG.

10 is a diagram illustrating the principle of interpolation processing in the interpolation processing unit shown in FIG.

11 is a diagram for explaining the principle of interpolation processing in the interpolation processing section shown in FIG.

12 is a diagram showing a detailed configuration of an interpolation processing unit shown in FIG.

13 is a diagram showing a detailed configuration of a vertical interpolation processing unit and an interpolation control unit shown in FIG.

14 is a diagram showing an internal block configuration of an arithmetic unit for the input image data shown in FIG.

FIG. 15 is a detailed block diagram of the exponent calculator shown in FIG. 14.

FIG. 16 shows 6 in the (VGA) display mode of the present embodiment.
It is a figure explaining 40 dot x 350 line interpolation.

FIG. 17 is a diagram illustrating 800 dot × 600 line interpolation in the (VESA) display mode according to the present embodiment.

FIG. 18 is a diagram illustrating 800 dot × 600 line interpolation in the (VESA 60 Hz) display mode according to the present embodiment.

FIG. 19 is a diagram illustrating 800 dot × 600 line interpolation in the (VESA 72 Hz) display mode according to the present embodiment.

FIG. 20 is a diagram illustrating 1024 dot × 768 line interpolation in the (VESA) display mode according to the present embodiment.

FIG. 21 is a diagram illustrating 1024 dot × 768 line interpolation in the display mode in the (MAC) series according to the present embodiment.

FIG. 22 is a flowchart showing key processing in the present embodiment.

FIG. 23 is a diagram illustrating a key operation panel according to the present embodiment.

24 is a flowchart showing details of the menu selection processing shown in FIG. 22 in the present embodiment.

FIG. 25 is a flow chart showing details of various menu selection processing such as the language selection processing shown in FIG. 22 in the present embodiment.

FIG. 26 is a diagram illustrating an OSD display menu in this embodiment.

FIG. 27 is a diagram illustrating an OSD display menu in this embodiment.

FIG. 28 is a diagram illustrating an OSD display menu in this embodiment.

FIG. 29 is a diagram illustrating an OSD display menu according to the present embodiment.

FIG. 30 is a diagram illustrating OSD display control during enlarged display in this embodiment.

FIG. 31 is a diagram illustrating OSD display control during enlarged display in this embodiment.

32 is a block diagram showing a detailed configuration of a digital processing unit shown in FIG. 1. FIG.

FIG. 33 is a diagram illustrating a γ characteristic of a CRT.

FIG. 34 is a diagram illustrating a γ characteristic of the FLCD in this example.

FIG. 35 is a diagram showing an example of an OSD menu in this embodiment.

[Explanation of symbols]

10 Display control device 1.01 Synchronous signal separation unit 1.02 Synchronous signal measurement unit s1.01 Video signal s1.02 Image signal 1.03 A / D converter 1.04 Clock generation unit 1.05 Interpolation processing unit cs1. 01 sync signal cs1.02 sync signal polarity discrimination signal 1.21 tuner section 1.22 color decoder section 1.24 field / frame converter 1.5 display device 1.7 audio processor 1.71 delay adjuster 1.72 Audio processing unit 1.73 Speaker unit 1.91 System control unit 1.93 OSD control unit 2.01 Clock generator cs2.01 Horizontal synchronization signal cs2.02 Vertical synchronization signal cs2.03, cs2.04 Frequency clock cs2.11 NHD cs2.12 TVD cs2.13 TVBlank cs2.22 Comparator output cs1 19 control bus 2.02 counter for periodically measuring 2.03 Counter 2.04 retrace time for period measurement THBlank (vertical synchronizing signal H
Counter for measuring D level "0") 2.05 FIFO 2.11 Vertical sync signal VD-Horizontal sync signal H in cycle
Counter for measuring the number of D 2.12 Counter for measuring the period of the vertical synchronizing signal VD 2.13 Retrace time VBlank of the vertical synchronizing signal VD
Counter for measuring (the level of the vertical synchronizing signal VD is “0”) 2.14 register 2.21 HD number comparison register 2.22 comparator 2.30 R / W control unit 3.05 phase comparator 3.06 to 3.08 Charge pump type low pass filter 3.10 VCO (Voltage-controlled Oscillator) 3.04 division period 3.01 to 3.16 clock generation module 3.02 polarity inversion unit 3.03 DERAYLINE cs3.01 horizontal synchronization signal cs3.03 dot clock signal 3.04 minute cycle 3.17 register 3.12 programmable counter 3.20 shift register 3.21 register 3.22 main device cs3.05 control signal 3.06 D / A converter 3.07 low pass Filter 3.08 Low-pass filter cs3.07 Gain control No. 3.06 VCO 3.11 D / A converter 3.10 VCO 3.13 DELAYLINE 3.14 Output level switching cs 3.11 Output controller 3.15 1/2 frequency division output level switching 3.16 Output level switching 4. 01 input unit 4.02 control input unit 4.02.01 memory device 4.02.02 setting supply device 4.03 synchronization input unit 4.04 output unit 4.05 output clock supply unit 4.06 vertical interpolation processing unit 4 0.07 interpolation control unit 4.06.01 flip-flop (F / F) circuit 4.06.02 input Fast In Fast Out (FIFO) memory 4.06.03 operation unit 4.06.04 output Fast In Fast Out ( FIFO) memory 4.06.05 switch section 4.06.06 switch section 4.07.01 input FIFO control section 4.07.02 output FIFO write Control unit 4.07.03 Output FIFO control unit 4.07.04 Display position detection unit 4.07.05 Output display position correction device 4.07.06 Arithmetic control unit 5.01 Contrast adjustment unit 5.02 Halftone Processing unit 5.03 Memory unit 5.04 Motion detection unit 5.05 Display control unit 5.06 Display device

Claims (8)

[Claims] 1. A display control device for inputting a video signal including an image signal and a sync signal to display on a display, the clock being a horizontal sync signal of the sync signal for generating a pixel sync clock signal. Generating means; control means for controlling the clock generating means; A / D converting means for converting an image signal of the video signal into a corresponding digital signal in synchronization with a pixel synchronization clock generated by the clock generating means, An output unit that inputs the synchronization signal, the pixel synchronization clock, and the digital signal and outputs the digital signal to the display; and the clock generation unit includes a delay unit that adjusts a delay of the horizontal synchronization signal. Display controller. 2. The clock generation means includes frequency division means for frequency-dividing the pixel synchronization clock signal, wherein the clock signal frequency-divided by the frequency division means and the horizontal synchronization whose delay is adjusted by the delay means. 2. The table control device according to claim 1, wherein the phase of the signal is locked and the pixel synchronizing clock signal is output. 3. The display control device according to claim 2, wherein the oscillating means is a voltage controlled oscillator. 4. The display control device according to claim 2, wherein the frequency dividing means is capable of arbitrarily controlling a frequency dividing ratio by the control means. 5. The display control device according to claim 1, wherein the delay unit can arbitrarily control the delay time by the control unit. 6. The display control device according to claim 1, wherein the A / D conversion means samples the video signal in synchronization with the pixel synchronization clock and converts it into a corresponding digital signal. 7. A display control method in a display control device for inputting a video signal including an image signal and a sync signal and displaying the video signal on a display device, wherein the horizontal sync signal of the sync signal is input. Adjust the delay of to generate the pixel sync clock signal,
Converting the image signal of the video signal into a corresponding digital signal in synchronization with the generated pixel synchronization clock, and outputting the synchronization signal, the pixel synchronization clock, and the digital signal to the display for display. Characteristic display control method. 8. The pixel synchronization clock signal is generated by adjusting a delay between a clock signal obtained by dividing the pixel synchronization clock signal and the horizontal synchronization signal to lock the phase of the horizontal synchronization signal. The display control method according to claim 7, wherein a pixel synchronization clock signal is output.