JPH08297478A - Device and method for display control and display device - Google Patents

Abstract

PURPOSE: To make it possible to properly display OSD in correspondence to each display condition different in image resolution and dot clock. CONSTITUTION: An OSD control section 1.93 judges whether the display mode of an image signal in display is the display of the video signal s1.13 or that of the computer input signal s1.05 based on a signal cs1.11. The OSD control section 1.93 selects the OSD data to be displayed based on the judged display mode. The selected OSD data s1.18 selected is changed to the image signal under display at present by a switch section 1.23 or 1.06 to be ultimately inputted into a digital processing section 1.4. The section 1.4 outputs the inputted OSD data to a display device 1.5 by the display mode of the image signal displayed just before.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device and method for a display, and a display device equipped with the display control device. In particular, the present invention relates to a display control device and method suitable for display control of a display device having a dot matrix display.

[0002]

2. Description of the Related Art There is a display controller for receiving a television input signal such as NTSC, PAL, SECAM or the like and a computer input signal for a personal computer, a workstation or the like and displaying the signal on a display device.

Further, in recent years, there is a technique called OSD (on-screen display) display for performing a display for facilitating various adjustment processes on a display device. The operator can easily perform various adjustment processing of the display device such as the brightness and contrast of the display screen by operating various operation keys provided in the display device while observing the OSD display. .

On the other hand, from various host computers to CRT
Analog input signal (CRT signal) input to the display device
There is a display interface called P & P (Plug and Play) that receives a signal as it is and converts it into a signal that can be displayed on a stand-alone type liquid crystal display device. The P & P interface is a very effective interface for replacing the CRT display device with a stand-alone type liquid crystal display device.

[0005]

The above P & P interface is compatible with various input signals of a personal computer, a workstation, a TV, a VTR, and can change the display mode (display resolution) of the personal computer. There is an increasing demand to realize a sync P & P interface. However, when implementing such a multi-sync P & P interface, since the input signal from the host computer and the input signal from the TV, VTR, etc. have different resolutions and different dot clocks, the respective input signals and the above The OSD display data could not be switched and output.

The present invention has been made in view of the above problems, and a display control method and apparatus capable of appropriately displaying an OSD corresponding to each display state in which the image resolution and the dot clock are different, and An object is to provide a display device.

[0007]

The display control device of the present invention for achieving the above object has the following configuration.
That is, a display control device having a plurality of types of display modes for displaying a plurality of types of image signals corresponding to different resolutions and dot clocks, the determination means determining the display mode of the image signal being displayed, Selecting means for selecting the OSD data to be displayed based on the display mode judged by the judging means; input means for switching and inputting the OSD data selected by the selecting means with the image signal currently being displayed; Output means for outputting the OSD data input by the means in the display mode of the image signal.

Preferably, the OSD data has a font size and shape corresponding to each display mode,
The selecting means selects the OSD data so that an appropriate character size and shape can be obtained in each display mode. This is because differences in driving conditions in various display modes can be absorbed and stable OSD data can be displayed.

Further, preferably, the font size and shape are determined based on the dot clock speed in each display mode and the input speed of the OSD data by the input means. Even if the image of the OSD data is enlarged or reduced due to the difference in dot clock depending on each display mode,
This is because it is possible to maintain a desired size and shape by using font size and shape data corresponding to this change.

Preferably, the OSD data has a display content corresponding to each display mode, and the selecting means selects the OSD data having a display content suitable for each display mode. This is because an appropriate operation can be performed in each display mode.

Preferably, the plurality of types of display modes include at least a first display mode for displaying a composite video signal and a second display mode for displaying a computer CRT signal. This is because it is possible to provide typical display modes with different driving modes, and it is possible to replace the display control device with a wide range of application.

Further, preferably, when the OSD data is displayed in the first display mode, the output means is
The input OSD data is subjected to the same processing as the processing applied to the RGB signal obtained by converting the composite video signal and output.

[0013]

According to the above construction, in the display control device having plural kinds of display modes for displaying plural kinds of image signals corresponding to different resolutions and dot clocks, OSD display adapted to each display mode is performed. Be seen. This is accomplished as follows. First, the judging means judges what the display mode of the image signal being displayed is, and the selecting means selects the OSD data to be displayed based on the display mode judged by the judging means. When the input means switches the selected OSD data to the image signal currently displayed and is input, the output means outputs the input OSD data in the display mode of the image signal displayed immediately before.

Therefore, for example, OSD data suitable for each of the input signal from the host computer and the input signal from the TV, VTR or the like can be appropriately output.
A multi-sync P & P interface is realized.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a display control device 1 according to this embodiment.
It is a block diagram of 0. This display control device 10 is NTS
Composite video signal input such as C, PAL, SECAM, YC (luminance, color difference) separation signal input, and
An analog computer input signal from a PC (personal computer), WS (workstation) or the like can be received and displayed on the display unit 1.5.

The composite video signal processing section 1.2 will be described.

First, a composite analog image signal of NTSC, PAL, SECAM or the like input through the tuner 1.21 or directly is a color decoder 1.2.
2, A / D conversion, color difference demodulation, and matrix conversion into RGB signals are performed. The YC separated image signal is A / D converted by the color decoder 1.22 and matrix-converted into an RGB signal to obtain RGB field data. The RGB field data is converted from 60 Hz field data to 60 Hz frame data in the field / frame conversion section 1.24.

The frame data is processed by the horizontal interpolation processing unit 1.2.
5, the interpolation processing is performed to a horizontal resolution equal to the horizontal resolution of the display unit 1.5. However, since the interpolation processing performed here is interpolation processing with a double resolution in the horizontal direction, it is performed by reading the same data twice.

Next, the voice processing unit 1.7 will be described.

The delay adjustment unit 1.71 is a system control unit 1.9.
Image display on the display unit 1.5, which is controlled by 1.
Adjust the deviation from the sound output from the speaker 1.73.

In the display section 1.5, a slight delay occurs in image display in the upper left and right corners of the display screen depending on the operating temperature of the main body. For this reason, when it is necessary to synchronize the moving image with the sound like a TV signal, a temporal mismatch occurs between the image affected by the temperature and the sound not affected by the temperature. In order to eliminate this phenomenon, the temperature information of the display unit 1.5 is fed back to the system control unit 1.91. Based on the fed back information, the system control unit 1.91 controls the delay adjustment unit 1.71 to generate a sound delay time for synchronizing the image and the sound. In other words, when there is no delay in the image display, the sound delay is not generated, and when there is a delay in the image display, the sound delay is generated.

However, for the audio delay time to be generated, the correlation table between the temperature of the display section 1.5 and the image display delay time prepared in advance is referred to and the corresponding delay time is extracted. By adjusting the delay, the image and the sound can be synchronized regardless of the temperature change of the display unit 1.5.

The delay-adjusted audio signal is sent to the audio signal processing unit 1.72. The audio signal processing unit 1.72 has a sound processor, an audio amplifier and the like. The sound processor controls the volume of audio input, switches between stereo / monaural, and controls by the system controller 1.91.
Performs left and right speaker balance adjustment, tone control, surround processing, etc.

The audio signal output from the sound processor 1.72 is sent to the audio amplifier and the speaker 1.
Amplification processing is performed for 73. The amplified audio signal is sent to the speaker 1.73 and output as audio.

Next, the computer image signal processing section 1.1.
Will be described.

An analog computer image signal of PC, WS, etc. is separated into horizontal and vertical synchronizing signals and analog RGB signals in a synchronizing signal separating section 1.01. The sync signal separation unit 1.01 will be described in detail. The sync signal separation unit 1.01 is a video signal s composed of RGB image signals from a computer or the like and sync signals such as composite sync, separate sync or sync on green.
Input 1.01, image signal s1.02, sync signal cs
It outputs 1.01 and the sync signal polarity discrimination signal cs1.02. The image signal s1.02 is output to the A / D converter 1.03. The sync signal cs1.01 is obtained by converting the sync signal separated from the input video signal into a negative sync signal, and the sync signal measuring unit 1.02, the clock generating unit 1.04, the interpolation processing unit 1 .05 and the system control unit 1.91. Sync signal polarity discrimination signal cs1.
02 indicates the polarity of the input synchronizing signal s1.01, and is output to the system control unit 1.91.

The horizontal and vertical synchronizing signals separated by the synchronizing signal separating unit 1.01 are input to the synchronizing signal measuring unit 1.02, and the horizontal and vertical frequencies and the polarities of the horizontal and vertical synchronizing signals are measured.

Here, the processing performed in the sync signal measuring section 1.02 will be described in detail with reference to FIG. FIG. 2 is a block diagram showing a detailed control configuration of the synchronization signal measuring unit 1.02.

Reference numeral 2.01 denotes a clock generator, which has a frequency sufficiently higher than the period of these signals for measuring the period of the horizontal synchronizing signal (HD) cs2.01 and the vertical synchronizing signal (VD) cs2.02. , A clock of a predetermined frequency, cs2.03, and cs2.
04 is generated.

2.02 is a horizontal synchronizing signal HD (cs2.0).
1) A counter for period measurement, which is a horizontal synchronization signal H
It is reset at the falling edge of D (cs2.01), and the clock cs2.03 having a predetermined frequency is counted by the clock generator 2.01 during the period from the falling edge to the next falling edge. Measurement count value T which is the result of this count
HD1 (cs2.05) is written to the FIFO memory 2.05 in synchronization with the rising edge of the horizontal synchronizing signal HD.

2.03 is a cs2.01 horizontal synchronizing signal HD
Of the horizontal synchronizing signal HD (c
s2.01) is reset at the rising edge of the clock, and clock generator 2.0
A clock cs2.03 having a predetermined frequency from 1 is counted. Then, the measurement count value THD2 that is the result
(Cs2.05) is written to the FIFO memory 2.05 in synchronization with the rising edge of the horizontal synchronizing signal HD.

2.04 is a horizontal synchronizing signal HD (cs2.0).
This is a counter for measuring the blanking time THBlank (1) (period when the level of the vertical synchronizing signal HD is “0”). The counter 2.04 is reset at the falling edge of the horizontal synchronizing signal HD (cs2.01), and counts the clock cs2.03 of a predetermined frequency from the clock generator 2.01 from that time to the next rising edge. And the measurement count value THBlank (cs2.06) which is the result
Is synchronized with the rising edge of the horizontal synchronizing signal HD,
It is written to O memory 2.05.

Reference numeral 2.05 denotes a FIFO memory, which has the above-mentioned THD1 (cs2.05) and THD2 (cs2.0).
6), TH Blank (cs 2.07) data is stored for one cycle of the vertical synchronizing signal VD. FIG. 3 is a diagram showing a data storage state in the FIFO memory 2.05 in the sync signal measuring unit 1.02. These data are R /
Through the W control unit 2.30, it is possible to sequentially read as the signal cs1.19 from the previously stored data.

Reference numeral 2.11 is a counter for measuring the number of horizontal synchronizing signals HD in one cycle of the vertical synchronizing signal VD, which is reset at the rising edge of the vertical synchronizing signal VD (cs2.02), and then from there. One period until the rise of
The horizontal synchronizing signal HD (cs2.01) is counted as a clock. Then, the measurement count value N that is the result
HD (cs2.07) is written in the register 2.14 in synchronization with the rising edge of the vertical synchronizing signal VD.

2.12 is a vertical synchronizing signal VD (cs2.0).
The counter for period measurement of 2), which is a vertical synchronization signal VD
It is reset at the rising edge of (cs2.02), and the clock cs2.04 of a predetermined frequency from the clock generator 2.01 is counted for one period from that time to the next rising edge. And the measurement count value TV which is the result
D (cs2.12) is written into the register 2.14 in synchronization with the rising edge of the vertical synchronizing signal VD.

2.13 is a blanking time VBlank of the vertical synchronizing signal VD (a period in which the level of the vertical synchronizing signal VD is "0").
Of the vertical synchronization signal VD (c
It is reset at the falling edge of s2.02) and the clock cs2.04 having a predetermined frequency from the clock generator 2.01 is counted from that point until the next rising edge. And the measurement count value TVBlank which is the result
(Cs2.13) is written in the register 2.14 in synchronization with the rising edge of VD.

2.14 is a register, which has the above-mentioned N
HD (cs2.11), TVD (cs2.12), TVB
lank (cs2.13) and VD / HD polarity (cs
1.02) is stored in synchronization with the vertical synchronization signal VD (cs2.02) as shown in FIG. FIG. 4 is a diagram showing a data storage state of the register 2.14 of the synchronization signal measuring unit 1.02. With the completion of writing the above data, R / W
The control signal cs1.19 is output to the bus through the control unit 2.30.

Reference numeral 2.21 denotes a comparison register, which stores the number of horizontal synchronizing signals HD to be compared via cs1.19.

2.22 is a comparator, which outputs the HD number counter output cs2.11 from the counter 2.11.
Comparison register output from the comparison register 2.21 cs2.
Compare with 21. As a result of the comparison, if they match, the comparator output cs2.22 is activated, and the comparator output cs2.22 is output through the R / W control unit 2.30.

2.30 is an R / W control unit, which has a FI
The FO memory 2.05, the register 2.14, the HD comparison register 2.21, the comparator output cs2.22 and the signal cs.
As 1.19, data transfer control for transferring to the control bus is performed.

The measurement value measured by the sync signal measuring unit 1.02 as described above is taken into the system control unit 1.91. The system control unit 1.91 determines the display mode of the input signal from this measured value. The system control unit 1.91 is based on the specified display mode,
Clock generation unit 1.04, interpolation processing unit 1.05, OSD
(On-screen display) Make necessary settings for the control unit 1.93.

The display mode determination will be described in detail with reference to the flow chart of FIG. FIG. 5 is a flowchart showing the procedure for determining the display mode in this embodiment. The system control unit 1.91 uses step S1001.
When the unlock signal is received from the clock generation unit 1.04, it is detected that the display mode of the input signal is changed or the host computer itself is changed to another signal specification, and the process proceeds to step S1002. Otherwise, if the clock generating means is outputting the lock signal, the processing ends without doing anything.

In step S1002, the horizontal synchronizing signal HD and the vertical synchronizing signal V are newly added from the synchronizing signal measuring section 1.02.
The frequencies of D (Hsync and Vsync, respectively) are received. Then, in step S1003, the horizontal synchronization signal frequency Hsync is the lowest corresponding frequency (H_boto
m) to AHz, and the vertical synchronization signal frequency Vsync is the lowest corresponding frequency (V_botom) to BHz.
It is determined whether it is between. If so, the process proceeds to step S1004, and the system control unit 1.92 sets the clock generation unit 1.04 in the case of MODE0. Then, in step S1005, the system control unit 1.
92 receives a lock or unlock signal from the clock generator 1.04. If the lock signal is received, it is determined in step S1006 that the display mode of the current input signal is MODE0.

Otherwise, if an unlock signal is received, the current input signal display mode is MODE0.
If not, the process proceeds to the determination process (proceeding to step S1007). The same process is performed up to MODE M. If the input signal is not identified by MODE M, the current input signal is determined to be an incompatible signal, and incompatible signal input processing is performed in step S1015.

Then, the analog RGB after the sync signal separation
The signal s1.02 is sampled by the A / D conversion unit 1.03 with a sampling clock such that the horizontal resolution becomes equal to the horizontal resolution of the dot matrix display. The sampling clock is a clock generator 1.0
4 obtained.

Next, the function of the clock generator 1.04 will be described in detail with reference to FIG. FIG. 6 is a block diagram showing the configuration of the clock generation unit 1.04. As shown in the figure, the clock generator 1.04 includes a phase comparator 3.0.
5, charge pump type low-pass filter 3.06 to 3.0
8, PLL (Phase Lock) based on VCO (Voltage-controlled Oscillator) 3.10 and division period 3.04
ed Loop) Clock generator. 3.17 is a control register for controlling the clock generator 1.04.
Data bus c connected to system controller 1.91
Interfaces with s1.19 and clock generation modules 3.01 to 3.16 described below.
Function as a group of registers that make settings for controlling the.

The horizontal synchronizing signal of the video is the signal line cs1.
01 to the i / F level selection unit 3.01. i /
In the F level selection unit 3.01, the signal interface output from the synchronization signal separation unit 1.01, such as TTL or P, is used.
The interface for the i / F signal is switched to support ECL or the like. The switching of the interface for the i / F signal is performed according to the control signal cs3.01 based on the data stored in the control register 3.17.
The polarity reversing unit 3.02 enables phase comparison at both the rising edge and the falling edge of the horizontal synchronization signal when performing the phase comparison, and the polarity switching control line cs3.0.
The polarity is switched according to 2.

The delay unit 3.03 has a horizontal synchronizing signal cs3.0.
1 and the dot clock signal s3.03 (output from the programmable counter 3.12) are input, and a delay adjustment of one dot clock period or more is programmable with respect to the horizontal synchronizing signal cs3.01. The delay time is adjusted by the delay control line cs3.03. s
The video signal input to 1.01 is synchronized with the sync signal separation unit 1.
At 01, it is divided into a sync signal and an image signal. Since they are input to different processing systems, the A / D converter 1.0
3 causes a phase difference between the image data s1.02 input to the No. 3 and the A / D conversion sampling clock cs1.03 generated by the clock generation unit 1.04. Therefore, the delay unit 3.03 adjusts the phases of the image data s1.02 and the sampling clock cs1.03. The delay-adjusted horizontal synchronization signal is output to the signal line s3.02 as the reference horizontal synchronization signal.

The frequency divider 3.04 outputs the dot clock signal s3.03 output from the programmable counter 3.12.
Is divided by the frequency division value set in the control register 3.17 by the system control unit 1.91. The frequency divider control line cs
The frequency division value is set to the counter in the frequency divider 3.04 by 3.04.

FIG. 7 is a block diagram showing the configuration of the counter in the frequency divider. The frequency divider control line cs3.04 is composed of CLOCK, DATA, and LATCH signals as shown in the figure, and DATA is serially transferred to the shift register 3.20 in synchronization with the CLOCK signal. After completion of DATA transfer, shift register 3.2 is generated by LATCH signal.
The data of 0 is transferred to the register 3.21 of the main divider. Circuit 3.23 has a main divider 3.22 value of 0.
When it becomes 0, the LOAD signal cs3.20 is output to the main divider 3.22. The main divider 3.22 receives the LOAD signal cs3.20 and transfers the data in the register 3.21 to the main divider 3.2.
Transfer to 2.

The phase comparator 3.05 has a delay-adjusted reference horizontal synchronizing signal s3.02 and an output signal s3.0 from the frequency divider.
4 is input and the phases of these signals are compared, and a voltage or pulse signal corresponding to the phase difference is generated. The phase comparison enable control signal cs3.05 is a signal for controlling whether or not the phase comparator 3.05 performs a phase comparison between the reference horizontal synchronization signal s3.02 and the output signal s3.04 from the frequency divider.

The charge pump type low pass filter is a low pass filter (3.0 specified by the charge pump 3.06 and the low pass filter switching control signal cs3.06).
7 or 3.08). This removes high frequency components and noise from the output voltage from the phase comparator 3.05 and supplies a DC voltage to the VCO 3.10.
Here, the phase comparison detection gain of the PLL can be adjusted by changing the charge pump current as follows. That is, the system control unit 1.91 sends the digital value set in the control register 3.17 to the D / A converter 3.09 via the gain control signal cs3.07. Then, the D / A converter 3.09 converts the current into a current corresponding to the value and supplies the obtained current to the charge pump 3.06 to control the charge pump current.

Further, the response characteristic of the PLL is that the low pass filter composed of a resistor and a capacitor is 3.07 or 3.0.
8 filter constants. Therefore, this PLL
The damping factor can be varied by adjusting the phase comparison detection gain and the filter constant.

The VCO 3.10 generates a signal having a frequency obtained by multiplying the reference horizontal synchronizing signal s3.02 according to the output signals from the D / A converter 3.11 and the charge pump 3.06 by the following method. That is, the system control unit 1.9
The digital value 1 set in the control register 3.17 is sent to the D / A converter 3.11 via the oscillation frequency control signal cs3.08. The D / A converter 3.11 supplies the VCO 3.10 with a current corresponding to that value. VCO 3.
10 is the output current of the D / A converter 3.11,
Determines the oscillation frequency during free run. Where VCO
The 3.10 can oscillate in a certain frequency range around the free-run frequency.

On the other hand, in that frequency range, a signal corresponding to the difference between the free-run frequency and the oscillation frequency set in the frequency divider 3.04 is output from the charge pump 3.06, and this output signal causes the VCO 3.10 to be output. The oscillation frequency of the output signal is controlled.

The programmable counter 3.12 has a VC
The system control unit 1.91 divides the output signal of O3.10 by the division value set in the control register 3.17. The frequency division value set in the control register 3.17 is set in the programmable counter 3.17 via the programmable counter control line cs3.09. Due to the existence of the programmable counter 3.12, it is possible to obtain a low frequency signal output from the variable frequency range of the VCO 3.10, and as a result, the variable frequency range can be expanded. On the contrary, since the variable frequency range of the VCO 3.10 can be narrowed, the stability of the oscillation frequency of the VCO 3.10 is improved. The output signal of the programmable counter 3.12 is a frequency divider 3.04 as a dot clock s3.03.
Is input to the delay unit 3.13.

The delay unit 3.13 adjusts the phase of the dot clock s3.03 and the reference horizontal synchronizing signal s3.02 for the following reason. That is, the PLL, which is the basic configuration of the clock generation unit 1.04, locks the phase difference between the reference horizontal synchronization signal s3.02 and the frequency divider output signal s3.04, and adjusts the phase difference. is not.
Therefore, there is a phase difference between the reference horizontal synchronization signal s3.02 and the dot clock s3.03. The delay unit 3.13 adjusts the delay time according to the delay control line cs3.10 to adjust the phase difference between these signals. A more detailed description will be given in the functional description of 1/2 frequency division output level switching (output level switching unit 3.15).

The output level switching devices 3.14 to 3.16 are TT
The output level is converted according to the signal interface level of the connection destination such as L, ECL, PECL or the output signal frequency, and the output control cs3.11 to cs3.
The output level is switched according to 13.

The output level switch 3.14 includes a delay unit 3.1.
The dot clock s3.03 from 3 is input and converted to the ECL level, and the complementary signal cs1.03
Is output to the A / D converter 1.03.

The 1/2 frequency-divided output level switching 3.15 inputs the dot clock s3.03 'from the delay unit 3.13 and the reference horizontal synchronizing signal s3.02 as a reset signal, and inputs them to ECL and TTL. The level-converted 1/2 frequency-divided signal is output.

FIG. 8 shows a 1/2 frequency division output level switch 3.1.
5 shows an operation timing chart of No. 5. Reset signal s
The Low state of 3.02 is detected at the rising edge b of the dot clock s3.03 ′, and the signals cs1.04 and cs1.06 are detected.
Is set to the reset state for four cycle periods of the dot clock s3.03 ′. At this time, surely Lo at the rising edge b
In order to latch the w state, it is necessary to satisfy the setup time for b. Therefore, the delay unit 3.13
The setup time is satisfied by adjusting the phases of the reset signal s3.02 and the dot clock s3.03. After that, dot clock s3.0
Signals cs1.04 and cs1.06 at the rising edge d of 3 '
To activate. ECL complementary signal cs
1.04 is output as a demultiplexer signal for A / D conversion 1.03, and TTL single end signal cs1.0 is output.
6 is output as the master clock of the interpolation circuit 1.05.

The output level switch 3.16 receives the reference horizontal synchronizing signal s3.02 and converts it to the TTL level.
The single end output signal cs1.05 is output to the interpolation processing unit 1.05.

Subsequently, the RGB signal s1.0 after A / D conversion
3 is interpolated by the interpolation processing unit 1.05 to a resolution that matches the vertical resolution of the display unit 1.5.

The interpolation processing performed by the interpolation processing unit 1.05 will be described in detail with reference to FIGS. 9, 10, and 11. As the interpolation processing method, the most commonly used methods include the nearest neighbor interpolation method, the linear interpolation method (first-order interpolation method), and the third-order convolutional interpolation method.

The nearest neighbor interpolation method is a method in which the pre-interpolation pixel closest to the pixel to be interpolated is used as the interpolation pixel. The linear interpolation method is a method of obtaining pixel data of a pixel to be interpolated using pixel data of pixels on both sides of a pixel to be interpolated. For example, as shown in FIG. 9, when the pixel b is interpolated at the positions (between the pixels a1 and a2) at the distances u and v from the pixels a1 and a2 arranged at the distance interval 1, respectively, The data is obtained by the following equation (1), b = a1 * u / (u + v) + a2 * v / (u + v) (1).

On the other hand, the cubic convolutional interpolation method is a method of obtaining pixel data of two pixels on both sides of the pixel to be interpolated and pixel data of the pixel to be interpolated using the cubic convolution function. The cubic convolution function f is expressed by the following equation (2), where t is the distance between the pixel to be interpolated and two pixels on both sides which are lined up at a distance of 1, and f (t) = sin (πt) / ( πt) is given by (2).

Equation (2) depends on the range of t, and equations (3), (4),
It is developed as in (5). That is, f (t) = 1-2 * | t | ^ 2 + | t | ^ 3 (0 ≦ | t | <1)… (3) f (t) = 4-8 * | t | + 5 * | t | ^ 2- | t | ^ 3 (0 ≦ | t | <1)… (4) f (t) = 0 (2 ≦ | t |)… (5) where A ^ 2 is A * A and A ^ 3 represent A * A * A, respectively.

For example, as shown in FIG. 10, the pixels a1, a2, a3, a4 arranged at the distance interval 1 to u are respectively arranged.
Positions at a distance of 1, u2, u3, u4 (pixels a2 and a
When the pixel b is to be interpolated (between 3), the pixel data of the pixel b is obtained by the equation (6) using the cubic convolution function f.

B = a1 * (4-8 * u1 + 5 * u1 ^ 2-u1 ^ 3) + a2 * (1-2 * u2 ^ 2 + u2 ^ 3) + a3 * (1-2 * u3 ^ 2 + u3 ^ 3) + a4 * (4-8 * u4 + 5 * u4 ^ 2-u4 ^ 3) (6) Here, using Equations (1) and (6), for example, 768 pixels to 960 pixels. A case of performing interpolation processing on a pixel by a linear interpolation method (first-order interpolation method) and a third-order convolutional interpolation method will be described with reference to FIG. 11. In the case of this example, the interpolation data of 8 pixels is created from the data before interpolation of 5 pixels.
Therefore, the pixel data bn after the linear interpolation and the pixel data bn after the interpolation by the cubic convolution interpolation method are given by the equations (7) and (8) using the pixel data an before the interpolation, respectively.

B [5n + 1] = a4n + 1 (n = 0,1,2 ...) b [5n + 2] = (4/5) * a [4n + 1] + (1/5) * a [4n + 2] b [5n + 3] = (3/5) * a [4n + 2] + (2/5) * a [4n + 3] b [5n + 4] = (2/5) * a [4n + 3] + (3/5) * a [4n + 4] b [5n + 5] = (1/5) * a [4n + 4] + (4/5) * a [4n + 5 ]… (7) b [5n + 1] = a [4n + 1] (n = 0,1,2…) b [5n + 2] = (-4/125) * a [4n] + (29 / 125) * a [4n + 1] + (116/125) * a [4n + 2] + (-16/125) * a [4n + 3] b [5n + 3] = (-12/125) * a [4n + 2] + (62/125) * a [4n + 2] + (93/125) * a [4n + 3] + (-18/125) * a [4n + 4] b [5n + 4] = (-18/125) * a [4n + 2] + (93/125) * a [4n + 3] + (62/125) * a [4n + 4)] + (-12/125) * a [4n + 5] b [5n + 5] = (-16/125) * a [4n + 3] + (116/125) * a [4n + 4] + (29/125) * a [4n +5] + (-4/125) * a [4n + 6] (8)

However, if it is attempted to configure the interpolation processing by the linear interpolation method or the cubic convolutional interpolation method by the hardware (ASIC) using the equations (7) and (8), it is necessary to calculate a complicated fraction. Therefore, the scale becomes unrealistic.

Therefore, in the display control apparatus according to the present embodiment, in view of the above problems, small-scale hardware (ASI) is used.
In C), in order to realize the interpolation processing by the linear interpolation method or the cubic convolutional interpolation method, the coefficients of Expressions (7) and (8) are approximated by the sum of the exponents of 2. Approximate results of equations (7) and (8) are obtained as equations (9) and (10), respectively.
Shown in

B [5n + 1] = a [4n + 1] (n = 0,1,2 ...) b [5n + 2] = (1/2 + 1/4) * a [4n + 1] + (1/4) * a [4n + 2] b [5n + 3] = (1/2 + 1/8) * a [4n + 2] + (1/4 + 1/8) * a [4n + 3] b [5n + 4] = (1/4 + 1/8) * a [4n + 3] + (1/2 + 1/8) * a [4n + 4] b [5n + 5] = ( 1/4) * a [4n + 4] + (1/2 + 1/4) * a [4n + 6] (9) b [5n + 1] = a [4n + 1] (n = 0, 1,2 ...) b [5n + 2] = (-1/16) * a [4n] + (1/4) * a [4n + 1] + (1/2 + 1/4 + 1/8 + 1/16) * a [4n + 2] + (-1/8) * a [4n + 3] b [5n + 3] = (-1/8) * a [4n + 1] + (1/2 ) * a [4n + 2] + (1/2 + 1/4) * a [4n + 3] + (-1/8) * a [4n + 4)] b [5n + 4] = (-1 / 8) * a [4n + 2] + (1/2 + 1/4) * a [4n + 3] + (1/2) * a [4n + 4] + (-1/8) * a [ 4n + 5] b [5n + 5] = (-1/8) * a [4n + 3] + (1/2 + 1/4 + 1/8 + 1/16) * a [4n + 4] + (1/4) * a [4n + 5] + (-1/16) * a [4n + 6] (10) The approximation from equation (7) to equation (9) has as few coefficient terms as possible, In addition, the approximation was performed so that the maximum approximation error was within 1/20. Also, the approximation from equation (8) to equation (10)
The approximation is performed so that the number of coefficient terms is as small as possible and the maximum approximation error is within 1/32. If it is desired to reduce the deterioration of the image quality due to the interpolation processing, the maximum approximation error is further reduced by adding a term smaller than 1/64. On the contrary, when it is desired to make the hardware (ASIC) smaller, it is possible to reduce the hardware (ASIC) scale by increasing the approximation error by applying a small term such as 1/64 or 1/32. it can.

Similarly, the approximation result in the case of performing interpolation from 480 pixels to 960 pixels is expressed by equation (11) for linear interpolation and equation (1) for cubic convolution interpolation.
2).

B [2n + 1] = a [n + 1] (n = 0,1,2 ...) b [2n + 2] = (1/2) * a [n + 1] + (1/2 ) * a [n + 2] ... (11) b [2n + 1] = a [n + 1] (n = 0,1,2 ...) b [2n + 2] = (-1/8) * a [n] + (1/2 + 1/8) * a [n + 1] + (1/2 + 1/8) * a [n + 2] + (-1/8) * a [n + 3 ] (12) Further, similarly, the approximation result in the case of performing the interpolation from 600 pixels to 960 pixels is expressed by the formula (1
3) The cubic convolutional interpolation is shown in Expression (14).

B [8n + 1] = a [5n + 1] (n = 0,1,2 ...) b [8n + 2] = (1/2 + 1/8) * a [5n + 1] + (1/4 + 1/8) * a [5n + 2] b [8n + 3] = (1/4) * a [5n + 2] + (1/2 + 1/4) * a [5n + 3] b [8n + 4] = (1/2 + 1/4 + 1/8) * a [5n + 2] + (1/8) * a [5n + 3] b [8n + 5] = ( 1/2) * a [5n + 3] + (1/2) * a [5n + 4] b [8n + 6] = (1/8) * a [5n + 4] + (1/2 + 1 / 4 + 1/8) * a [5n + 5] b [8n + 7] = (1/2 + 1/4) * a [5n + 4] + (1/4) * a [5n + 5] b [8n + 8] = (1/4 + 1/8) * a [5n + 5] + (1/2 + 1/8) * a [5n + 6]… (13) b [8n + 1] = a [5n + 1] (n = 0,1,2…) b [8n + 2] = (-1/16 + -1 / 32) * a [5n] + (1/4 + 1/8 + 1/16 + 1/32) * a [5n + 1] + (1/2 + 1/4) * a [5n + 2] + (-1/8) * a [5n + 3] b [8n + 3] = (-1/8) * a [5n + 1] + (1/2 + 1/4 + 1/8) * a [5n + 2] + (1/4 + 1/32) * a [ 5n + 3] + (-1/32) * a [5n + 4] b [8n + 4] = (-1/64) * a [5n + 1] + (1/8 + 1/64) * a [5n + 2] + (1/2 + 1/4 + 1/8 + 1/16 + 1/32) * a [5n + 3] + ((-1/64) + (-1/32)) * a [5n + 4] b [8n + 5] = (-1/8) * a [5n + 2] + (1/2 + 1/8) * a [5n + 3] + (1/2 + 1/8) * a [5n + 4] + (-1/8) * a [5n + 5] b [8n + 6] = (-1/16 + -1 / 32) * a [5n + 3] + (1/2 + 1/4 + 1/8 + 1/16 + 1/32) * a [5n + 4] + (-1/8) * a [5n + 5] b [8n + 7] = (-1/32) * a [5n + 3] + (1/4 + 1/32) * a [5n + 4] + (1/2 + 1/4 + 1/8) * a [5n + 5 ] + (-1/8) * a [5n + 6] b [8n + 8] = (-1/8) * a [5n + 4] + (1/2 + 1/4) * a [5n + 5] + (1/4 + 1/8 + 1/16 + 1/32) * a [ 5n + 6] + (-1 / 16 + -1 / 32) * a [5n + 7] (14) In order to obtain the counts of the approximate expressions (9) to (14) as described above, the shift image data An operation for obtaining image data by adding each shift from 0 to the number of bits (6 bits in this embodiment) is called a shift operation.

Next, a hardware example of the interpolation processing unit 1.05 will be described in detail with reference to FIG. Figure 12
Vertical interpolation unit 1.0 that vertically interpolates the input effective display image data and enlarges the display on the dot matrix display.
5 is a detailed block diagram of FIG.

In the figure, 4.01 is an input section,
Digital image data output from the AD converter 1.03 is input. A control input unit 4.02 receives a control signal for controlling the interpolation processing unit 1.05 from the system control unit 1.91. A memory unit 4.02.01 stores the setting data set in the system control unit 1.91. Further, 4.02.02 is a setting supply unit that supplies the saved setting data to another processing apparatus.

Reference numeral 4.03 is a synchronization input section to which a clock and a synchronization signal are input. An output unit 4.04 is provided to the digital processing unit 1.4 to send the image data s1.04 and the synchronization signal cs.
Outputs 1.07. An output clock supply unit 4.05 determines the transfer rate at which the output unit 4.04 outputs image data. A vertical interpolation processing unit 4.06 performs digital processing on the input image data to increase horizontal lines. An interpolation control unit 4.07 controls the vertical interpolation processing unit 4.06.

In the above structure, the input section 4.01 is
Data signal line S1.03 output from the / D conversion unit 1.03
The image data input via the
The vertical interpolation processing unit 4.0 is synchronized with each signal input to
Supply to 6. Memory section 4.02 of control input section 4.02.
The setting data stored in 01 is the setting supply section 4.02.0.
2 to the interpolation control unit 4.07. And
Processing is performed based on the supplied setting data, and image data is sent from the output unit 4.04 to the switch means 1.06 in synchronization with the clock supplied by the output clock supply unit 4.05. When the vertical interpolation processing is not performed, the clock supplied from the synchronization input unit 4.03 is used to output the image data from the output unit 4.04 to the switch means 1.06.

FIG. 13 is a block diagram for explaining the details of the vertical interpolation processing unit 4.06 and the interpolation control unit 4.07 shown in FIG.

In the figure, 4.06.01 is a flip-flop (F) for synchronizing the image data with the synchronizing signal.
/ F) circuit, 4.06.02 is an input Fast In Fast Out (FIFO) memory that stores one horizontal line, 4.06.03
Is a calculation unit that performs calculation processing with the image data input using the interpolation coefficient. A switch unit 4.06.05 selects the output of the output FIFO memory 4.06.04 and transfers it to the switch unit 4.06.06. Switch part 4.
06.06 is through-passed data when the interpolation coefficient is 1, that is, when interpolation is not performed, or the switch unit 4.06.
One of the data input from 05 is selected.

Reference numeral 4.07.01 denotes an input FIFO control unit, which inputs the image data and the FIFO memory 4.
The data write timing and the data read timing to 06.02 are controlled. An output FIFO write control unit 4.07.02 controls the timing of the arithmetic unit 4.06.03 and the write timing of the FIFO memory 4.06.04. 4.07.03 is an output FIFO control unit,
It controls the read timing of the output FIFO memory 4.06.04. A display position detection unit 4.07.04 detects a display start position. An output display position correction unit 4.07.05 adjusts the timing of the image data and the synchronization signal output from the interpolation processing unit 1.05. Reference numeral 4.07.06 is an arithmetic control unit for controlling the index of each line.

In the above configuration, the input image data is synchronized in the signal of the input FIFO control section 4.07.01 in the F / F circuit 4.06.01 and the FIFO
The image data is transferred to the memory 4.06.02.

Each FIFO memory 4.06.02 is controlled by the input FIFO control unit 4.07.01 so that image data delayed by one horizontal line is sequentially transferred. Each calculation unit 4.06.03 has a calculation control unit 4.07.
Image data of the same horizontal column is input by a control signal from 06, and a vertical interpolation line is generated. The generated vertical interpolation line is stored in the FIFO memory 4.06.04 based on the signal from the output FIFO control unit 4.07.03. The stored image data is read by the signal from the output FIFO control unit 4.07.03, and is sent to the switch unit 1.06 via the switch unit 4.06.05 and the switch unit 4.06.06. Transfer image data. When the image data is transferred, a signal synchronized with the image data is generated and output from the output display position correction unit 4.07.05.

When the system control unit 1.91 determines that the number of lines of the input signal matches the number of lines of the display unit 1.5 as a result of measurement by the synchronization signal measuring unit 1.02, the switch unit By switching 4.06.06, the interpolation processing unit 1.05 does not perform the interpolation processing and outputs it as it is.

Also, the interpolation processing unit 4.06 according to the present embodiment.
13, since the FIFOs 4.06.02 and 4.06.04 and the operation unit 4.06.03 are configured as shown in FIG. 13, it is possible to interpolate up to twice the maximum number of lines by the interpolation processing in the vertical direction. By providing a plurality of such interpolation processing units 4.06, the number of lines that can be interpolated can be increased.

FIG. 14 is a block diagram showing a configuration of an arithmetic unit 4.06.03 for input image data.

In the figure, the exponent calculation unit 4.06.03.
01 receives the image data of each line from the F / F circuit 4.06.01 or the FIFO memory 4.06.02 and multiplies it by a predetermined exponent, and a 4-input adder 4.0.
The image data is transferred to 6.03.02 and added. The image data of the addition result is sent to the code processing unit 4.06.0.03, and if the calculation result is negative, the minimum value "00"
Change to (6bit, hexadecimal) and if it exceeds the maximum value, change to maximum value "3F" (6bit, hexadecimal).

FIG. 15 shows the exponentiation unit 4.06.03.01.
3 is a detailed block diagram of FIG.

In the same figure, input image data 1
A value from / 32 to 32/32 is created, and the 2's complement calculator 4.06.03a converts the image data of the preceding stage into a negative number. The selector 4.06.03b is a two's complement calculator 4.06.0.
Image data passed through 3a and image data not passed through are selected, and the image data is transferred to the 4-input adder 4.06.03.02.

Next, an OSD (on-screen display) display that displays necessary information on the screen of the display unit 1.5 to facilitate various adjustment processing by the operator is shown in FIGS. 16, 17, and 18. 19 and FIG. 20 showing enlargement of the character size by the display control device of the present embodiment.
Will be described with reference to.

When the system control section 1.91 detects an OSD display request from the key input processing by the operator, etc., the system control section 1.91 informs the OSD control section 1.93 of the OSD display request based on this request.
By transferring information such as display start position (horizontal and vertical), display pattern, font size, display color, blinking presence / absence, and space between fonts, OSD display as shown in FIGS. 16 to 19 is performed. 16 to 19 are diagrams showing OSD display examples of this embodiment.

First, FIGS. 16 and 17 show examples of OSD display of the menu screen by the adjustment item selection process in the key input process described later. 16 and 23 show a case where the language selection is selected as the setting item as an example. FIG. 16 shows a display example in which the background of characters is not a watermark, and the selected language (LAN
(GUAGE) items are distinguished from other items by using a different color from the background of the other items or by blinking. Further, FIG. 17 shows a display example in which the background of characters is a watermark. In this case, only the background of the selected item is colored instead of the watermark.

FIG. 18 shows an example of the OSD display when the language selection (LANGUAGE) is selected by the adjustment item selection processing described later on the menu screen shown in FIG. In this case, since it is a two-person selection type, every time the UP and DOWN keys are pressed, English (ENG
LISH) and Japanese (JAPANESE) are selected alternately.

FIG. 19 shows an OSD display example when brightness adjustment is selected in the menu selection. In this case, the adjustment value is changed step by step with the UP and DOWN keys, and there are, for example, 255 step setting values.
When the D display level is 10 levels, the OSD display level is also increased / decreased by 1 every time the set value is increased / decreased by about 25.

FIG. 20 is a diagram for explaining the control of the font size in the OSD display. When the composite video signal s1.06 such as NTSC / PAL and the YC separated video signal s1.08 are displayed, the OSD display data s
1.18 is a field / frame converter that converts data in feed units into data in frame units.
At 24, it is vertically doubled in size. Further, the horizontal interpolation processing unit 1.25 enlarges the size in the horizontal direction to double the size. When it is finally displayed on the display unit 1.5, the same data is displayed in two lines in the vertical direction, which means that the data is enlarged to twice the size in the vertical direction. , Vertically enlarged to 4 times size. Therefore, the font size used for OSD display is double the size in the horizontal direction and the size in the vertical direction, so that the font size in the horizontal direction and the vertical direction is displayed on the display unit 1.5. You can

On the other hand, when the computer input signal s1.01 is displayed, the OSD display data s1.18 is displayed in the switch section 1.06 as the computer input signal s1.0.
It is switched to 1 and output. At this time, the same data is read four times in order to read at the same clock speed as the computer input signal s1.01. for that reason,
It will be enlarged four times in the horizontal direction. Therefore, by using a font size of 1 times in the horizontal direction and 4 times in the vertical direction as the font size used for the OSD display, the same 4 times as the above case is used in both the horizontal direction and the vertical direction on the display unit 1.5. The size font can be displayed.

The user can adjust the vertical direction by adjusting the key input.
The double drive and the single drive can be selected, and the system control unit may detect this change and control the OSD control unit. Here, when the double drive in the vertical direction is selected, a double size font is used in the vertical direction.

Further, since the computer image signals are all sampled in the horizontal direction to 1280 pixels (at the time of A / D conversion), the horizontal size is the same in all display modes. Therefore, by reading only the OSD data four times and switching by the switch unit 1.06, it is possible to combine them in a proper size. Further, the same size and the same timing are always input to the digital processing unit 1.4.

FIG. 21 is a diagram showing a list of OSD display items at the time of displaying video signals and computer signals. In the display control device according to the present embodiment, the OSD display of different contents is performed at each display as shown in FIG. These display contents are held in the system control unit. The OSD control unit holds the font data.

Therefore, in the display control device of this embodiment, OSD display of different font sizes, different read clock speeds, and different display contents is performed during video signal display and computer signal display.

The OSD control unit 1.93 is a switch unit 1.23 in the case of a video input signal such as NTSC.
In case of computer input signal, switch part 1.06
Image data s1.10 or s1.04 is switched to the OSD data s1.18 and output.

The switch unit 1.32 uses the system control unit 1.9 based on the operator's selection by the key input processing described later.
Video input signal s such as NTSC which is switched by 1
1.13 and the computer input signal s1.05 are switched and transferred to the digital processing unit 1.4.

Here, the key input processing from the operator will be described in detail with reference to the flow charts of FIGS. 22 to 25 and FIG. 26 showing an example of keys for receiving key input from the user. 22 to 25 are flowcharts for explaining the key input processing in this embodiment. Also,
FIG. 26 is a diagram showing an overview of the key operation panel in this embodiment.

The system controller 1.91 operates in step S11.
In 01, a key scan is performed on the key matrix section 1.92. In step S1102, it is determined whether or not there is a key input as a result of the key scan, and if there is no key input, the key input processing is immediately terminated. Otherwise, if there is a key input, step S110.
Go to 3.

In step S1103, it is determined whether the detected key input is the TV / PC switching key (KEY1) in FIG. 26. If it is the TV / PC switching key, TV / PC switching in step S1104 is performed. PC mode switching processing is performed. This TV / PC switching processing consists of 1, switching control of the switch unit 1.3, setting of TV / PC switching information to the interpolation processing unit 1.03, and OSD display of TV / PC switching information. After the TV / PC mode switching process ends, the key input process ends. In step S1105, the detected key input is the volume UP key (KE
If it is the volume UP key, the volume UP processing of step S1106 is performed.
This volume UP processing consists of: 1, volume UP setting 2 to the audio signal processing unit 1.72, and OSD display of the updated volume. After the voice UP process ends, the key input process ends.

In step S1107, it is determined whether or not the detected key input is the volume down key in FIG. 25, and if it is the volume down key, step S1.
The volume DOWN processing of 108 is performed. The volume DOWN processing includes: 1, volume DOWN setting 2 to the audio processing unit 1.72, and OSD display of the updated volume. After the voice DOWN processing ends, the key input processing ends.

In step S1109, the clear key (KEY8) and the set key (KEY5) shown in FIG.
At the same time, it is determined whether or not the key has been continuously pressed for a certain period or longer. The reset process is as follows: 1. Read the factory default settings from the non-volatile memory 1.94, set the color decoder 1.22 2. Read the factory default settings from the non-volatile memory 1.94, Set to audio signal processing unit 1.72 3, read out factory default settings from non-volatile memory 1.94, and set to clock generator 1.04 4. From nonvolatile memory 1.94 to factory default The setting value is read out and the interpolation processing unit 1.05 performs the setting process. After the reset process ends, the key input process ends.

In step S1111, it is determined whether the detected key input is the menu key (KEY4), and if it is the menu key, step S11.
Proceed to 12. Otherwise, when any key other than the above, that is, any one of the set key, the UP key, the DOWN key, and the clear key is detected, the key input process is immediately terminated without doing anything. In step S1112, it is determined whether the TV mode is the current TV mode or the PC mode. In the TV mode, the process proceeds to step S1113, and in the PC mode, the process proceeds to step S1128.

In step S1113, the operator selects the setting item while looking at the menu screen. Refer to the flowchart of FIG.
Alternatively, the processing of 1128 will be described.

In step S1501, the OSD display is performed with the previously selected item selected. Step S1
At 502, waiting is performed until a key is input from the operator. In step S1503, the keys input by the operator are the TV / PC switching key, the volume UP key, and the volume DO.
It is determined whether or not the key is any one of the WN keys (that is, any one of KEY1 to KEY3), and if so, the process returns to step S1502 without doing anything.

If none of KEY1 to KEY3, the process proceeds from step S1503 to step S1504. In step S1504, it is determined whether the key input by the operator is the menu key (KEY4), and if so, the process ends. If not, the process proceeds to step S1505.

In step S1505, it is determined whether or not the key input by the operator is the set key (KEY5), and if so, the setting item is determined in step S1514, and the flow advances to step S1114 or step S1129.

The key entered by the operator is the set key (KE
If not Y5), the process proceeds to step S1506. In step S1506, it is determined whether the key input by the operator is the clear key (KEY8), and if so, the selection item is initialized in step S1507, and the process returns to step S1501. If the entered key is not the clear key, the process advances to step S1508.

In step S1508, it is determined whether or not the operator has pressed the clear key and the set key at the same time for a certain period of time or more, and if so, it is determined that a reset request has been made, and the reset processing of step S1509 is performed. The process ends. If not, step S
Proceed to 1510.

In step S1510, it is determined whether the key entered by the operator is the UP key (KEY6). If so, the selection item is set to the previous item in step S1511, and then the process returns to step S1501. If not, it proceeds to step S1512.
In step S1512, the key entered by the operator is DOW.
It is determined whether or not the key is the N key (KEY7). If so, the selection item is changed to the next item in step S1513, and the process returns to step S1501.

If the keys are not all the above keys, nothing is done and the process returns to step S1501. Therefore, step S
The key input process ends only when the menu key is input in 1504 or the reset request is issued in step S1508, and only when the key input by the operator in step S1505 is the set key, step S1113 in FIG. Alternatively, the process of step S1128 ends.

Returning to FIG. 23, in step S1114,
It is determined whether the adjustment item selected in step S1113 is language selection. If the language is selected, the language selection process of step S1115 is performed. In step S1116, it is determined whether or not the selected process is the input selection. If it is the input selection, the input selection (composite signal input / YC separated signal input) process of step S1117 is performed. In step S1118, it is determined whether or not the selected process is the sound quality selection, and if it is the sound quality selection, the sound quality selection process of step S1119 is performed. Step S1
At 120, it is determined whether or not the selected process is contrast adjustment, and if it is brightness adjustment, the brightness adjustment process of step S1123 is performed. In step S1124, the selected process performs the saturation adjustment process. In step S1126, the selected process performs the hue adjustment process. Otherwise, if a process other than the above is selected, the process ends immediately.

The language selection process of step S1115 will be described below with reference to FIG. Step S16
In 01, the language selection screen is displayed by OSD, and step S1
At 602, the operation waits until the operator inputs a key. In step S1603, it is determined whether the key input from the operator is the TV / PC switching key, the volume UP key, or the volume DOWN key (that is, any of KEY1 to KEY3), and if so, Then, the process returns to step S1602. If not, the process proceeds to step S1604. In step S1604, the key input from the operator is the menu key (KEY4).
Alternatively, it is determined whether the key is the set key (KEY5), and if so, the menu selection processing 11
Return to 13. If not, step S160
Proceed to 6.

In step S1606, it is determined whether the key input from the operator is the clear key (KEY8). If so, step S160
In step 7, the setting value is returned to the setting value when the processing was started, and the process returns to step S1601. If not, the process proceeds to step S1608. In step S1608, it is determined whether or not the operator has pressed the clear key and the set key at the same time for a certain period of time or more, and if so, it is determined that a reset request has been made, and step S160
The reset process 9 is performed, and the language adjustment process and the key input process are completed. If not, the process proceeds to step S1610.

In step S1610, it is determined whether or not the key input from the operator is the UP key. If yes, in step S1611 the set value is set to the previous item or the set value is set. UP. And
The procedure returns to step S1601. If it is not the UP key in step S1612, the process proceeds to step S1612.
In step S1612, the key input from the operator is DO.
It is determined whether the WN key is pressed, and if so, the setting value is set to the next item or the setting value is DOWN in step S1613.

If it is determined in step S1612 that the key is not the DOWN key, the key input from the operator is none of the above keys, and nothing is done in step S160.
Return to 1.

Input type selection processing in step S1117, sound quality selection processing in step S1119, step S1
121 contrast adjustment processing, step S1123 brightness adjustment processing, step S1125 saturation adjustment processing,
The same processing is performed for the hue adjustment processing in step S1127.

On the other hand, in step S1128, step S
In the same manner as in 1113, in the PC mode, a process of selecting a setting item through the menu screen is selected. In step S1129, it is determined whether the selected process is language selection, and if it is language selection, the language selection process of step S1130 is performed. If not, the process proceeds to step S1131. In step S1131, it is determined whether or not the selected process is the sound quality selection. If the selected process is the sound quality selection, the sound quality selection process of step S1132 is performed. if,
Otherwise, it proceeds to step S1133.

In step S1133, it is determined whether or not the selected process is γ selection. If it is γ selection, the γ selection process of step S1134 is performed.
If not, it proceeds to step S1135. In step S1135, it is determined whether or not the selected process is gradation selection. If it is gradation selection, the gradation selection process of step S1136 is executed. If not, it proceeds to step S1137. In step S1137, it is determined whether the selected process is phase adjustment. If it is phase adjustment, the phase adjustment process of step S1138 is performed. If not, it proceeds to step S1139. Step S113
At 9, it is determined whether the selected processing is position adjustment. If it is phase adjustment, step S1
Display position adjustment processing of 140 is performed. If not, the process proceeds to step S1141.

In step S1141, it is determined whether or not the selected process is DPMS adjustment.
If it is an adjustment, DPMS in step S1142
Perform adjustment processing. If not, step S1
Proceed to 143. In step S1143, it is determined whether or not the selected process is model setting, and if it is model setting, the model setting process of step S1144 is performed. Otherwise, if a process other than the above is selected, the key input process is immediately terminated. The system control unit 1.91 performs the above determination processing, OSD display control, various adjustment selection processing control, and the like.

Next, the processing performed in the digital processing section 1.4 will be described with reference to FIG. FIG. 27 is a block diagram showing the configuration of the digital processing unit in this embodiment. The video input signal s1.13 such as NTSC and the computer input signal s1.05 switched and input in the switch unit 1.32 are subjected to γ correction processing and gradation adjustment processing in the contrast adjustment unit 5.01.

The above gamma correction processing will be described with reference to FIG. FIG. 28 is a diagram for explaining the γ correction processing when γ = 2.2, 8-bit input, 8-bit output. When the input data is, for example, a, the output data is also a when γ = 1.0, but when γ = 2.2, the output data is b (<a), and the contrast of An image is obtained.

Next, the gradation adjustment processing will be described with reference to FIG. FIG. 29 is a diagram for explaining the gradation adjustment processing in this embodiment. When the gradation adjustment processing is not performed, an output value that is linear with respect to the input value is taken as in the characteristic of 100% in FIG. On the other hand, when the 50% gradation adjustment is performed, the output values for the input data from 0 to 64 and 192 to 255 are pasted to 0 and 255, respectively, and the input data between them are as shown in FIG. Changes to twice as much as the input data. An image with higher contrast can be obtained by decreasing the value of the gradation adjustment (lowering%). The adjustment value in the γ correction process and the gradation adjustment is selected by the operator in the above-described key input process, and is set in the contrast adjustment unit 5.01 by the system control unit 1.91.

Gamma-corrected and tone-adjusted data s
The halftone processing unit 5.02 displays, for example, ED
Halftone processing such as (error diffusion) method and dither method is performed.

The motion detecting section 5.04 steals the display data before the halftone processing, detects a line that has changed by a certain value or more, and detects this result as the system control section 1.91.
Transfer to. System control unit 1.91 is memory 5.03
Among the frame display data stored in, the only line display data in which the motion is detected is output to the display control unit 5.05 together with the line address data.

The display control unit 5.05 displays the line display data on the display 5.06 at the vertical position designated by the line address data.

Next, the power supply unit 1.8 will be described. The power supply unit 1.8 supplies power to the composite video signal processing unit 1.2, the computer image signal processing unit 1.1, the digital processing unit 1.4, and other units. The power supply unit 1.8 is controlled by the system control unit 1.91 to turn on / off the composite video signal processing unit 1.2, the computer image signal processing unit 1.1, and the digital processing unit 1.4.

In the above configuration, the control procedure relating to the OSD control will be summarized below. FIG. 30 is a block diagram showing the configuration of OSD control in this embodiment.

As described above, the input composite analog image signal is converted into RGB by the color decoder 1.22.
Image signal s1.10. When displaying this image signal, the video signal that can be displayed on the display unit 1.5 by the field / frame conversion unit 1.24 and the horizontal interpolation processing unit 1.25 is selected by the switch unit 1.23. Generate the signal s1.13. And switch part 1.3
By selecting the video signal s1.13 by selecting 2, the composite analog image signal input to the display unit 1.5 is displayed. Here, the switch unit 1.31 outputs the signal cs1.1 indicating that the video signal is selected.
0 is selected and this is output as cs1.11. The digital processing unit 1.4 recognizes that the video signal s1.13 is selected by this cs1.11, and the display unit 1.
5 is driven in a driving mode suitable for the video signal s1.13.

As described above, when the OSD display is performed while the video signal s1.13 is being displayed, the following control is performed. O from system controller 1.92
Upon receiving the SD display command, the OSD control unit 1.93 recognizes that the video signal is being displayed by the signal cs1.11. As a result, the OSD control unit 1.93 outputs the OSD data s1.18 for displaying the video signal. The switch unit 1.23 converts the OSD data s1.
Switch the selection to 18. As a result, the OSD data s1.
The field 18 is subjected to predetermined processing by the field / frame conversion unit 1.24 and the horizontal interpolation processing unit 1.25 and supplied as a video signal s1.13 to the display unit for display.

On the other hand, the computer CRT signal s1.01
In the case of displaying, the computer input signal s1.04 sampled and interpolated according to the number of pixels of the display section is selected by the switch section 1.06. The display signal s1.05 output from the switch unit 1.06 is selected by the switch unit 1.02 and input to the digital processing unit 1.4. Also, a signal cs1.0 indicating a computer input display
7 is selected by the switch unit 1.31 and input to the digital processing unit 1.4. The digital processing unit 1.4 recognizes that it is the display of the computer input signal by the signal cs1.11, and displays it on the display unit 1.5 in synchronization with the computer input signal. Here, the display control device
As described above, the digital processing unit 1.4 drives the display unit 1.5 at the display speed suitable for each display mode, because it supports a plurality of computer-input resolutions (display modes).

As described above, the computer input signal s1.
When the display by OSD is performed while 05 is displayed, the following control is performed. System control unit 1.92
OSD control unit 1.93 which received an OSD display command by
Recognizes from the signal cs1.11 that the image currently displayed is a computer input signal. As a result, the OS
D1.93 outputs OSD data s1.18 for computer input display. The switch unit 1.06 switches the selection from the computer input signal s1.04 to the OSD data s1.18 and outputs it as the display signal s1.05. OSD data is displayed on the display unit 1.5 by selecting the display signal s1.05 with the switch unit 1.32.
Since the digital processing unit 1.4 drives the display unit 1.5 at the synchronous speed for computer display, in the present embodiment, the same pixel is read four times at the time of reading from the OSD control unit 1.93. As described above, the image is taken out and is magnified four times in the horizontal direction.

As described above, according to this embodiment, in each display state such as a composite video signal and a computer CRT signal having different resolutions and display speeds (synchronization speeds), it is possible to display OSD data which facilitates various adjustment operations. It becomes possible to do it appropriately.

Further, the OSD data is held for each display such as the composite video signal and the computer CRT signal, and the OSD data is selected and displayed according to each display state. It can be obtained and the operability is improved.

Further, since the circuit for displaying a video signal and the circuit for displaying a computer signal are used for the OSD, it is not necessary to provide a display processing circuit dedicated to the OSD, and the circuit structure can be made compact.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0145]

As described above, according to the present invention, the OSD can be appropriately displayed in correspondence with the display states having different image resolutions and dot clocks.

[0146]

[Brief description of drawings]

FIG. 1 is a block diagram of a display control device 10 according to an embodiment.

FIG. 2 is a block diagram showing a detailed control configuration of a synchronization signal measuring unit.

FIG. 3 is a diagram showing a data storage state in a FIFO memory in the synchronization signal measuring unit.

FIG. 4 is a diagram showing a data storage state of a register of a synchronization signal measuring unit.

FIG. 5 is a flowchart showing a procedure for determining a display mode in this embodiment.

FIG. 6 is a block diagram showing a configuration of a clock generation unit 1.04.

FIG. 7 is a block diagram showing a configuration of a counter in the frequency divider.

FIG. 8 is a diagram showing an operation timing chart of the 1/2 frequency division output level switch 3.15.

FIG. 9 is a diagram illustrating an interpolation processing method in the present embodiment.

FIG. 10 is a diagram illustrating an interpolation processing method in this embodiment.

FIG. 11 is a diagram illustrating an interpolation processing method in this embodiment.

FIG. 12 is a detailed block diagram of a vertical interpolation unit 1.05 which vertically interpolates the input effective display image data and performs enlarged display on a dot matrix display.

13 is a block diagram illustrating details of an interpolation processing unit 4.06 and an interpolation control unit 4.07 illustrated in FIG.

FIG. 14 is a diagram illustrating a calculation unit for input image data, 4.06.03.
3 is a block diagram showing the configuration of FIG.

FIG. 15 is a detailed block diagram of an exponent calculation unit 4.06.03.01.

FIG. 16 is a diagram showing an example of OSD display according to the present embodiment.

FIG. 17 is a diagram showing an example of OSD display according to the present embodiment.

FIG. 18 is a diagram showing an OSD display example of the present embodiment.

FIG. 19 is a diagram showing an example of OSD display according to the present embodiment.

FIG. 20 is a diagram illustrating control of a font size in OSD display.

FIG. 21 is a diagram showing a list of OSD display items during video signal display and computer signal display.

FIG. 22 is a flowchart illustrating a key input process according to this embodiment.

FIG. 23 is a flowchart illustrating a key input process according to this embodiment.

FIG. 24 is a flowchart illustrating a key input process according to this embodiment.

FIG. 25 is a flowchart illustrating a key input process according to this embodiment.

FIG. 26 is a diagram showing an overview of a key operation panel in the present embodiment.

FIG. 27 is a block diagram showing the configuration of a digital processing unit in this embodiment.

FIG. 28 is a diagram illustrating a γ correction process when γ = 2.2, 8-bit input, and 8-bit output.

FIG. 29 is a diagram illustrating a gradation adjustment process according to the present embodiment.

FIG. 30 is a block diagram showing the configuration of OSD control in this embodiment.

[Explanation of symbols]

 10 Display control device 1.1 Computer image signal processing unit 1.2 Composite video signal processing unit 1.3 Switch unit 1.4 Digital processing unit 1.5 Display unit 1.7 Audio processing unit

Claims (9)

[Claims] 1. A display control device having a plurality of types of display modes for displaying a plurality of types of image signals corresponding to different resolutions and dot clocks, the determining means determining a display mode of an image signal being displayed. A selecting means for selecting the OSD data to be displayed based on the display mode judged by the judging means; and an input means for switching and inputting the OSD data selected by the selecting means with the image signal currently being displayed. An output unit that outputs the OSD data input by the input unit in the display mode of the image signal. 2. The OSD data has a font size and shape corresponding to each display mode, and the selection means selects the OSD data so that a character size and shape of an appropriate size can be obtained in each display mode. The display control device according to claim 1, wherein the display control device is a display control device. 3. The display control device according to claim 2, wherein the font size and shape are determined based on a dot clock speed in each display mode and an input speed of OSD data by the input unit. 4. The OSD data has a display content corresponding to each display mode, and the selecting means selects the OSD data having a display content suitable for each display mode. The display control device described. 5. The plurality of types of display modes include at least a first display mode for displaying a composite video signal and a second display mode for displaying a computer CRT signal. The display control device according to 1. 6. When the OSD data is displayed in the first display mode, the output means receives the input OSD data.
The display control apparatus according to claim 5, wherein the data is subjected to the same processing as the processing performed on the RGB signal obtained by converting the composite video signal, and is output. 7. A display device, which displays an image based on a signal output by the display control device according to claim 1. Description: 8. The display device according to claim 7, wherein the image display is performed on a dot matrix display. 9. A display control method for displaying in a plurality of types of display modes for displaying a plurality of types of image signals corresponding to different resolutions and dot clocks, and determining the display mode of the image signal being displayed. Determining step, selecting step for selecting OSD data to be displayed based on the display mode determined in the determining step, and inputting the OSD data selected in the selecting step by switching with the image signal currently being displayed. A display control method comprising: an input step; and an output step of outputting the OSD data input in the input step in a display mode of the image signal.