JPH0955656A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce lock up time by receiving a control voltage to operate or release the power-down mode so as to short-circuit a capacitor or to release the short-circuit and applying a voltage for the purpose to a power-down mode terminal. SOLUTION: A voltage from a terminal C receiving a control voltage is fed to a voltage controlled oscillator VCO 5 as a power supply voltage via a ripple filter 6 and the effect of power noise onto the VCO 5 is reduced by the ripple filter 6. A power-down mode terminal PD connects both terminals of a capacitor 9 with a transistor(TR) 8, and a voltage applied to a terminal C is fed to a base of the TR 8. Then when a voltage applied to the terminal C reaches a low voltage, the TR 8 is controlled to be conductive to discharge charges in the capacitor 9 rapidly via the Tr 8 resulting that a level of the terminal PD is zero. When a voltage fed to the terminal C is high, the TR 8 is nonconductive to release the short-circuit of the capacitor 9, resulting that the level of the terminal PD reaches a terminal voltage of the capacitor 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit,
More specifically, a PLL capable of operating in a power down mode
Regarding the circuit.

[0002]

2. Description of the Related Art A conventional PLL circuit capable of reducing the consumption of a power storage battery, that is, a power down mode operation is shown in FIG.
Was configured as shown in. That is, the phase comparator 1
Further, the PLL integrated circuit 3 including the programmable divider 2 is provided with the power supply terminal Vcc and the power down mode terminal PD, and the terminal C to which the control voltage for the power down mode operation and the power down mode operation release is applied,
In the power down mode operation, for example, a voltage of 0 V is applied to apply a voltage of 0 V to the power down mode terminal PD, and when the power down mode operation is released, a voltage of, for example, 3 V is applied to the terminal C to power down mode terminal P.
By applying a voltage of 3V to D, the power down mode operation and the power down mode operation cancellation of the PLL circuit are controlled.

Through the terminal M, the power source terminal Vcc is always 3
The voltage of V is applied, and during operation in the power down mode, the power supply terminal Vcc is supplied to each circuit that constitutes the PLL integrated circuit 3 including the phase comparator 1 and the programmable divider 2.
The PLL integrated circuit 3 including the phase comparator 1 and the programmable counter 2 holds the phase comparison output terminal Do in the high impedance state while cutting off the application of the voltage from the The voltage from the power supply terminal Vcc is applied to each of the circuits constituting the circuit to control the PLL integrated circuit 3 in the operating state. In FIG. 2, reference numeral 7 indicates the internal resistance of the PLL integrated circuit 3 as viewed from the power supply terminal Vcc and the power down mode terminal PD.

On the other hand, the phase comparison output output from the phase comparison output terminal Do of the phase comparator 1 of the PLL integrated circuit 3 is supplied to the loop filter 4, and the output from the loop filter 4 is used as a frequency control voltage in a voltage controlled oscillator ( VCO) 5 to cause the VCO 5 to oscillate at a frequency based on the output voltage of the loop filter 4, supply the oscillation output of the VCO 5 to the programmable divider 2, and divide the frequency separately supplied to the programmable divider 2. The frequency of the oscillation output of the VCO 5 is divided by the division ratio based on the data, and the phase comparator 1 compares the phase with the input signal.

On the other hand, the voltage from the terminal C is applied as a power supply voltage to the VCO 5 through the ripple filter 6 composed of the transistor 61, the resistor 62 and the capacitor 63,
The ripple filter 6 influences the power supply noise on the VCO 5.
I am trying to reduce it.

[0006]

However, in the conventional PLL circuit as described above, the rise of the VCO at the time of canceling the operation in the power down mode is higher than that of the PLL integrated circuit 3 because of the presence of the ripple filter and the like. It will be delayed in time. Therefore, for the voltage waveform shown in FIG. 3A applied to the terminal C when the power down mode operation and the power down mode release operation are repeated, the frequency control voltage of the VCO supplied through the loop filter. Has a waveform of period t as shown in FIG.
There was a problem that it fluctuated over 1.

This will be explained in more detail. FIG. 4 which is applied to the terminal C when the power down mode operation is released.
As for the waveform of the output voltage of the ripple filter with respect to the voltage shown in (a), its rise is delayed with time as shown in FIG. 4 (b). For this reason, the PLL integrated circuit starts its operation immediately after the terminal C becomes high potential, but the VCO is delayed by the time determined by the time constant of the ripple filter, as shown in FIG.
Oscillation is started as shown in. However, even if the VCO starts to oscillate, the voltage applied to the transistor or the like that constitutes the VCO gradually increases from a value lower than the value in the steady state, so that the parameter of the transistor fluctuates and the oscillation frequency fluctuates. To do.

Therefore, since the VCO does not oscillate immediately after the voltage of the terminal C becomes high potential, the phase comparison output from the phase comparison output terminal Do fluctuates in the rising direction,
After that, the VCO starts oscillating, the phase comparison output from the phase comparison output terminal Do fluctuates so as to be pulled in to the set frequency after the oscillation starts, and becomes a steady state after a certain time. That is, the PLL integrated circuit locks after the time. FIG.
(D) shows the waveform of the phase comparison output from the phase comparison output terminal Do.

That is, when the operation of the power down mode is released, the operation of the PLL integrated circuit and the oscillation of the VCO are not synchronized, and the latter is delayed, so that it takes time for the frequency control voltage of the VCO to stabilize. There is a problem that the lockup time of the PLL circuit is delayed.

It is an object of the present invention to provide a PLL circuit which shortens the lockup time when the power down mode operation is released.

[0011]

A PLL circuit according to the present invention includes a PLL integrated circuit in which a power down mode operation and a power down mode operation cancellation are switched based on a voltage level applied to a power down mode terminal, In a PLL circuit including a ripple filter that receives a control voltage at a level according to down mode operation and cancellation of power down mode operation, performs ripple removal of the control voltage and supplies the voltage as a power supply voltage to a voltage controlled oscillator, A capacitor connected between the mode terminal and the ground and a control voltage for operating the power down mode are received to short-circuit the capacitor and the voltage for the power down mode operation is substantially supplied to the power down mode terminal. Applied and receiving the control voltage to release the power down mode operation Characterized by comprising a switch means for applying a voltage for is released substantially power-down mode operation releasing a short circuit of the capacitor to the power-down mode terminal.

According to the PLL circuit of the present invention, the short circuit of the capacitor is released by the switch means when the control voltage for canceling the power down mode operation is applied during the power down mode operation. However, the capacitor is connected between the power down mode terminal and the ground, the capacitor is charged through the internal resistance of the PLL integrated circuit, and the potential of the power down mode terminal is based on the time constant between the internal resistance and the capacitor. And the potential of the power-down mode terminal is delayed and reaches the potential for canceling the power-down mode operation, and the PLL integrated circuit is controlled to the operating state. During this period, the output voltage from the ripple filter which has received the control voltage for canceling the power down mode operation increases and the voltage controlled oscillator starts the oscillation operation.
In this case, the oscillation frequency at the start of oscillation of the voltage controlled oscillator is the frequency based on the output voltage of the loop filter during the power down mode operation, and the lockup time of the PLL circuit becomes short.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a PLL circuit according to the present invention will be described. FIG. 1 shows a PLL according to the present invention.
It is a block diagram which shows one Embodiment of a circuit.

In one embodiment of a PLL circuit according to the present invention, a PLL integrated circuit 3 including a phase comparator 1 and a programmable divider 2 is provided with a power supply terminal Vcc and a power down mode terminal PD, and a power down mode operation is in progress. At times, a voltage of 0 V, for example, is applied to the power down mode terminal PD, and when the power down mode operation is canceled, for example, 3 V is applied to the power down mode terminal PD.
Is applied to control the power down mode operation and the power down mode operation release by the voltage applied to the power down mode terminal PD.

The power supply terminal Vcc is always connected to the terminal 3 through the terminal M.
The voltage of V is applied, and during operation in the power down mode, the power supply terminal Vcc is supplied to each circuit that constitutes the PLL integrated circuit 3 including the phase comparator 1 and the programmable divider 2.
The PLL integrated circuit 3 including the phase comparator 1 and the programmable counter 2 holds the phase comparison output terminal Do in the high impedance state while cutting off the application of the voltage from the The voltage from the power supply terminal Vcc is applied to each of the circuits that configure the PLL circuit 3 to control the PLL circuit 3 in the operating state. In FIG. 1, reference numeral 7 indicates the internal resistance of the PLL integrated circuit 3 viewed from the power supply terminal Vcc and the power down mode terminal PD.

The phase comparison output output from the phase comparison output terminal Do of the phase comparator 1 of the PLL integrated circuit 3 is supplied to the loop filter 4, and the output from the loop filter 4 is supplied to the VCO 5 as a frequency control voltage. The VCO 5 is caused to oscillate at a frequency based on the output voltage of the loop filter 4, and the oscillation output of the VCO 5 is programmable by the programmable divider 2.
The frequency of the oscillation output of the VCO 5 is divided by a frequency division ratio based on the frequency division ratio data separately supplied to the programmable divider 2, and the phase comparator 1 compares the phase with the input signal.

The voltage from the terminal C to which the control voltage is applied is applied as a power supply voltage to the VCO 5 via the ripple filter 6 so that the ripple filter 6 reduces the influence of the power supply noise on the VCO 5. The ripple filter 6 is constructed similarly to the conventional case shown in FIG. The configuration described above is the same as the conventional example. Therefore,
A voltage of 0V is applied to the terminal C during the power down mode operation, and 3 is applied to the terminal C when the power down mode operation is released.
The voltage of V is applied, and the ripple-removed voltage of 3V is applied to the VCO 5 as a power supply voltage, and the VCO oscillates.

On the other hand, the power-down mode terminal PD is grounded via the capacitor 9, both ends of the capacitor 9 are connected by the transistor 8, and the voltage applied to the terminal C is applied to the base of the transistor 8 and applied to the terminal C. When the applied voltage becomes a low potential, the transistor 8 is controlled to be in the ON state, the charge of the capacitor 9 is rapidly discharged through the transistor 8 and 0 V is applied to the power down mode terminal PD, and conversely to the terminal C. When the applied voltage becomes 3 V, the transistor 8 is turned off to release the short circuit of the capacitor 9 and the terminal voltage of the capacitor 9 is applied to the power down mode terminal PD.

The operation of the present embodiment configured as above will be described. When the power down mode operation and the power down mode release operation are repeatedly executed, the voltage having the waveform shown in FIG. 3A is applied to the terminal C. At the rising edge of the voltage shown in FIG.
The transistor 8 is controlled to the off state, and the potential of the capacitor 9 gradually increases based on the time constant of the internal resistance 7 and the capacitor 9 as shown in FIG.

Based on the increase in the potential of the capacitor 9, the potential of the power-down mode terminal PD is changed from the time when the potential of the terminal C becomes 3V to the time t2 (t) as shown in FIG. 3 (d).
1> t2) and reaches 3V with a delay, and the oscillation frequency of the VCO 5 is controlled by the frequency control voltage shown in FIG. As is clear from comparison between FIG. 3B and FIG. 3D, the lockup time is shortened because the PLL integrated circuit 3 operates after the VCO 5 operates.

This will be described in more detail with reference to FIG. As shown in FIG. 4A, when the potential of the terminal C is set to 3 V and the power down mode release is instructed, the output voltage waveform of the ripple filter 6 is delayed as shown in FIG. 4B. As a result, the oscillation of the VCO 5 is started with a time delay based on the time constant of the ripple filter 6 as shown in FIG. On the other hand, as the potential of the terminal C rises, the transistor 8 is controlled in the off state, the capacitor 9 starts to be charged and the potential of the capacitor 9 increases, and the potential of the power down mode terminal PD is shown in FIG. 4 (e). , The power-down mode operation is released, and PL
The L integrated circuit 3 is in the operating state.

However, the VCO 5 has already started oscillating at the time when the power down mode operation is released, and when the VCO oscillates, the high impedance of the phase comparison output terminal Do in the power down mode operation causes the VCO 5 to start oscillating. The oscillation voltage of the VCO 5 is started by receiving the maintained output voltage of the loop filter 4 as a frequency control voltage, and this oscillation frequency is close to the original oscillation frequency, that is, the oscillation frequency immediately before shifting to the power down mode operation. is there.

As a result, the VCO 5 oscillates from a frequency close to the frequency set in the PLL circuit immediately before shifting to the power-down mode operation, and the fluctuation of the output from the phase comparison output terminal Do is shown in FIG. As shown in (f), it is a short time, and the lockup time is shortened.

On the other hand, in the above-mentioned conventional case,
When the power-down mode operation is released, the PLL integrated circuit 3 is activated in time before the start of oscillation of the VCO 5, so that the output voltage of the loop filter held before the transition to the power-down mode operation is VCO5. Since the VCO 5 does not operate even when it is applied to, the output from the phase comparison output terminal Do fluctuates greatly, so that it takes time to converge, and the lockup time is as shown in FIG. It will be longer during the period of t3.

[0025]

As described above, the PL according to the present invention is
The L circuit has the effect of shortening the lockup time when the power down mode operation is released. Therefore, the repetition cycle of the power down mode operation and the power down mode operation cancellation can be shortened, and the consumption of the storage battery power supply can be suppressed. Further, when the PLL circuit according to the present invention is used in a wireless communication device, the lockup time can be short, so that the beginning portion of the received signal can be prevented from being interrupted.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a PLL circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional PLL circuit.

FIG. 3 is a schematic diagram for explaining the operation of one embodiment of the PLL circuit according to the present invention.

FIG. 4 is a schematic diagram for explaining the operation of one embodiment of the PLL circuit according to the present invention.

[Explanation of symbols]

 1 Phase Comparator 2 Programmable Divider 3 PLL Integrated Circuit 4 Loop Filter 5 VCO 6 Ripple Filter 7 Internal Resistance 8 Transistor 9 Capacitor Vcc Power Supply Terminal PD Power Down Mode Terminal

Claims (1)

[Claims] 1. A PLL integrated circuit in which a power down mode operation and a power down mode operation cancellation are switched based on a voltage level applied to a power down mode terminal, and a power down mode operation and a power down mode operation cancellation. In a PLL circuit including a ripple filter that receives a control voltage of a different level, removes the ripple of the control voltage, and supplies the voltage as a power supply voltage to a voltage controlled oscillator,
The capacitor connected between the power-down mode terminal and the ground and the control voltage for operating the power-down mode are short-circuited to substantially reduce the voltage for the power-down mode operation. Switching means for applying a voltage to the terminals and for applying a control voltage for canceling the power down mode operation to cancel the short circuit of the capacitor and substantially apply the voltage for canceling the power down mode operation to the power down mode terminals. And a PLL circuit.