JPH095112A - Absolute encoder - Google Patents

Abstract

PURPOSE: To obtain an absolute encoder in which the complicatedness of the input operation of the origin is eliminated by a method wherein, on the basis of the absolute position width of the virtual origin which is set by making use of an arbitray position on a code plate as the virtual origin, binary data is shifted by a portion by which the origin has been moved. CONSTITUTION: A head 11 is arranged so as to face a code plate 10 which obtains a signal indicating an absolute position, the head 11 can move the code plate 10 relatively, and a relative movement amount to the code plate 10 is detected. The head 11 detects respective patterns, and it outputs an incremetal signal S1 and an absolute signal S2. The output terminal of an A/D converter 12 and the output terminal of a conversion table 14 which is converted into a binary code are connected to the input port of a CPU 16 which performs a correction computing operation. In addition, the output terminal of a push switch 15 which sets an arbitrary position on the code plate 10 as the virtual origin is connected to the input port. The CPU 16 corrects data on the present position of the code plate 10 by data on a virtual origin position by means of a prescribed expression, and the deviation between the origin position of an absolute encoder and that of a machine tool is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute encoder for obtaining a signal indicating an absolute position.

[0002]

2. Description of the Related Art An absolute encoder is a numerical control device (hereinafter referred to as "N" as position detecting means for detecting an absolute position.
C)) and the like. In order to output the absolute position information, the conventional absolute encoder uses a code plate on which a pattern for obtaining a signal indicating the absolute position is formed, and moves relative to this code plate to form on the code plate. The detection unit that detects the light that has passed through the patterned pattern and the electric capacitance that changes according to the movement of the pattern, and the signal that converts the detection signal detected by this detection unit into a signal that indicates the absolute position using a conversion table or the like. And a processing unit.

An absolute encoder normally outputs absolute position information as binary data by using a conversion table of the signal processing unit, but in the conventional absolute encoder, the binary data is only for a specific section. The origin position on the board was fixed.

[0004]

Since the conventional absolute encoder is constructed as described above, when the code plate of the absolute encoder is attached to the machine tool, it is located between the origin of the machine tool and the origin of the absolute encoder. It was necessary to input information regarding the offset amount of the above into the NC.

In order to perform this information input work, it is necessary for an operator who attaches the code plate to the machine tool to acquire operation techniques for the machine tool and NC only for setting the origin. It was one of the factors that made the work difficult.

Further, the input operation itself to the NC is also complicated. For example, after moving the code plate of the absolute encoder to the origin of the machine tool, the power of the NC is turned on and the screen for setting the origin is displayed on the NC. After displaying it on the display, I had to go through multiple steps to set the parameters. Having multiple steps in this way has the meaning of protection from erroneous operation in which the origin is mistakenly moved during operation.In this sense, it is effective, but it is extremely effective in terms of origin setting work efficiency. It was inefficient.

Further, as another origin setting method, there is a method in which the distance from the machine origin of the machine tool to the current position of the code plate is measured using other measuring means, and the measured value is input to NC. Also in this method, similarly to the above-mentioned method, the measured value is input through a plurality of steps, and the work efficiency of origin setting is extremely poor.

The present invention has been made in view of the above circumstances, and its problem is that the origin of the machine tool and the origin of the absolute encoder can be made coincident with each other only by the operation on the absolute encoder side, and the origin input of the absolute encoder can be performed. An object of the present invention is to provide an absolute encoder that can eliminate the complexity of work.

[0009]

In order to solve the above-mentioned problems, an absolute encoder according to the invention of claim 1 is a code plate having an absolute pattern made from an n-th order binary cyclic random number sequence, and a relative to the code plate. In an absolute encoder including detection means for detecting movement and signal processing means for converting a detection signal from the detection means into binary data representing an absolute position, an arbitrary position of the code plate is set as a virtual origin. An origin setting means and a correction calculation means for shifting the binary data by the amount of the origin moved by the origin setting means based on the absolute position information of the virtual origin set by the origin setting means.

In the absolute encoder of the second aspect of the present invention, the origin setting means is a switch.

In the absolute encoder of the third aspect of the present invention, the origin setting means is a potentiometer.

In the absolute encoder of the present invention as defined in claim 4, the correction calculation means includes binary data generation means for generating binary data, storage means for storing the binary data generated by the binary data generation means, and the origin. Address changing means for changing the address for storing the binary data generated by the binary data generating means in the storage means based on the absolute position information of the virtual origin set by the setting means.

[0013]

In the absolute encoder according to the invention of claim 1, the virtual origin is set at an arbitrary position on the code plate by the origin setting means, and the correction calculation means makes the origin based on the absolute position information of the virtual origin. The binary data representing the absolute position is shifted by the amount of movement of the origin by the setting means. This makes it possible to arbitrarily change the correspondence between the output data from the code plate and the binary data, and by operating only the absolute encoder side,
The origin position on the code plate can be matched with the origin position of the machine tool.

In the absolute encoder of the second aspect of the present invention, the origin can be easily set by the switch.

In the absolute encoder of the third aspect of the present invention, the origin can be easily set by the potentiometer.

According to another aspect of the absolute encoder of the present invention, the address changing means causes the storage means to store the binary data generated by the binary data generating means on the basis of the virtual origin position information set by the origin setting means. Change the address. As a result, the correspondence between the output data from the code plate and the binary data can be arbitrarily changed with a simple configuration.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an absolute encoder according to the first embodiment of the present invention. In FIG. 1, a head (detection means) 11 is arranged to face a code plate 10 on which an incremental pattern for obtaining a signal indicating an absolute position and an M-series absolute pattern are formed, and the head 11 corresponds to the code plate 10. It is relatively movable, and the amount of relative movement with respect to the code plate 10 is detected. The head 11 detects each pattern and outputs an incremental signal S1 and an absolute signal S2. 2 with 90 ° phase difference as the incremental signal S1
The output terminal of the head 11 that outputs the phase pseudo sine wave signal is A
It is connected to the input terminal of the / D converter 12. The output terminal of the head 11 that serially outputs the M-sequence signal S2 as an absolute signal is connected to the input terminal of the shift register 13 for performing serial-parallel conversion. The output terminal of the shift register 13 is connected to the input terminal of a conversion table (signal processing means) 14 for converting into a binary code composed of an EEPROM or the like. Output terminal of A / D converter 12 and conversion table 14
The output terminals of are connected to the input ports of the CPU (correction calculation means) 16 for performing correction calculations.

A push switch (origin setting means) for setting an arbitrary position of the code plate 10 as a virtual origin.
The output terminal of 15 is connected to the input port of the CPU 16.

At the output port of the CPU 16, a non-volatile memory 17 such as a rewritable EEPROM for storing the set virtual origin data and the system program of this embodiment, a numerical controller (NC), etc. Interface circuit 18 of FIG. The output port of the CPU 16 is connected to the control terminal of the head 11 to output a control signal to the head 11.

Next, the operation of the absolute encoder of this embodiment will be described with reference to the flow chart of FIG.

First, the absolute encoder of this embodiment is powered on, the CPU 16 and its peripheral circuits are initialized, the system program and the output pulse number P of the absolute encoder of this embodiment, and the arbitrary number set by the previous operation. Data such as data X indicating the origin position is read from the non-volatile memory 17 to the CPU 16 (step S501).

Next, the CPU 16 issues a command to the head 11 to read the current position of the code plate 10, and the code plate 1
The incremental signal S1 read from the 0 incremental pattern is converted into a digital signal by the A / D converter 12 and input to the CPU 16.

The M-sequence signal S2 read from the absolute pattern of the code plate 10 is converted into a parallel signal by the shift register 13, and the conversion table 1
After being converted into binary data in 4, the data is input to the CPU 16. The CPU 16 synthesizes the input incremental signal S1 and M-sequence signal S2 to obtain absolute position data X indicating the absolute position of the absolute encoder (step S502).

Subsequently, the CPU 16 corrects the current position data X of the code plate 10 of the absolute encoder according to the set virtual origin position data Xz as shown in the following equation, and sets the origin between the absolute encoder and the machine tool. The position shift is eliminated (step S503).

In case of linear encoder: Y = X−Xz In case of rotary encoder: Y = X if X ≧ Xz
-Xz If X <Xz, Y = P + X-Xz Here, X is absolute position data indicating the current position of the code plate 10 of the absolute encoder, Y is absolute position data indicating the corrected current position, and Xz is the previous setting. If the virtual origin is not set in the virtual origin position data, Xz = 0,
P is the number of output pulses of the rotary coder.

The absolute position data Y corrected in step S503 is output to the interface circuit 18 (step S504) and output to the NC side via the interface circuit 108 (step S505).

FIG. 3 is a flowchart showing an interrupt operation (Interrupt) when a new virtual origin is set. To set the virtual origin in this embodiment, when the code plate 10 is located at a position desired to be the virtual origin,
The push switch 15 is operated. Then, the interrupt signal is input from the push switch 15 to the CPU 16,
The interrupt sequence of FIG. 3 is started.

First, the CPU 16 reads the current position of the code plate 10 as in step S502, updates the value of Xz by using the read absolute position data as absolute position data Xz indicating a new origin (step S506), The updated value is stored in the non-volatile memory 17 so as to be valid after the next power-on (step S507).

Next, the correction operation of the virtual origin will be described with reference to FIGS. 4 and 5. FIG. 4A is for a linear encoder, and is a diagram showing the positional relationship between the signal detected by the head 11 and converted by the CPU 16 into binary data indicating the absolute position and the code plate 10. It is assumed that, for example, absolute position signals from 100 to 500 are associated with the code plate 10.

In this state, the interrupt operation described above is performed, and the push switch 15 is moved to the position 300 of the code plate 10.
Is operated and is designated as the virtual origin position.

The CPU 16 performs the calculation according to the above equation, and the data of 100 to 500 are shifted by the value 300 of the virtual origin position, respectively, and as shown in FIG. Converted to data.

In this way, according to the virtual origin position,
This means that the binary data in one section has been converted into the binary data in another section.

When the absolute encoder is a rotary encoder, as shown in FIG. 5, for example, when the output pulse number P is 401 and the binary data position 200 is designated as the virtual origin position, the CPU 1
6, the binary data associated with each position of the code plate 10 is changed as shown in FIG. 5 (a) to FIG. 5 (b) until the set virtual origin position. This means that the origin position of the code plate 10 has moved.

According to the absolute encoder of the first embodiment, the correspondence relationship between the output data from the code plate 10 and the binary data indicating the absolute position can be changed arbitrarily, and the simple operation on the absolute encoder side makes it possible. Since the origin position on the code plate 10 can be matched with the origin position of the machine tool, the burden of the origin setting work can be significantly reduced.

Next, a second embodiment of the present invention will be described.

FIG. 6 is a block diagram showing an absolute encoder according to the second embodiment of the present invention. In this embodiment, the conversion table itself for converting the M-sequence signal S2 into binary data is rewritten at the time of setting the virtual origin, so that the CPU 16 does not need to calculate the above equation. 6, the same components as those of the embodiment of FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

The output terminal of the shift register 13 is connected to the input terminal of the multiplexer 22 that switches the input signal, and is also connected to the input terminal of the M sequence generation circuit 19 that generates the M sequence signal. M series generation circuit 1
The output terminal of 9 is connected to the input terminal of the multiplexer 22. The output terminal of the multiplexer 22 is connected to the address input terminal of the conversion table 14, while the output terminal of the binary generation circuit (binary signal generation means) 20 (composed of a binary counter) for generating binary data is the conversion table (storage means). ) 14 data input terminals. The output terminals of a controller (address changing means) 21 for generating control signals for controlling the operations of the conversion table 14, the M-sequence generation circuit 19, the binary generation circuit 20, and the multiplexer 22 are connected to the control terminals of the respective circuits. There is.

FIG. 7 is a circuit diagram showing a specific structure of the M-sequence generation circuit 19. In FIG. 7, the controller 21
Output signals hold, load, shift of the above and the 4-bit bid parallel M-sequence signals D0, D1, D2, D3 output from the shift register 13 are input to AND circuits N1 to N12 provided in parallel, respectively. It The output terminals of the AND circuits N1 to N12 are three-input OR
It is connected to each input terminal of the circuits O1 to O4. The output terminals of the OR circuits O1 to O4 are connected to the input terminals D of the D flip-flop circuits D1 to D4, respectively. Output terminals Q of D flip-flop circuits D1 to D4
From the address signals A3 to A0 input to the address input terminals of the conversion table 14 via the multiplexer 22.
Are output respectively. The output terminal Q of the D flip-flop circuit D1 is connected to one input terminal of the AND circuit N1 and one input terminal of the exclusive OR circuit E, respectively. Output terminal Q of D flip-flop circuit D2
Are connected to one input terminal of the AND circuits N3 and N4 and the other input terminal of the exclusive OR circuit E, respectively. The output terminal of the exclusive OR circuit E is connected to one input terminal of the AND circuit N12.

Next, the operation will be described. FIG. 8 is a flowchart showing the operation of the absolute encoder of the second embodiment. In the flowchart of FIG. 8, the same operations as those in the flowchart of FIG. 2 are designated by the same step numbers, and the description thereof will be omitted. The operation of the second embodiment differs from the operation of the first embodiment only in the operation of rewriting the conversion table 14 in step S508, and therefore step S508 will be described below.

First, the operation of the M-sequence generation circuit 19 will be described. FIG. 9 is a timing chart showing an example of the operation of the M-sequence generation circuit 19 shown in FIG. As shown in FIG. 9, the output signals A3 to A0 of the M-sequence generation circuit 19 can be controlled by the output signals hold, load, and shift from the controller 21 according to the M-sequence signals D3 to D0.
Depending on the length of the shift signal, it starts at 0001 and becomes 0
010, 0100, 1001, ..., 1010 can be sequentially generated.

Table 1 in FIG. 10 shows the converted values before rewriting when the M-sequence signal has 4 bits, and Table 2 in FIG. 10 shows the converted values after rewriting. Code plate 1 when the operator operates the push switch 15 to set the virtual origin
It is assumed that the M-sequence signal at the position of 0 is 0001. In this case, the output of the conversion table 14 before rewriting is 10
However, after rewriting, the position of the code plate 10 becomes the virtual origin, so that a binary code of 0000 (binary data) is output from the conversion table 14 according to Table 2. The conversion table 14 is rewritten as follows.

When the push switch 15 is pressed, the CP
An interrupt signal is input to the U 16 and the controller 21 from the push switch 15. Then, the controller 21 to which the interrupt signal is input outputs the control signal to the multiplexer 22, the M-sequence generation circuit 19, the conversion table 14, and the binary generation circuit 20. The multiplexer 22 is
Switching is performed by a control signal from the controller 21, and the M-sequence generation circuit 19 is connected. As a result, the M-sequence signal S2 from the shift register 13 is output to the M-sequence generation circuit 19, and the M-sequence generation circuit 19 outputs the output signal A3 based on the M-sequence signal S2 from the shift register 13.
.About.A0 are generated, and the output signals A3 to A0 are generated.
Is output to the conversion table 14 via the multiplexer 22. Further, the conversion table 14 is the controller 21.
Write mode (write mode) by control signal from
Switch to.

Further, the CPU 16 uses the push switch 1
When the interrupt signal from 5 is input, a read command for the current position is issued to the head 11, and the head 11 outputs the M series signal of the code plate 10 to the shift register 13. The M-sequence signal S2 from the shift register 13 is read into the M-sequence generation circuit 19 (hold = L, l in FIGS. 7 and 9).
oad = H, shift = L). M sequence generation circuit 19
Sequentially generates M-sequence signals based on the read M-sequence signals (hold = L, load in FIGS. 7 and 9).
= L, shift = H). The M-sequence generation circuit 19 sequentially generates M-sequence signals, and at the same time, the binary generation circuit 20
However, binary data is generated as, 000,0001,0010,0011 .... M series generator 19 is M
The timing for generating the series signal and the timing for the binary generation circuit 20 to generate the binary data are controlled by the control signal output from the controller 21. In this way, in the case of 4 bits, the contents of the conversion table 14 are rewritten from Table 1 to Table 2 in FIG.

After the conversion table 14 is rewritten, the conversion table 1 is converted by the control signal from the controller 21.
4 switches to the read mode (read mode), and the multiplexer 22 switches to input the M-sequence signal S2 from the shift register 13 directly to the conversion table 14.

When the push switch 15 is not pressed (normal time), the M series signal from the shift register 13 is output to the multiplexer 22 and the conversion table 14.

According to the absolute encoder of the second embodiment, the conversion table 14 itself is rewritten at the time of setting the virtual origin, so that the CPU 16 does not need to calculate the above equations, and the output data from the code plate 10 can be simply structured. And the binary data can be arbitrarily changed.

Incidentally, in the above-described embodiment, each element constituting the hardware may be replaced with another element exhibiting the same function. For example, a potentiometer may be used as the origin setting means instead of the push switch 15. Good.

[0049]

As described above, according to the absolute encoder of the first aspect of the invention, the correspondence between the output data from the code plate and the binary data can be arbitrarily changed, and only the absolute encoder side can be changed. Since the origin position on the code plate can be matched with the origin position of the machine tool by a simple operation of, the load of the origin setting work can be greatly reduced.

According to the absolute encoder of the second aspect of the present invention, the origin can be easily set by the switch.

According to the absolute encoder of the third aspect of the present invention, the origin can be easily set by the potentiometer.

According to the absolute encoder of the fourth aspect of the present invention, the binary data generated by the binary data generating means is stored in the storage means by the address changing means based on the virtual origin position information set by the origin setting means. Since the address to be stored is changed, the correspondence between the output data from the code plate and the binary data can be arbitrarily changed with a simple structure.

[Brief description of drawings]

FIG. 1 is a block diagram showing an absolute encoder according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the first embodiment.

FIG. 3 is a flowchart showing an interrupt operation of the first embodiment.

FIG. 4 is an explanatory diagram showing an example of a result of a virtual origin correction operation of the linear encoder of the first embodiment.

FIG. 5 is an explanatory diagram showing an example of a result of a virtual origin correction operation of the rotary encoder of the first embodiment.

FIG. 6 is a block diagram showing an absolute encoder according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing an M-sequence generation circuit of a second embodiment.

FIG. 8 is a flowchart showing the operation of the second embodiment.

FIG. 9 is a timing chart showing the operation of the M-sequence generation circuit.

FIG. 10 is a diagram showing a table of conversion values before rewriting and a table of conversion values after rewriting when the M-sequence signal has 4 bits.

[Explanation of symbols]

 10 Code Board 11 Head 14 Conversion Table 15 Push Switch 16 CPU 19 M Series Generation Circuit 20 Binary Generation Circuit 21 Controller

Claims (4)

[Claims] 1. A code plate having an absolute pattern made from an n-th order binary cyclic random number sequence, a detection unit for detecting relative movement with respect to the code plate, and a binary signal representing an absolute position of a detection signal from the detection unit. In an absolute encoder provided with a signal processing means for converting into data, an origin setting means for setting an arbitrary position of the code plate as a virtual origin, and absolute position information of the virtual origin set by the origin setting means. An absolute encoder comprising: a correction calculation unit that shifts the binary data by an amount corresponding to the movement of the origin by the origin setting unit. 2. The absolute encoder according to claim 1, wherein the origin setting means is a switch. 3. The absolute encoder according to claim 1, wherein the origin setting means is a potentiometer. 4. The correction calculation means includes binary data generation means for generating binary data, storage means for storing the binary data generated by the binary data generation means, and the virtual data set by the origin setting means. The absolute encoder according to claim 1, further comprising: an address changing unit that changes an address for storing the binary data generated by the binary data generating unit in the storage unit based on absolute position information of the origin. .