JPH09510592A - Data decryption device for pay television signal receiving system - Google Patents

Abstract

(57) Summary A receiver of satellite-broadcast signals, including high-definition television signals, includes a device for decrypting encrypted signals (FIG. 1: 12-26). When unencrypted "plaintext" signal information that does not need to be decrypted is received, the plaintext information is provided to the decryption device. The normal cryptanalysis operation is changed so that the input plaintext information can be directly obtained as the plaintext information at the output of the cryptanalysis device. The bit selection network (628; S ₁ , ..., S ₈ ) associated with the cryptanalysis function (f (R, K)) of the cryptanalyzer is not a lookup table, but a combinatorial logic network (18,628). To use.

Description

Detailed Description of the Invention     Data decryption device for pay television signal receiving system                            Background of the Invention   FIELD OF THE INVENTION The present invention relates to the field of digital video signal processing, and in particular, for example in broadcasting satellites. For decrypting television signals received from transmission channels such as You.   Subscriber video and television such as cable and satellite / reception systems The service restricts access to paid subscribers only, so it uses control words or "keys". Is often used to encrypt various broadcast services such as video and audio. . The encryption process on the transmitter side is performed according to various techniques. Some of the above techniques Is "American National Standard Data Encryption Algorithm" ANSI X3.92-1 981 and "Information Systems-Data Encryption Algorithms-Modes of Operation" It is described in American National Standard "ANSI X3.106-1983".                            Summary of the invention   At the receiver of a signal that may contain encrypted information, decryption of the receiver The bit selection processor associated with the decryption function of the processor is Improved behavior by utilizing combinatorial logic networks rather than uptables Indicates the work speed.                          Brief description of the drawings   In the drawing:   FIG. 1 is a block diagram of a decryption device according to the principles of the present invention.   2 is a satellite video signal transmitter including the decryption device of FIG. 1 in the transport unit of FIG. It is a block diagram of a transmission and reception system.   FIG. 3-13 is a block diagram to help understand the decryption operation of the device shown in FIG. It is a chart and a table.   14 and 15 are state diagrams and related diagrams of the input main state machine of the system of FIG. 1, respectively. It is a figure showing the logical table.   16 and 17 are state diagrams of the output state machine of the system of FIG. 1 and related figures, respectively. It is a figure showing a logic table.                            Detailed description   The decryption device shown in FIG. 1 is based on the "American national standard data encryption algorithm". Digital data as described in ANSI X3.92-1981. Data encryption / decryption algorithm, which is a standard algorithm for encrypting and decrypting Operates in accordance with Gorythm (DEA). In particular, the device of FIG. Data encryption algorithm-American national standard "ANSI" for modes of operation   "Electronic Codebook Mode" as described in X3.106-1983. Works with. In this example, the received input data stream is a pay TV Encryption, including data from five sources or "services" associated with the When the decryption device provides 10 decryption keys, 2 for each service Is assumed. By alternately using two keys for each service, Periodic change of the unused key is the current cipher with the other key. The advantage is that the reading process can be performed without interruption. According to the DEA standard, each key , A 56 bit decryption bit and 8 parity check bits It's a word. In the disclosed system, 8 parity bits are used. Not.   The input signal is either encrypted ciphertext data or unencrypted plaintext data. Either may be included. According to the DEA standard, "plain text" has a meaning, A clear text or signal that can be read and used and that The standard algorithm This is a process of converting a ciphertext into a plaintext using a computer. Input signal is 8 bits / byte Is a parallel 8-byte data stream. Input 8-byte shift register 10 Receives input data of 1 byte at a time according to the clock. Clock signal The numbers are not shown to simplify the figure. Thus, each 8 bits (1 byte) Since it is put into the register 10 in synchronization with the clock during the clock cycle, Eight clock cycles are required to completely fill star 10 with 64 bits You. Elements 12, 14, 16 and 18 form a decryption processor. Input cash register The loading of the star 10 is done by the decryption processor from the previous input cycle. End while executing the data decoding algorithm on 64 bits of data. (Less than, The standard data decoding algorithm (described) consists of 16 iterations. , 8 clock cycles are needed to fill register 10, decryption The clock speed of processor elements 12, 14, 16 and 18 depends on the clock of the input register. It is twice as fast as the lock speed, that is, the speed to receive the next 8 bytes of input data. Twice as fast as   The decryption operation is under the control of the state machine 20, eg a microcontroller. . The state machine 20 restores the data after the remaining 64 bits of the input data are obtained. It may be programmed to put the system on standby during encryption, or Make the system proceed with the decoding of new data immediately after the decoding of the previous data has finished. It may be programmed. The state machine 20 starts the input control signal (START). And output control (CONTROL) signal in response to bypass (BYPASS) I do.   The bypass signal is a plaintext data of the input that is not scrambled Normal decryption behavior should be modified to keep the same format at the output of the reading network That is, that the decryption process should be bypassed. State machine 20 The output control signal from these devices outputs this bypass instruction to the decryption processing elements 12 and 16. Force state machine 2 Communicate to 2. To bypass the decryption operation for plaintext data input, The instrument 20 causes the “I” register 12 to receive the load from the input register 10, and Dista 12 does 16 times (in "idles") without repeating Wait an interval to achieve the decoding iterations of (described with respect to FIG. 3), then The contents of register 12 are sent to output register 26. Of the input of the output register 26 The final data replacement (reverse replacement) must be the reverse of the initial replacement of the register 12 input. Since it is predetermined that the plaintext output data from the register 26 Matches the Riki plain text data. Thus, the decryption bypass function is the decryption processing circuit. Circuits related to the use of switching networks to switch plaintext data around the network and The advantage is realized that does not depend on the complexity of the interface.   The input ciphertext / plaintext digital signal received and processed by the above system is The data component to be encoded and the related header component that stores the data identification information. It is in the form of a data packet that contains. The header is not encrypted. To unit 20 The input bypass control signal is detected by the input signal processing circuitry (not shown). It is generated according to the control bit included in the header of the received data packet. Uni As described above, the control signal from the computer 20 is repeated 16 times in the plaintext bypass mode. During that time, information is included that causes the register 12 to be left in a blank state. Unit 2 The control signal from 0 causes the multiplexer in register 12 to output the output of unit 10. Further information is included to allow selection of either the force or the output of unit 18 for processing. I have. The start signal input to the unit 20 is input to the unit 20 in front. Generated by signal processing circuitry (not shown), the unit 20 receives 8 bytes data packet is detected, and after 8 bytes are detected (input register 10 is filled), the output of the input register 10 to the register 12 Information to be loaded is generated on the control signal line. In addition, this information is Block The output state machine 22 is informed that the data processing pipeline has been entered, and the data block After completing the 16-step iterative decryption process as described above, It is output from the shift register 26 under control.   14 and 15 show the state diagram of the state machine 20 and the associated logic table, respectively. I have. When the start signal is received, the unit 20 first Encryption by loading 64-bit input data from the Initialize the decryption system. Unit 20 then performs 16 iterations of decryption. Unit 20 then waits for the next start signal. Cryptanalysis process In anticipation of the last start signal still appearing at the end of Go to the state "End-Wait" and wait until the start signal disappears, then 20 waits for the next start signal. 19 states, as shown in this example Only a 5-bit data word between 10001 and 11111 The 13 states involved are unused and do not appear.   16 and 17, the state diagram of output state machine 22 and the associated logic are shown. When the control signal is received, the signal indicates that the data is being decoded or the data is Data is bypassed through the device in bypass mode. Unit 22 Then moves to the ready state. The state machine 20 sends a signal indicating the end of the decryption process. Then, the output state machine 22 has 8 bytes (state S₁To S₈) Is counted. Uni But 22 Follow it by ending the count at R8. Cryptanalysis at the end of the count If the reading is not finished yet, the unit 22 moves to the ready state and decrypts. Wait until the process is completed. End signal while states R1 through R8 are in use If received, the coun At the end of the session, the state machine 22 immediately moves on to the delivery of the next 8 bytes.   The code word substitution defined by the DEA standard is equivalent to the units 12, 14, 1 of FIG. Proper placement of data bits on the data link interconnecting 6 and 18 It is realized by. The decryption bit selection function performed by the unit 18 is a combination. Advantages can be obtained by implementing a logic network. Especially the bit selection machine Noh is realized by a combinational logic arrangement of 6-input and 4-output, as described below. May be. By using combinatorial logic to perform the bit select function, For example, hardware economy and using ROM-based lookup tables It is conceivable that a faster operation of the selection function can be obtained than the above.   The output state machine 22 outputs the next 64-bit sequence by the unit 12-18. Processed and another 64-bit sequence is obtained by the input register 10. While simultaneously, the plaintext output of 1 byte at a time is output through the register 26. Can be transmitted to Le. The output state machine 22 indicates that the next 64 bits are not completely decrypted. The last byte of a given sequence is output register 2 6 may be programmed to wait until communicated by The device 22 may immediately begin delivering the next 64-bit plaintext output sequence. Yes. Thus, the state machine 22 and the output register 26 have a delayed or non-uniform data Waits when they occur at different rates, or the unit 22 is Shift the data block out of register 26 so that it will appear when it occurs You. The output state machine 22 indicates that new data has been processed but has not been fully decrypted. If not, or the new data has been decrypted and passed through register 26. And waiting for delivery to the output channel, new data is decrypted. Determine if it is being processed by the reading network. This is, for example, The control from unit 20 indicating that the block was decrypted after 16 iterations. You It is determined according to the signal information.   When there is plaintext input information that is not encrypted in "bypass" mode The input plaintext information is transferred from the input register 10 to the decryption processor unit 12 and And the decryption processor unit transmitted to the output register 26 via 12 and 18 show the modified behavior in this mode. In particular, the block of FIG. The output of unit 18 corresponding to 622 is used during 16 repeating cycles No decryption is performed during that iteration cycle.   In the bypass mode, the register 12 does nothing during the bypass mode as follows. It is realized by putting it in a non-conforming state. 64-bit input is accepted in bypass mode When received, the decryption processor and the state machine 20 determine the decryption operation mode and the actual state. Starts in a qualitatively similar way. The data is a permutation of the bit positions as above It is transferred from the shift register 10 to the register 12. 16 iterations of decryption At, the right half of register 12 gets the previous left half of register 12, The left half of the star 12 acquires the output of the combinational logic circuit 18. But bypass In mode, there is only one iteration. In this single bypass iteration, The right half of the register 12 acquires the left half before the register 12, and the left half of the register 12 Gets the previous right half of register 12. The register 12 is the output register 26. Maintains its value until it is ready to receive data from register 12. Regis The data 12 maintains its value by transmitting the output to the input at each clock.   The DEA data encryption / decryption algorithm performed by the device of FIG. For more specific information, refer to the DEA publication "American National Standards Data Encryption Algorithms." Mu ", based on American National Standard X3.92-1981. The encryption process is essentially the reverse of the encryption process described in detail below.   The data encryption / decryption algorithm is under the control of a 64-bit key. It is designed to encrypt and decrypt 64-bit data blocks. Recovery Encryption uses the same key that was used for encryption, but the decryption process The schedule for addressing key bits has been changed so that I have.   The block to be encrypted undergoes an initial permutation "IP" and then a complex key-dependent Substituent IP which is the inverse of the initial replacement^-1Receive. Key-dependent Is defined in terms of the encryption function "f" and the key schedule function "KS". You. The calculation and encryption operation will be described below. The following notation makes sense below. It is convenient to understand. Given two blocks L and R of bits In this case, LR indicates a block consisting of L bits followed by R bits. this The linkage is cohesive, so for example B₁, B₂. . . B₈Is B₈A bit of I ... . . Similarly, B₂Followed by a bit B₁A block of bits Show.   The encryption calculation is shown in FIG. 64 bits of input block to be encrypted 1 is given in Table 1 of FIG. 4 before being received by register 12 of FIG. Receive the initial replacement IP as obtained. The replaced input has bit 58 of the input As the first bit, bit 50 as the second bit, and so on. As the last bit. The permuted input block is then Input into the complex key-dependent calculations described below. Above called "preceding output" The output of the calculation then undergoes the permutation given in Table 2 of FIG. 5, which is the inverse of the initial permutation. . Thus, the output of the algorithm makes bit 40 of the preceding output the first bit Bit 8 of the preceding block, and so on. Bit 25 is the last bit of the output. Where done with the input of register 12 Period replacement relocates the wiring that connects the output of unit 10 to the input of unit 12. It is done by doing. Alternatively, this can be done by using logic networks. Can be. At the input of the output register 26 The reverse permutation performed is likewise realized.   The above calculation inputs the replaced input block to produce the preceding output block. Use as force. Except for the final block permutation, the computation is a 32-bit block. The operation is performed on two blocks, a lock block and a 48-bit block. 16 iterations of a set of operations involving the computation of the cryptographic function f to generate a block of It is composed of For example, if 64 bits of the input block to the iteration The input block consists of a block L and a 32-bit block R that follows. Consider the case shown as LR. 48-bit K selected from a 64-bit key , The output L'R 'of the iteration on the input LR is     L '= R     R '= L + f (R, K) (Formula 1) In the above example, “+” is a modulo 2 of 1 bit. Indicates addition.   As mentioned above, the input of the first iteration of the calculation is the permuted input block. If L'R 'is the output of the 16th iteration, then R'L' is the previous output block. is there. At each iteration, a different block K in the key bits is called 64 KEY. Selected from the key of bits. It is selected in response to a control signal from unit 20. An optional 56 bit shift register 16 is used. Especially shift register 16 then shifts the 56 bits of the activated key to 1 or 2 positions for each iteration. Shift by two, as shown by the function "K" at the output of the shift register 16. 48 bits are selected at the same time. In the case of the above example, between the units 16 and 18 48 bits are selected by appropriately configuring the wiring bus. Key lock An example of a tool is the above-mentioned "American National Standard Data Encryption Algorithm" ANS IX3.92-1981. Explain the calculation iteration in more detail . KS is an integer in the range 1 to 16 as input Take "n" and a 64-bit block KEY, and output the bit from KEY as an output. 48-bit block K, which is the permuted selection of_n   K_n= KS (n, KEY) (Equation 2) If it is a function that generates_nIs 48 distinct bit positions in the KEY Defined by a bit within. Block used in the nth iteration of Equation 1 above Block K defined by equation 2_nTherefore, KS Called. As described above, the replaced input block is represented by LR. L and R are husbands L_n-1And R_n-1And K is K_nL₀And R₀L respectively And R, L_nAnd R_nAre represented by L'and R ', respectively. That is, n is 1 to 16 When in the range of   L_n= R_n-1   R_n= L_n-1+ F (R_n-1, K_n) (Formula 3) It is. Leading output is R₁₆L₁₆It is. The key schedule KS is based on the DEA publication "A Merica National Standard Data Encryption Algorithm "American National Standard X3.92- Required for the above algorithm, as described in more detail in 1981. K_n16 values are generated.   Applied to the preceding output block during the decryption operation performed by the apparatus of FIG. Reverse replacement IP^-1(Final replacement in FIG. 1) is the initial replacement IP applied to the input. The opposite is true. From Equation 1,   R = L '   L = R '+ f (L', K) (Equation 4) Is obtained. Therefore, to perform the decryption, the block cipher is The same block of key bits K that was used during encryption is encrypted The same algorithm is used for encrypted messages, noting that it is used during decryption. It only has to be applied to the aging block. This concept has the following formula:   R_n-1= L_n   L_n-1= R_n+ F (L_n, K_n) (Equation 5) , Where R₁₆L₁₆Is the replaced input block for the decoding computation. And L₀R₀Is the preceding output block. That is, as the replaced input R₁₆L₁₆For the decryption computation on₁₆Is used for the first iteration, K_FifteenIs 2 Used for the second iteration, and so on, for K₁Is used for the 16th iteration. In this regard, the permutation performed at the transmitter / cryptographic device is the receiver / decryptor device. Note that it is the reverse of the permutation performed on the device. Thus, the darkness of Figure 1 The initial permutation (IP) of the decryptor is the corresponding reverse permutation performed by the cryptographic device. .   The 16-step iterative process (FIG. 3) requires the combinational logic bit selection network 18 of FIG. Contains the calculation of 16 key-dependent cryptographic functions f (R, K) performed by You. f (R, K) is actually a decryption function in the context of the decryption device of FIG. Need to understand that. The decryption function is the encryption performed by the transmitter / encryption device. It is the opposite of the conversion function. FIG. 6 is a complementary detailed view of circuitry 18. See FIG. In addition, each calculation consists of a 32-bit block “R” designated by the number 610, This is performed for the 48-bit block “K” indicated by the numeral 616. Block R is half of the input 64-bit data block, K is 64 bits It is a block of 48 bits selected from the key of. Block R is block R And K match the length of block K when combined by unit 626 So that the function "E" executed by unit 612 causes 48 bits (block 614). As mentioned above, for each iteration, there are 48 key bit differences. Block K is a 64-bit key (shifted) according to a predetermined schedule Is selected (replaced) from.   The combinatorial logic bit selection network 628 essentially forms the basis of the encryption / decryption function. A plurality of unique selection functions S to form₁,. . . S₈Including No. Each selection function S₁,. . . S₈6 received from the exclusive OR logic network 626 Generate unique combinations of the four output bits in response to the input bits. That is, Each selection function uses one original set of bits instead of another set of bits. No. The replacement of bits 6 to 4 complies with the DEA standard. The original bi that was replaced Whether the operation was performed at the transmitter / encryptor or the receiver / decryptor Depending on, either plaintext bits or encrypted bits.   More specifically, in FIG. 6, block 610 is converted to unit 12 of FIG. 1 represents the input data block of the element E, and element E is an expansion block performed in unit 12 of FIG. Represents the tension function. Block 614 is a 48-bit block from unit 12 of FIG. Output block. Block 616 is the input of unit 18 of FIG. 2 represents an output data block from unit 16 of FIG. Times The permutation function P shown by the network 626, the processor 628 and the element 620 is , Generate a 32-bit data block of the output indicated by numeral 622 in FIG. 1 within unit 18 of FIG. Elements 612, 614, 620 and 6 of FIG. 28 executes the encryption function "f" shown in FIG. The element of FIG. 6, in particular the element 612, 614, 626, 628 and 620 handle both encryption and decryption. Used in.   In FIG. 6, element E receives a 32-bit input block and a 48-bit output block. It represents an extension function that creates a force block. Function E is 6 bits each The 48 output bits depicted as 8 blocks are shown in Table 3 of FIG. A function such as that obtained by selecting the input bits in order. Thus, The first 3 bits of E (R) are the bits at positions 32, 1 and 2 of R, and E (R) The last two bits of) are the bits at positions 32 and 1. Each unique bit selection function Number S₁, S₂,. . . S₈Receives a 6-bit input block and a 4-bit output block Generate a lock. This process Function S₁The values are shown in Table 4 of FIG. S₁Is the function defined by Table 4. Is a number and B is a 6-bit block, S1 (B) is defined as Can be The first and last bits of B are in base 2 binary form and range from 0 to 3. Represents the number inside. The number is represented by "i". The middle 4 bits of B are at base 2 , Represents a number within the range of 0 to 15. The number is represented by "j". Table 4 Smell The numbers in the i-th row and j-th column are in the range 0 to 15 Uniquely represented by a block. The block is S1 which is S1 for input B. It is the output of (B). For example, for a binary input 011011, the line 01 (ie row 1) and the column is defined by the binary number 1101 (ie row 13). Can be Since the number 5 is in row 1 and column 13, the binary output is 0101. You. Selection function S₁, S₂,. . . S₈The complete set of is shown in Table 6 of FIG.   Selection function S₁Table 4 which defines the , May be used as it is. However, for the system shown in FIG. 1, the table of FIG. 1 to facilitate the use of combinatorial logic networks rather than lookup tables , Were repositioned as shown in FIG. In particular, the table shown in FIG. Thus, a 6-bit input B can be used without changing the order of the bits in B (at base 2 ) The table has been rearranged to represent numbers in the range 0-63. Table space in Figure 11 In this case, the “output” is the above amount S₁(B) is shown.   The table of FIG. 11, as shown in the table of FIG. A unique 4-bit output (representing) produces the above output (a number in the range 0-63). Be used to determine four possible 6-bit B inputs. , Was further arranged. That is, the table of FIG. 12 shows that 4 bits of output and 6 bits of practicable 2 represents the relationship between the B input of the G. Finally, it is represented by the table shown in FIG. A Boolean algebraic expression has been created that describes the parsed function. This Boolean algebraic expression is Using conventional logic circuit design techniques, a combination for the selection function shown by the table in FIG. Used to synthesize logic circuits. In FIG. 13, the Boolean expressions of the table of FIG. 12 are combined. The VHDL code for embedding is shown. Selection function S₁Figure 8 and for A technique similar to that described for the tables shown in 11-13 is shown in Table 6 of FIG. Each other bit selection function S₂,. . . S₈Combined logic circuit for Used to create a boolean expression that Relocate the above decryption table to the transmitter / You can do it with a cryptographic device, but that doesn't mean you have to Absent.   The permutation function P replaces the bits of the input block to obtain a 32-bit input. Generate a 32-bit output block from the force block. The replacement function is shown in Table 5 of FIG. Is defined in. The output P (L) for the function P defined by this table is L The 16th bit of L is regarded as the 1st bit of P (L), and the 7th bit of L Is regarded as the second bit of P (L), and the same applies to the 25th bit of L. From the input L by continuing until is considered the 32nd bit of P (L) Can be S₁,. . . S₈If is eight different selection functions, then P is a permutation function Yes, E is an extension function. Block B to define f (R, K)₁,. . . B₈Are defined as blocks of 6 bits each and   B₁B₂. . . B₈= K + E (R) (Equation 6) It is. Block f (R, K) is therefore   P (S₁(B₁) S₂(B₂). . . S₈(B₈)) (Equation 7) Is determined to be Thus, K + E (R) is initially shown in Equation 6 Is divided into 8 blocks. Next, each B_iIs S_iGiven as input to 8 blocks S each consisting of 4 bits₁(B₁), S₂(B₂). . . S_Three (B₈) Are combined into a single block of 32 bits that forms the input to P. It is. The output (shown in equation 7) is the output of the function f for inputs R and K.   In the satellite transmitter / receiver system of FIG. 2, the transmitter side receives signals from the signal source 30. Process issue. In the above example, the signal source 30 includes, for example, payload data generation. A transport package containing the minutes and associated header components that describe the contents of the associated data components. Multiple audio and video sources, including a television signal source that stores information in the form of Includes deo source. Data packets from the respective signal sources are transmitted to the units 32 and 3 Undergo asynchronous time division multiplexing (ATDM) on the output path before being processed by .   The signal from the source 30 is the unit 3 containing the MPEG encoder in the above example. 2, encoding and compression are performed. MPEG is a moving image and accompanying audio Established by the Video Expert Group of the International Standards Organization for Coded Representation of It is an international standard. The encoded signal from unit 32 contains error correction data. 4-division unit for encoding a signal containing the signal and QPSK modulating the encoded signal on a carrier Phase shift keying (QPSK) modulator and FEC (forward error corrector) 34. Unit 34 includes convolution and Reed Solomon ( Both RS) encoding is performed. The uplink unit 36 is compressed and encoded. The received signal to a satellite 40 that broadcasts the signal to the reception area of the selected area. . In this example, the satellite 40 is two satellites that considers the balance between channel capacity and transmission power. It works in the same mode. In one mode, the satellite 40 has 120 watts each 16 channels of transmission, and in the other mode, 8 of 240 watts each To transmit the channel.   The signal from the satellite 40 is received by an antenna (not shown) and input to the receiver. It is coupled to the tuner circuit 44. The output signal from the tuner 44 is the unit 46 QPSK demodulated by and decoded using units 48, 50 and 52, Supply to transport processor 56 Is done. A suitable QPSK demodulator for use as unit 46 is the Mary Run Hughes Network Systems (Germany, Germany) 016212) and Comstream Inc. of San Diego, California No. CD 2000). The transport processor 56 Depending on the content of the signal from the unit 52, eg audio or video information. Transport the encoded output signal from unit 52 to an appropriate decoder in unit 62 You. The transport unit 56 receives the corrected data packet from the unit 52, The header of each packet is examined to determine its route. Figure of transport unit 56 1 includes a decryption device shown in FIG. In case of satellite pay system, it is encrypted No plaintext information is entered for each of the header data, decryption key, and multiple sources. It includes a list of available program materials, audio, and miscellaneous items. Satellite cis Systems typically use a larger number of channels for decryption than broadcast or cable systems. It is provided with a larger program listing, which is advantageous in that it need not be read.   The audio and video signals from unit 62 are respectively fed to an audio processor. The video signal to a standard NTSC consumer television receiver 68. NTSC television signal video code encoding into a format suitable for use by Is supplied to the encoder 64. The audio signal from the unit 66 is output from the receiver 68. Supplied to audio input.   Microcontroller 60 is based on Johon S. Stewart. t) in the pending PCT patent application (RCA 87,182). , In response to a user control signal input from the remote control device, Ar 44, demodulator 46, decoder units 48 and 50, and transport processor 5 It works interactively with 6. In summary, the microcontroller 60 is The frequency control signal is supplied to the tuner 44 according to the channel selection of Tune tuner 44 to the appropriate channel. The QPSK demodulator 46 is tuned The demodulated signal to the decoder 48 in synchronization with the received channel The signal quality control signal indicating the quality (for example, SN ratio) is sent to the microcontroller 60. To supply. The demodulator 46 also determines if the demodulator 46 is synchronized with the input signal. A demodulator lock control signal indicating that is supplied to the microcontroller 60.   Decoder 48 decodes the bit errors in the demodulated signal from unit 46. , Use Viterbi algorithm to correct. Decoder 48 is the demodulated signal. In order to efficiently decode the signal, to synchronize its operation with the incoming demodulated signal, Includes well-known internal circuitry. The decoder 48 uses the error correction coding provided to the transmitter. It operates at one of the two error correction decoding rates corresponding to the rate. Satellite 4 When the 0 operates in the low power mode, the transmitted signal is, for example, at rate 2/3. Use error correction code. Transmitted when the satellite 40 operates in high power mode The signal uses a rate 6/7 error correction code. Code rate control signal, example For example, a binary signal generated by the comparator network of the microcontroller 60. Should the code rate used by the encoder 48 remain unchanged, or No, indicates whether to switch to another programmed code rate. Code The remote control signal indicates to the decoder 48 a Reed-Solomon signal indicating the occurrence of a decoding error. A signal product that is combined with the error signal from the decoder 52 to indicate a low quality received signal. A function of the quality signal, or if the demodulator 46 is locked (synchronized to the received signal). Change code rate as a function of demodulator lock signal to indicate May be instructed.   Decoder 48 is using an incorrect error correction code rate for a given input signal. If so, the RS decoder 52 is unlikely to produce a normal output. Decoder 52 Error signal from the demodulator 46 with respect to signal quality and demodulator lock signal. Parsed. The latter two The signal is of acceptable quality and the demodulator 46 is synchronized with the input signal. , The decoder 48 has a different code rate than the received signal. That the error correction code rate of the transmitted signal is Decoding error represented by the error signal has occurred due to the modification There is a possibility to be made. Signal quality or demodulator lock signal is poor quality received Error signal, or the lack of synchronization of the demodulator, the error signal indicates an incorrect code rate. Is used by the decoder 48 (e.g., rain fades (rai (caused by n fade)). The microprocessor 60 Wait a predetermined amount of time before checking the control signal again.   The de-interleaver 50 changes the order of the data signal packets to the original sequence. Return and form Reed-Solomon blocks according to known techniques. For this purpose Therefore, the de-interleaver 27 is inserted by the encoder at the beginning of each RS block. Depending on the 8-bit sync word performed, this results in RS block sync. De The interleaved signal is fed to the Reed-Solomon decoder 28.

[Procedure Amendment] Patent Law Article 184-8 [Date of submission] September 29, 1995 [Amendment content] Claims 1. A digital signal processing device in a system for processing a digital video signal containing a signal containing encrypted information, the input means (10) responsive to the digital signal which may contain encrypted information, and the input. Decryption means (12-18) for providing decrypted information to its output in response to a signal containing encrypted information from the means, and transmitting a signal from the output of the decryption means to an output channel. Output means (26) for providing a first predetermined number of output bits according to a second predetermined number of input bits, the plurality of bit selection functions (S ₁ ,. .., device comprising decryption function means (18) utilizing a combination logic means (628) for executing S _8). 2. Apparatus as claimed in claim 1, wherein said decryption means further comprises means for performing a plurality of iterative calculations each including a calculation of a decryption function (f (R, K)) and a predetermined bit selection function. 3. The apparatus of claim 2, wherein each encryption function is key dependent. 4. 3. The apparatus of claim 2, wherein said decryption means further comprises a plurality of combinational logic means individually associated with each function of said bit selection functions. 5. An apparatus according to claim 1, wherein said decryption means operates according to the DEA standard. 6. The apparatus of claim 1 included in a pay satellite broadcasting system.

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Claims (1)

[Claims] 1. A digital signal processing device in a system for processing a digital video signal containing a signal containing encrypted information, the input means (10) responsive to the digital signal which may contain encrypted information, and the input. Decryption means (12-18) for providing decrypted information to its output in response to a signal containing encrypted information from the means, and transmitting a signal from the output of the decryption means to an output channel. And a decryption function means (18) utilizing combinational logic means (628) for executing a plurality of bit selection functions (S ₁ , ..., S ₈ ). ) Including a device. 2. Apparatus as claimed in claim 1, wherein said decryption means further comprises means for performing a plurality of iterative calculations each including a calculation of a decryption function (f (R, K)) and a predetermined bit selection function. 3. The apparatus of claim 2, wherein each encryption function is key dependent. 4. 3. The apparatus of claim 2, wherein said decryption means further comprises a plurality of combinational logic means individually associated with each function of said bit selection functions. 5. An apparatus according to claim 1, wherein said decryption means operates according to the DEA standard. 6. The apparatus of claim 1 included in a pay satellite broadcasting system.