CN1147890A - Data decryption apparatus in a subscription television signal receiving system - Google Patents

Abstract

A receiver of satellite-broadcast signals including high definition television signals includes apparatus for decrypting encrypted signals. When unencrypted "plaintext" signal information which is not to be decrypted is received, the plaintext information is applied to the decrypting apparatus. Normal decrypting operation is modified so that the input plaintext information appears as unaltered plaintext information at the output of the decrypting apparatus. A bit selection network (628; S1, ... S8) associated with a decipher function (f (R, K)) of the decryption apparatus employs a combinational logic network (18, 628) rather than look up Tables.

Description

Data decryption apparatus in the subscription television signal receiving system

The present invention relates to the field of digital video signal processing, more specifically say to relate to from transmission channel, broadcasting satellite for example, the device of the TV signal that receives deciphering.

Charge video and television equipment, for example wired and satellite broadcasting/receiving system comes all broadcasting equipments are encrypted only to limit the paying customer to insert through control word commonly used or " key ".Encryption at the transmitter place can be adopted various methodologies.In " American National Standard DEA (American NationalStandard Data Encryption Algorithm) " ANSI X3.92-1981 and " American National Standard information system-DEA-operator scheme (American National Standard forInformation Systems-Data Encrption Algorithm-Modes of Operation) " ANSIX3.106-1983, SOME METHODS has wherein been described.

According to principle of the present invention, when the decrypted device of predetermined information of " expressly text " information that needn't decipher and so on received, this predetermined information was transmitted rather than is bypassed (that is, bypass) physically decryption processor through decryption processor.The operation of decryption processor is modified, and makes the predetermined information of input do not appeared at an output of decryption processor by the decryption processor transmission with changing.

Fig. 1 is the block diagram according to the described decryption device of principle of the present invention.

Fig. 2 is the block diagram of satellite video signal broadcasting and receiving system, contains the decryption device of Fig. 1 at the delivery unit Inner of Fig. 2.

Fig. 3 to Figure 13 is block diagram and form, and they help to understand the decryption oprerations of device shown in Figure 1.

Figure 14 distinguishes the state diagram and relevant logical table of importing host state machine in presentation graphs 1 system with Figure 15.

Figure 16 and Figure 17 state diagram and relevant logical table of output state machine in presentation graphs 1 system respectively.

Decryption device shown in Figure 1 is according to data encryption/decryption algorithm (DEA) operation, and this algorithm describes in detail in " American National Standard DEA " ANSI X3.92-1981 to some extent, and it is the canonical algorithm of encryption and decryption to digital data.Especially, the device of Fig. 1 is in " electronic codebook mode pattern " operation down, and this describes in " American National Standard information system-DEA-operator scheme " ANSIX3.106-1983 to some extent.In this example, suppose that the input traffic that receives contains the data from relevant with charged TV system five sources or " equipment ", suppose that also this decryption device provides ten deciphering keys, two keys of each equipment.It is to allow the known current decryption processing of not destroying current another key of usefulness at the key periodic variation that uses that each equipment uses the benefit of two keys that replace.According to the DEA standard, each key is separated mil and 8 words of 64 that parity check bit is formed by 56.In system of the present disclosure, do not use this 8 parity check bits.

Input signal can comprise one of two kinds of data: the cryptogram data of encryption or the plaintext text data of not encrypting.According to the DEA standard, " expressly text " is significant, readable available understand text or signal, and deciphering then is with canonical algorithm cryptogram to be transformed into the expressly process of text.The form of input signal is parallel 8 byte datas stream, and every byte is 8.8 byte shift registers 10 of input are gathered the input data of a byte next time in the effect of clock.In order to simplify not shown clock signal.So, in each clock cycle, 8 (1 bytes) are input in the register 10 by clock, therefore need 8 clock cycle fully with 64 load registers 10. Unit 12,14,16 and 18 form a decryption processor.This decryption processor to from an input 64 of the cycle finish the loading of input register 10 when carrying out the data decryption algorithm.Because (will describe in detail) normal data decipherment algorithm is made up of 16 iteration, and 8 clock cycle bit load registers 10 of needs, so decryption processor unit 12,14,16 and 18 clock speed is two times of input register 10 clock speeds, that is, be two times of speed of gathering following 8 bytes of input data.

Decryption oprerations is subjected to state machine 20, a microcontroller for example, control.State machine 20 can be programmed to system is waited in the data decryption process during 64 remainder gathering input data next time, directly new data is continued to decipher after also can being programmed to the deciphering of secondary data on finishing.20 pairs of input control signals of state machine ' starting ' (Start) (Bypass) respond with ' bypass ', produce (Control) signal of an output ' control '.

' bypass ' signal means that must change Normal decrypting operation makes in the data maintenance of output place of deciphering network and the identical form of plaintext text data of importing not scrambling, promptly must walk around decrypting process.Send this bypass command to decryption processing unit 12 and 16 from ' control ' signal of state machine 20 outputs, and output state machine 22.For decryption oprerations is walked around in the data input that makes a plaintext text, state machine 20 makes " I " register 12 load from input register 10, register 12 waits for that (" do-nothing operation ") a section comprises the time (will describe this process in detail in conjunction with Fig. 3) of 16 deciphering iteration and do not carry out iteration, after this delivers to output register 26 with the content of register 12 then.Be predefined for initial arrange contrary in register 12 inputs owing to arrange (reciprocal permutation) at the final data of output register 26 inputs, expressly text data is identical so the plaintext text dateout of register 26 outputs is with input.So, advantageously finished the deciphering bypass function, need not complexity, used switching network to walk around expressly text data of decryption processing network switch otherwise will involve by means of circuit and interface.

The form of the input cryptogram that system of the present disclosure received and handled/plaintext textual number signal is some packets, and these data are surrounded by one and should be subjected to ciphered data part and to contain the relevant header part of data identification information.Header is not encrypted.Receive packet header Inner and handle the control bit that the network (not shown) detects according to being included in, produce ' bypass ' control signal that is input to unit 20 by an input signal.As above-mentioned, ' control ' signal of 20 outputs has comprised the information of instigating register 12 do-nothing operation during 16 iteration under plaintext text bypass mode from the unit.' control ' signals of 20 outputs also comprise the information that the Port Multiplier of instigating register 12 Inner is operated from the unit, make in the output of the output of this Port Multiplier selected cell 10 and unit 18 one as process object.' starting ' signal that is input to unit 20 is handled the generation of network (not shown) by the input signal before the unit 20, this input signal is handled the header that 8 byte data bags are received in network measuring one, and detect eight bytes (this indication input register 10 is for full) afterwards on ' control ' holding wire generation make the output of input register 10 be loaded into information in the register 12.This information informs that also output state machine 22 another blocks of data have entered the data processing streamline.As will describing in detail, under the control of unit 22, this data block will be from shift register 26 outputs after the decrypting process of 16 step iteration finishes.

Figure 14 and 15 is respectively the state diagram of state machine 20 and relevant logical table.When receiving ' starting ' signal, data loading locations 12 at first will 10 64 of exporting be imported so that the decryption system initialization from the unit in unit 20.16 iteration count of the 20 pairs of deciphering in unit then, after this next ' starting ' signals are waited in unit 20.Under the situation that ' starting ' signal still exists on when the expection decrypting process finishes, unit 20 forward " finishing-waits for " state to and wait for should ' starting ' signal disappearance, the unit 20 wait next one ' starting ' signals after this.Do not use do not occur yet with 10001 and 11111 between 13 relevant states of 5 bit data word because only need 19 states in this example.

Figure 16 and 17 is respectively the state diagram of output state machine 22 and relevant logical table.When unit 22 receives one ' finishing ' (Done) promptly during ' non-finishing ' control signal from state machine 20, this signal is pointed out that data are being deciphered or passing through decryption device under bypass mode.Unit 22 advances to ' ready ' (Ready) state then.When state machine 20 sent decrypting process and ' finishes ' (Done) signal, output state machine 22 number one by one went out 8 bytes (from state S1 to S8).The burst that ' finishing ' ' finishes ' is again waited in right and unit 22.If receive ' finishing ' signal when distributing 8 bytes, then unit 22 writes down byte is distributed by finishing counting with state R1 to R8.If remain unfulfilled deciphering when counting finishes, then unit 22 forwards ' ready ' state to, and waits by the time decrypting process is finished always.If receive ' finishing ' signal when using R1 to R8 state, then state machine 22 directly forwards branch to and gives 8 bytes when counting finishes.

Realize by the data bit on the data link of interconnection between the unit 12,14,16 and 18 in the Pareto diagram 1 suitably by the code word arrangements of DEA standard definition.Realize by the most handy combinational logic network of mil choice function of separating that unit 18 is finished.Specifically, can realize that this will be illustrated afterwards with the combinational logic circuit of one 6 inputs, 4 outputs.For example compare with use, use combinational logic to realize that a choice function is considered to cause the saving of hardware and choice function to carry out faster based on the look-up table (ROM based Look Uptable) of ROM.

When next 64 bit sequences were being gathered by input register 10 by unit 12 to 18 processing and another 64 bit sequence, output state machine 22 allowed the plaintext text to export next byte ground and is sent to output channel via register 26.Output state machine 22 can be programmed to after output register 26 is sent out last byte of known array waits for (because next 64 may not deciphered fully), and state machine 22 also can begin to distribute next plaintext text output sequence of 64 immediately.Therefore data with at a slow speed or inhomogeneous speed when occurring state machine 22 and output register 26 may wait for that or unit 22 may make data block shift out from register 26 when data occur with maximal rate.Whether determine new data by the deciphering network processes by output state machine 22, i.e. whether present but deciphering fully of new data, or whether new data has been deciphered and is just being waited for via register 26 and be distributed to output channel.This decision is made according to for example unit 20 output ' control ' signal messages, should indicate a known block decrypted 16 circulation backs by ' control ' signal.

Under ' bypass ' mode, when having the plaintext text input information of not encrypting, this input expressly text message is sent to output register 26 from input register 10 via decryption processor unit 12 and 18, the operation that makes an amendment in this mode lower unit 12 and 18.Specifically, otherwise during 16 iteration cycles that will be decrypted, do not use output corresponding to the unit 18 of Fig. 6 square frame 622.

By making the do-nothing operation of register 12 during the bypass mode, the bypass mode becomes more convenient, is described as follows.When received 64 whens input under the bypass mode, decryption processor and state machine 20 are started working, and situation is identical during basically with the deciphering mode of operation.Data are sent to register 12 by shift register 10, and each bit position carries out foregoing arrangement simultaneously.In each iteration of 16 iteration of deciphering, the right-hand part of register 12 obtains the last left side of register 12, and the left side of register 12 obtains the output of combinational logic circuit 18.Yet, iteration for once under the bypass mode.In this bypass iteration once, the right-hand part of register 12 obtains the last left side of register 12, and the left side of register 12 obtains the last right-hand part of register 12.The value that register 12 is kept it is ready to be received from the data of register 12 up to output register 26.Register 12 is kept its value by send output to input when each clock arrives.

Realize by Fig. 1 device, be right after as follows based on the data more specifically of the DEA data encryption/decryption algorithm of DEA publication American National Standard X3.92-1981 " American National Standard DEA ".The inverting of ciphering process in greater detail below decrypting process comes down to.

Being designed under the control of one 64 keys of data encryption/decryption algorithm to 64 bit data block encryption and decryption.The previous used same key of encrypting is used in deciphering, has still changed the program of access keys position, makes decrypting process opposite with ciphering process.

Make the initial arrangement " IP " of certainly doing to be encrypted earlier, make once relevant COMPREHENSIVE CALCULATING then, make once opposite arrangement IP at last with initial arrangement with key ^-1The arrangement relevant with key can define by cipher function " f " and key program function " KS ".The explanation of calculating and cryptographic operation hereinafter is provided.Following mark is convenient to understand following material.Known two position pieces are L and R, and then LR represents the every piece of being formed by every follow-up R of L.Because link is joined, for example, B1B2 ... B8 then represents one by everybody of every follow-up B2 of B1 ... every piece of being formed of follow-up B8.

Computations is illustrated by Fig. 3.There are 64 of an input block to be encrypted before being received, at first to stand initial arrangement IP, provide as the table 1 of Fig. 4 by the register 12 of Fig. 1.Input after the arrangement has position 58 as its first, and position 50 is as its second, or the like, position 7 is as last position.Input block after the arrangement enters the COMPREHENSIVE CALCULATING of being described by following equation relevant with key then.This kind that is called " pre-output " then calculates the arrangement shown in output acceptance pattern 5 tables 2, and this arrangement is the contrary of initial arrangement.So the output of algorithm has the position 40 of pre-IOB as its first, position 8 is as its second, or the like, be the last position of output up to the position 25 of pre-IOB.Can rearrange the connecting line that unit 10 exports unit 12 input to and carry out initial arrangement in the input of register 12.In addition, can carry out this arrangement with logical network.Reciprocal permutation in output register 26 inputs can be finished with identical method.

As input, calculate the input of having used through arranging and determine to produce pre-IOB.Except that last piece exchange, calculate the operation that comprises 16 iteration of a cover, this operation comprises the calculating of cipher function f.Cipher function is used two and is determined, and one is 32 determine, and another is 48 a piece, and produces 32 piece.For example, 64 inputs that enter iteration certainly are made up of 32 follow-up 32 piece R of piece L, so this input block is expressed as LR.If K is 48 the piece of selecting from 64 keys, then imports the output L ' R ' of LR after iteration and be defined as

L′＝R

R '=L+f (R, K) (equation 1) wherein "+" in this example represent the computing that adds of mould two by turn.

As previously mentioned, this calculating input of iteration for the first time is that input after arranging is determined.If the output of the 16 iteration is L ' R ', then R ' L ' is pre-IOB.Each iteration is selected the piece K of different keys position from 64 keys representing with KEY.This by can select 56 bit shift register 16 according to from the unit ' control ' signal of 20 realize.Specifically, as a predetermined key program, shift register 16 is moving one or two position with 56 displacements of effective key at that time in the iteration at every turn, and selects 48 positions representing with function " K " at the output of shift register 16 at every turn.Select this 48 positions by the connecting bus between the dispensing unit 16 and 18 suitably in this example." American National Standard DEA " ANSIX3.92-1981 that has mentioned before the example of such key program sees.The iteration of calculating can be described now in more detail.If KS is that n is the integer of 1 to 16 scope Inner as the n of input and the function of KEY, KEY is 64 a piece, the piece K that KS output is 48 _n, this K _nThe position of selecting from KEY is arranged form.

K _n=KS (n, KEY) (equation 2) K _nDecide by the position on 48 different bit positions of KEY.KEY is called the key program because the piece K that uses is exactly the piece K that determines with equation 2 in the n time iteration of above-mentioned equation 1 _nAs preceding, establish input after the arrangement and determine and be LR.If L ₀And R ₀Be respectively L and R, establish L again _nAnd R _nBe respectively the L ' and the R ' of equation 1, when L and R are respectively L _N-1And R _N-1The time ,-K is K _nThat is, when n is in 1 to 16 scope

L _n＝R _n-1

R _n=L _N-1+ f (R _N-1, K _n) (equation 3)

Therefore, pre-IOB is R ₁₆L ₁₆Key program KS produces needed 16 K of algorithm _nValue, this has more detailed description in DEA publication " American National Standard DEA " American National Standard X3.92-1981.

When the device by Fig. 1 is decrypted, be added to the contrary IP of arrangement on the pre-IOB ^-1(the last arrangement among Fig. 1) is the inverting that is added to the initial arrangement IP of input.Therefore have according to equation 1

R＝L′

L=R '+f (L ', K) (equation 4) therefore, in order deciphering only need make the message blocks of having encrypted to be used same algorithm, to be careful simultaneously and in each iterative computation of deciphering, to use the identical key position piece K that adopts with to the data block encryption time.This notion can be expressed as follows:

R _n-1＝L _n

L _N-1=R _n+ f (L _n, K _n) (equation 5) wherein present R ₁₆L ₁₆Be to make the input block that usefulness is calculated in deciphering, L through arranging ₀R ₀It is pre-IOB.That is, for R ₁₆L ₁₆Calculate for the deciphering of passing through the input of arranging, use K in the iteration in the first time ₁₆, use K in the iteration in the second time ₁₅, or the like, in the 16 iteration, use K ₁Relevant therewith, notice that in the arrangement that transmitter/the encryption equipment place carries out be in the inverting that receiver/arranges at the deciphering machine place.Therefore the initial arrangement (IP) at deciphering machine place has arranging at the contrary of encryption equipment place of a correspondence in Fig. 1.

The iterative processing of 16 steps (Fig. 3) has comprised by the combinational logic position among Fig. 1 selects 16 cipher function fs relevant with key (R, calculating K) that network carried out.Should be appreciated that (R K) in fact is exactly decryption function under the decryption device situation of Fig. 1 to f.These decryption function are the contrary of the cipher function realized at transmitter/code machine place.Fig. 6 illustrates network 18 more details.Referring to Fig. 6, be that a piece " R " of 32 of 610 and a label are that 616 48 piece " K " calculates at every turn to a label.The R that determines is half of a data block of 64 of importing, and K is one 48 the piece of selecting from one 64 key.The function " E " that piece R is realized by unit 612 extends to 48 (pieces 614), with 626 consistent with the length of piece K when R made up with K in the unit.As previously mentioned, the iteration of whenever determining is selected the piece K of 48 different key positions of (arrangement) from (after the displacement) 64 keys according to a preset program.

Combinational logic selects network 628 to contain a plurality of unique choice function S1 ... S8, these choice functions have formed the basis of encrypt/decrypt function basically.According to 6 input positions that receive from one ' XOR ' logical network 626, each choice function S1 ... S8 produces the single combination of 4 carry-out bits.That is, each in these choice functions replaces to another group position with one group of raw bits.6 to 4 replacements meet the DEA standard.The raw bits that is replaced is the position or the position through encrypting of expressly text, and this depends on that replacement operation is to carry out at transmitter/encryption equipment place or at receiver/deciphering machine place.

Say that more specifically in Fig. 6, piece 610 representatives are input to the data block of the unit 12 of Fig. 1, and the extended function that unit 12 Inner carry out in the unit E representative graph 1.In piece 614 representative graphs 1 from the unit 12 output 48 pieces.The data block of 18 inputs, unit Fig. 1 is exported and be added to piece 616 representatives from the unit 16 of Fig. 1.Network 626, processor 628 and the permutation function P that is represented by unit 620 are included in the unit 18 of Fig. 1, output 32 bit data block that unit 18 produces by 622 marks of Fig. 6.The unit 612,614,620 of Fig. 6 and the cipher function " f " shown in 628 execution graphs 3.Some unit among Fig. 6, particularly the unit 612,614, and 626,628 and 620 can use in encryption and decryption are handled.

In Fig. 6, the extended function that unit E represents to receive one 32 input blocks and produces one 48 IOB.Function E represents that to obtain 48 carry-out bits, these 48 carry-out bits are write as 8, every 6 by select the input position by the indicated order of table 3 among Fig. 7.Therefore the junior three position of E (R) is the position on the position 32,1,2 of R, and last two of E (R) is position on position 32,1.Unique position choice function S1, S2 ... among the S8 each receives one 6 input block, and the output that produces one 4 is determined.This process is by table 4 expression of Fig. 8, and this table has comprised the numerical value of function S 1.If S1 is that B is one 6 a piece by the function of table 4 definition, then S1's (B) is definite as follows.Binary form with base 2 represents that the number of 0 to 3 scope Inner is represented in the first place of B and position, end.If should be " i " by number.Represent that with base 2 number in 0 to 15 scope is represented in 4 of the centres of B.If should be " i " by number.In table 4, the number on the capable j column position of i is a number of representing uniquely in 0 to 15 scope and with one 4 piece.This piece of 4 is exactly the output S1 (B) of S1 for input B.For example, for binary system input 011011, line number is binary zero 1 (at once 1), and columns is by binary one 101 decisions (that is, row 13).Be expert at 1, on the row 13, occur several 5, so binary system is output as 0101.Choice function S1, S2 ... the full set of S8 sees the table 6 of Fig. 9.

The table 4 of definition choice function S1 can as directed mode use, and promptly uses as the mode of above-mentioned DEA standard declaration.Yet in the system of Fig. 1, the table 4 of Fig. 8 had once been done as shown in Figure 11 to rearrange and had not been used look-up table so that use combinational logic network.Specifically, shown in the table of Figure 11, the table 4 of Fig. 8 had once been done to rearrange, and made 6 input B (with base 2) represent a number at 0 to 63 scope Inner, and did not change order every among the B.In the table of Figure 11, the above-mentioned several S1 (B) of " output " representative.

Once the table of Figure 11 is done further to arrange, (representing the number of 0 to 63 scope Inner) four kinds of possible 6 B that shown in the table of Figure 12, make (represent the number of 0 to 16 scope Inner) unique 4 outputs can be used for determining producing this output import.Be that the table of Figure 12 is represented the relation between one 4 outputs and possible 6 the B inputs.At last, once created a Boolean algebra expression formula of describing the function of the table representative shown in Figure 12.This Boolean expression is used to use the synthetic combinational logic circuit of conventional Logic Circuit Design technology, to realize by the choice function shown in the table of Figure 12.Figure 13 is expressed as the Boolean expression of the table of realizing Figure 12 and the VHDL sign indicating number that adopts.Used the technology identical to come to be each other position choice function S2 with the above-mentioned technology that table adopted of the Fig. 8 that realizes choice function and 11 to 13 ... S8 creates the Boolean expression that synthetic combinational logic circuit is used, and these choice functions see the table 6 of Fig. 9.Rearranging also of described each decryption table can be in that transmitter/the encryption equipment place finishes, but this is optional.

Permutation function P is by everybody arrangement is produced one 32 IOB by 32 input block to input block.The table 5 of Figure 10 is seen in the definition of this permutation function.The output P (L) of the function P of table definition can be with the following method obtains from input L thus, promptly gets the 16th of L the 1st as P (L), gets the 7th of L the 2nd as P (L), or the like, up to getting the 25th of L the 32nd as P (1).Suppose S1 ... S8 is eight different choice functions, and P is a permutation function, and E is an extended function.For define f (R, K), piece B1 ... B8 is defined as 6 piece, has for these pieces

B1B2 ... B8=K+E (R). (R K) is defined as (equation 6) piece f then

P (S1 (B1) S2 (B2) ... S8 (B8)). (equation 7)

So, K+E (R) at first is separated into 8 and is determined, shown in equation 6.Each Bi is got the input of making Si then, respectively is 8 piece S1 (B1) of 4, S2 (B2) ... S8 (B8) is merged into single 32 piece of the input of forming P.Then output (seeing formula 7) is the output of the function f when being input as R and K.

In satellite transmitter/receiver system of Fig. 2, radiating portion is handled the signal from signal source 30.In the present embodiment, source 30 comprises a plurality of Voice ﹠ Videos source, for example comprise a plurality of TV signal source, these TV signal source comprise the information that transmits bag (transport packets) form again, and described information contains the relevant header composition of the valid data composition data component content relevant with an explanation.From the packet in each source before being handled by unit 32 and 34 by asynchronous time-division multiplex (ATDM) to an output channel.

The signal of 30 outputs is encoded from the source, is compressed by unit 32 then, and unit 32 contains the mpeg encoded device in this example.MPEG is the international standard by the motion picture expert group of International Standards Organization (International StandardsOrganization) (Moving Pictures Expert Group) exploitation, is used for representing to encode the audio signal that is stored in the motion video on the digital storage medium and follows.Coded signal by unit 32 outputs is sent to a quaternary PSK (QPSK) modulator and forward error correction device (FEC) 34, and unit 34 is modulated to signal on one carrier wave with the error correction data coding and with coded signal QPSK.Convolutional encoding and Reed-Solomon (RS) coding are carried out in unit 34.Upstream cell 36 will be compressed and encoded signals sends to satellite 40, the geographical receiving area that this satellite 40 is selected with signal broadcasting to.In this example, satellite 40 is worked in the mode of two kinds of compromise selection channel capacities and transmitting power.Under a kind of mode, satellite sends 16 passages with the power of 120 watts in each passage, sends 8 passages at the next power with 240 watts in each passage of another way.

Received by one (unshowned) antenna from the signal of satellite 40, be coupled to the input tuning circuit 44 of a receiver then.By unit 46 demodulation,, be added to a transport processor 56 then from the signal of tuner 44 output by unit 48,50 and 52 decodings.The qpsk demodulator that is fit to do unit 46 usefulness can be buied from the company of Hughse Network system (Hughes NetworkSystems) (the integrated circuit model is NO.1016212) in Germany city, the Maryland State (Germantown) or from the emerald green nurse company of Gene Combs (Comstream Corp.) (model NO.CD2000) in Californai San Diego city.Transport processor 56 will be sent to the suitable decoder of unit 62 Inner from the decoded output signal of unit 52 according to unit 52 output signal content such as audio or video information.Delivery unit 56 receives from the packet of the error correction of unit 52 and checks the transmission route of the header of each bag with the decision bag.Delivery unit 56 has comprised decryption device shown in Figure 1.In this satellite Fare Collection System, the plaintext text message of not encrypting comprises header data, deciphers key, can obtain the list of program material in each of some sources, audio frequency and other.Satellite system provides usually than broadcasting or the much more channel of wired system, and these channels have preferably should decrypted much more program guide.

Voice ﹠ Video signal by unit 62 outputs is added to an audio process 66 and a ntsc television signal video frequency encoder 64 respectively, and this video encoder 64 becomes to be suitable for the form that signal processing circuit is used in the standard NTSC domestic television set 68 with video signal coding.Be added to the audio frequency input of receiver 68 by the audio signal of unit 66 outputs.

Microcontroller 60 in response to one for example from ' user controls (User Control) ' input signal of remote control, and with tuner 44, demodulator 46, decoding unit 48 and 50, alternatively operate with transport processor 56, this has detailed description in the PCT of JohnS.Stewart patent application (RCA87,182).Say that simply microcontroller 60 provides one ' frequency (Frequency) ' control signal according to user's channel selection to tuner 44, make tuner 44 be tuned to suitable passage.Qpsk demodulator 46 with tuning channel synchronous, provide a demodulated signal to decoder 48, ' signal quality (Signal Quality) ' control signal of the signal quality (as signal to noise ratio) that indication one receives also is provided to microcontroller 60.Whether synchronous with input signal demodulator 46 also provide an indication demodulator 46 ' demodulator locks (Demodulator Lock) ' control signal to microcontroller 60.

Decoder 48 uses Viterbi (Viterbi) algorithm to decode and to correct by the bit-errors in the demodulated signal of unit 46.Decoder 48 comprises some known internal networks, and the demodulated signal that makes its work and input is synchronously so that decode to demodulated signal effectively.Decoder 48 is operated in one of two kinds of error correction decoding rates, and these two kinds of code checks conform to the error correction coding rate that provides at the transmitter place.When satellite 40 is operated in low power mode, transmits and use for example 2/3 error correction code rate.When satellite 40 is operated in high power mode, transmits and use 6/7 error correction code rate.' code check (Code Rate) ' control signal, the binary signal exported of the comparator network in microcontroller 60 for example, expression decoder 48 employed code checks should remain unchanged, and perhaps should be transformed on another code check of drafting.When ' signal quality ' signal indicates the signal quality that receives inferior, perhaps indicate demodulator 46 and be not locked in (not synchronous) on the signal that is received with received signal when ' demodulator locks ' signal, and when one decoding error has appearred in indication from ' (Error) makes mistakes ' signal of Reed-Solomon decoder 52, ' code check ' but control signal instruction decoder 48 changes code checks.

If 48 pairs one known input signals of decoder are using an incorrect error correction code rate, RS decoder 52 provides an output normally with regard to unlikely meeting.Analysis must be considered ' signal quality ' and ' demodulator locks ' signal by demodulator 46 outputs during from ' makeing mistakes ' signal of decoder 52 output.If the quality of these two signal indication input signals can be accepted and demodulator 46 is synchronous with input signal, then might be because decoder 48 is using the code check different with the code check that receives signal by the decoding error of ' makeing mistakes ' signal indicating, promptly change the error correction code rate that transmits at the transmitter place.If the signal quality that the indication of ' signal quality ' signal is received is inferior or ' demodulator locks ' signal indication demodulator is not synchronous, the signal of then ' makeing mistakes ' may be exactly that these factors (as the decline that is caused by rain) rather than decoder 48 use incorrect code check to cause.Thereby microprocessor 60 can be waited for one section preset time before checking these control signals once more.

Deinterleaver (deinterleaver) 50 orderings with the data-signal bag return to original order, and form each Reed-Solomon piece according to technique known.Deinterleaver 27 relies on the 8 bit synchronization words of the section start of each RS piece by the encoder insertion for this reason, thereby is the synchronous condition of having created of RS piece.Signal behind the deinterleave is added to Reed-Solomon decoder 28.

Claims (7)

1, a kind of data stream processing device the system that receives the video signal digital data flow that comprises enciphered message and non-enciphered message from communication port comprises

Be used to receive the input unit (10) of described data flow;

Be used for receiving to contain encrypting and the decrypts information device (12-18) of the signal of enciphered message not from described input unit, described decryption device (a) presents Normal decrypting operation according to the received signal that contains enciphered message under normal first mode, and (b) makes described not coded signal be sent to the output of described decryption device basically unchangeably via described decryption device according to containing the operation that the received signal of enciphered message not presents through revising under one second mode; And

Be used for signal is sent to from the described output of described decryption device the output device of an output channel.

2, according to the described device of claim 1, wherein

Described device is included in a charge broadcasting-satellite system Inner, and this charge broadcasting-satellite system is used to broadcast the information that comprises a plurality of program guides of not encrypting and decryption key spoon in the source of Inner from a plurality of.

3, according to the described device of claim 1, wherein

Described input unit contains input shift register (10);

Described output device contains Output Shift Register (26);

Described decryption device comprises that one is used for receiving from described input shift register the input memory device (26) of data; And

Described decryption device is carried out the data arrangement of iteration under described normal first mode, and under described second mode period of do-nothing operation one regulation and do not carry out described iteration, this section is after the period, and data are sent to described Output Shift Register from described decryption device.

4, according to the described device of claim 3, wherein

When described decryption device was being handled follow-up data sequence and described input shift register and gathered next data sequence, described Output Shift Register sent data to described output channel.

5, according to the described device of claim 1, wherein

Described decryption device comprises and is used to realize an initial data arrangement (IP), an iterative computation relevant with key and one and arrange opposite final arrangement (IP at first ^-1) device.

6, according to the described device of claim 1, wherein said decryption device comprises

One have from described input unit receive data first input, first output that one second input, is connected with described output device, reach one second memory device of exporting (12); And

One has the input that is connected with described second output of described memory device, and the selection network (18) of exporting that is connected with described second input of described memory device.

7, according to the described device of claim 6, wherein

Institute's rheme selects network that each key position is responded.

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