JPH0950698A - Data rewriting method for microcomputer incorporated with flash memory together - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent degradation of holding data caused by driving memory by providing a refresh mode in which data transfer is performed between a flash memory and a RAM. SOLUTION: A refresh mode is selected by a mode register 3, a start address and a finish address of area in which refresh is performed is generated by a flash mode control circuit 4, and an address counter 7 is set. Next, data is read out from a flash memory 1 according to a counter value of a counter 7, it is transferred to a RAM 2 and compared. Successively, after block erasing is performed by an erasing/writing control circuit 9, data evacuated to a RAM 2 is transferred to the memory 1, and rewriting is performed. Thereby, degradation by disturbance and stress generated by operation of reading out and rewriting data stored in the memory 1 can be prevented, reliability and a holding characteristic of a holding data can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data rewriting method for a microcomputer in which a flash memory having a divided memory cell array is mixedly mounted as a nonvolatile memory.

[0002]

2. Description of the Related Art Conventionally, a data rewritable EPR is used as a nonvolatile memory mounted in a microcomputer.
OM, EEPROM, etc. may be used. This EP
The ROM can irradiate a predetermined position with ultraviolet rays to erase the stored data up to that point and write new data. When this memory is rewritten, it may be affected by ultraviolet rays on other parts or it may be mounted at a position where it cannot be irradiated with ultraviolet light. Therefore, remove it from the board on which it is mounted and rewrite it with the memory alone. There is a need.

However, the EEPROM can erase the data held up to that point and rewrite it with new data by applying a predetermined electric signal. That is, in the EEPROM, when mounted, a wiring pattern for erasing / writing is formed on the wiring board, and a predetermined electric signal is applied to the EEPROM to erase the retained data without removing the memory, You can write new data.

However, since the EEPROM is provided with a selection transistor, the overall cell size is EP.
It is several times larger than ROM and difficult to integrate. Therefore, in recent years, a flash E that is electrically rewritable and has a memory cell composed of one transistor
EPROM is used. This flash EEPR
The OM can be rewritten by a predetermined electric signal in a state of being mounted on the wiring board, and a large memory capacity can be realized.

[0005]

However, as shown in FIG. 7, the above-mentioned flash EEPROM has, for example, an N-type flash EEPROM.
In the case of an OR flash EEPROM, data writing is the same as in EPROM, and the principle is that hot electrons generated near the drain are injected into the floating gate by using the high voltage applied to the control gate. Data erasing is based on the principle that the control gate is grounded and the tunnel current generated by the high voltage applied to the source is used to extract hot electrons from the floating gate.

Therefore, the oxide film under the floating gate is formed as a thin film of about 10 nm called a tunnel oxide film. Therefore, the memory cells of the flash EEPROM have various disturb problems which are technically difficult to solve. For example, as a technical approach, from the viewpoint of forming technology, the quality of the tunnel oxide film is improved to eliminate defects. Further, when the circuit is configured, the stress applied to the parts is avoided as much as possible.

FIG. 8 shows various disturbs that occur in the flash EEPROM. In this configuration, when writing to the memory cell 1, the memory cell 2 has a common word line, so that a gate disturbance occurs in which the gate is at a high potential. Furthermore, in the memory cell 3,
On the contrary, since the bit lines are common, a drain disturb in which a high potential is applied to the drain occurs. Further, when the block 1 is erased, the source disturb of the block 2 in which the source becomes a high potential occurs.

[0008] These disturbances or stresses are relatively short in time when erasing all blocks at once, and are not a problem. In particular, source disturb does not occur in the case of batch erase.

However, when it is actually used, block erasing is often used, usually 10 ⁴ to 10
Writing / erasing ⁶ times is required. Especially, depending on the usage situation, only certain blocks are used repeatedly,
Writing and erasing may be performed 10 ⁴ to 10 ⁶ times. At this time, there is a block that is not rewritten at all, and that block receives 10 ⁴ to 10 ⁶ times more stress when rewriting other blocks than in the case of batch erasing, affecting the stored data. May be given.

Further, considering that the state of the data stored for a long period of time is favorably maintained, the disturbance in the drain voltage and the gate voltage applied during reading also poses a problem.

Therefore, an object of the present invention is to provide a data rewriting method of a microcomputer having a flash memory for preventing deterioration of held data caused by driving the memory with a simple structure.

[0012]

In order to achieve the above object, the present invention provides a flash memory in which data can be electrically rewritten and a memory cell area is divided into a plurality of blocks, and a memory device in which data can be written and read. In a microcomputer in which the blocks are mixed, the data in the area based on the block is saved from the flash memory to the storage device, the data in the saved area part of the flash memory is erased, and the data is again stored in the flash memory from the storage device. A data rewriting method of rewriting the data in the saved area and refreshing the data held in the flash memory for each area based on the block.

According to the data rewriting method of the microcomputer having the flash memory having the above-mentioned configuration embedded therein, the data retained in the flash memory is stored in the storage device (RA).
Data is transferred to M) and temporarily saved, and the data in the saved area of the flash memory is erased. And
The retained data is refreshed by rewriting the data saved in the area of the flash memory from the storage device again.

[0014]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a schematic configuration for carrying out a rewriting method of a microcomputer including a flash memory as an embodiment according to the present invention.

In this structure, the flash memory 1 in which the memory cell array is divided into a plurality of blocks, the RAM 2 incorporated in the microcomputer, the mode register 3 for designating the refresh mode, and the voltage for refresh are applied. A refresh mode control circuit 4 for determining whether or not the start is performed, a start address register 5 for generating a start address of an area (one block or several blocks) to be refreshed, an end address register 6 for generating an end address, and the start An address counter 7 that counts based on an address and an end address, compares the count number of the address refreshed in the address counter 7 with the end address number, and instructs the refresh mode control circuit 4 to complete the refresh. Based on a control signal from the comparator 8 and the refresh mode control circuit 4, transfer (writing) of data held between the flash memory 1 and the RAM 2 and erasing data held in the flash memory 1 in block units. It is composed of an erase / write control circuit 9.

In this embodiment, the refresh mode is selected by the mode register 3 in order to switch from the normal operation to the refresh mode. The methods are (1) hardware mode, (2) monitor mode,
(3) Software mode and the like are possible. (1) Hardware Mode As shown in FIG. 2, the microcomputer is provided with an input terminal for functioning as a refresh mode. By setting the potential of this input terminal to High level,
The refresh mode is set in the mode register.

When this mode is set, as shown in FIG. 3, the preset start address and end address of the refresh block are set in the mode register respectively, and the data from the start address to the end address is stored in the flash memory. It is read from 1, and temporarily saved in the RAM.

After this, the blocks in the saved area are erased. After the erase operation is completed, the flash memory 1 is restarted.
By rewriting the data read from the RAM 2 to the original area of the above, the series of refresh processing is completed. (2) Monitor mode As shown in FIG. 4, in addition to a matrix (block-divided area) of the main body memory for storing data, control programs, etc., a matrix including cells of several bits or more for monitoring is provided. .

For example, a matrix of at least 2 bits or more for monitoring is provided. This is "0" of DATA
This is because both "1" and "1" are monitored. Further, in consideration of the sensitivity of the monitor cell, for example, a configuration with a total of 6 bits using 3 bits for DATA of 1 and 0 may be used. According to this configuration, a majority decision can be made for each DATA. That is, from the beginning, the monitor cell has 1b
It can be used even if it has a defect. Alternatively, a weak monitor cell can be used.

The read voltage applied to the cells of this matrix is controlled more strictly than the voltage applied to each cell of the main body memory. For example, it is used as a data retention monitor by increasing the voltage a applied to the drain of the cell at the time of reading, by increasing the gate voltage b, or by always continuing reading. If even one bit of data in the monitor cell is inverted, the refresh mode is automatically set in the mode register, and a series of refresh processing similar to that described above is started. (3) Software mode As shown in Fig. 5, an appropriate address (1by
te or several bytes), write the password to the software created in advance, and periodically monitor whether the password is the same as the one written when reading the data. Software for automatically setting the refresh mode is written in the register, and a series of refresh processes similar to those described above is started.

A method of rewriting a microcomputer in which the flash memory having the above-described configuration is mounted will be described with reference to the flowchart shown in FIG. First,
When the refresh mode is selected by the mode register 3, the fresh mode control circuit 4 determines whether or not the instruction voltage (voltage for refresh) VPP for writing / erasing is applied (step S2) and is applied. If so (YES), the start address and end address of the area (one block or several blocks) to be refreshed first are generated, and the start address is set in the address counter 7 (step S3). If the indicated voltage VPP
If is not applied (NO), the refresh mode is not entered.

Next, in accordance with the counter value of the address counter 7, the data held in the flash memory 1 is sequentially read and the data is sequentially written into the RAM 2 (step S4). At this time, unlike the address on the normal memory map, the address to be written to the RAM 2 is assigned from address 0, the data read first from the flash memory 1 is the address 0 of RAM 2, and the next read data is the address of RAM 2 1. Address, and data is transferred in the same manner thereafter.
In this way, the area of the block to be refreshed of the flash memory 1 and the area of the RAM 2 in which the data is written have a one-to-one correspondence.

Then, the comparator 8 compares the address of the data to be refreshed in the flash memory 1 with the end address, and if they are the same (YES), the refresh mode control circuit 4 is informed of the end of the transfer. The instruction is given, and the data transfer (temporary saving) to the RAM 2 is completed.

Next, in response to an instruction from the refresh mode control circuit 4 to erase the data block saved in the RAM 2, the erase / write control circuit 9 performs block erase (step S6), and the erase is completed. In this case, the end instruction is output to the refresh mode control circuit 4.

The refresh mode control circuit 4 is
In accordance with the end instruction, the address counter 7 is again set to RA
The start address of the area for transferring data from M2 to the flash memory 1 is set (step S7), the erase / write control circuit 9 is instructed to rewrite, and the data saved in the RAM 2 is transferred to the flash memory 1 (step S7). S8). Then, when the rewriting of all data is completed (step S9), it is judged whether or not the refresh operation is completed for the area (block) in which the data to be refreshed is stored (step S10), and the steps are performed until the completion. Returning to S3, the same refresh operation as described above is repeated. When the blocks of all areas of the flash memory are refreshed, the operation in this mode ends.

The refresh mode may be performed not only for all areas but also for any block. Further, as the RAM2, the RAM built in the microcomputer was used, but through the port,
It may be saved in an external memory using DAM or the like. Further, the refresh mode may be set by an external terminal or added to an instruction instead of being set by the mode register. It may also be registered as a refresh command as in the conventional program and erase modes.

As described above, according to the present embodiment, by providing the refresh mode for transferring data between the flash memory and the RAM, the disturb which is held in the flash memory and is generated by the read operation or the rewrite operation is performed. It is possible to refresh the held data by temporarily transferring and saving the held data that deteriorates due to the stress and by rewriting. The reliability and retention characteristics of the data retained by this refresh can be improved. It is very effective in combination with the conventional process approach. Moreover, the circuit required for executing this refresh mode is extremely small, and does not affect the cell area of the flash memory or the device structure.

[0028]

As described above in detail, according to the present invention, it is possible to provide a data rewriting method for a microcomputer having a flash memory in which the deterioration of the held data caused by the driving of the memory is prevented by a simple structure. it can.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration for carrying out a rewriting method of a microcomputer including a flash memory as an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example for setting a hardware mode for starting data rewriting.

FIG. 3 is a timing chart for explaining data rewriting in the hardware mode of the present embodiment.

FIG. 4 is a diagram showing a configuration example for explaining a monitor mode for starting data rewriting according to the present embodiment.

FIG. 5 is a diagram for explaining a software mode for starting data rewriting according to the present embodiment.

FIG. 6 is a flowchart for explaining the data rewriting method of the present embodiment.

FIG. 7 is a diagram for explaining data writing and data erasing in a conventional flash EEPROM.

FIG. 8 is a diagram for explaining various disturbances that occur in a conventional flash EEPROM.

[Explanation of symbols]

 1 ... Flash memory 2 ... RAM 3 ... Mode register 4 ... Refresh mode control circuit 5 ... Start address register 6 ... End address register 7 ... Address counter 8 ... Comparator 9 ... Erase / write control circuit

Claims (6)

[Claims] 1. A microcomputer in which a flash memory in which data is electrically rewritable and a memory cell area is divided into a plurality of blocks and a storage device in which data can be written and read are mounted together are provided in an arbitrary area for each block. Data in the flash memory to the storage device, erase the data in the saved area of the flash memory, rewrite the saved data from the storage device to the original area again, and write it to the flash memory. A data rewriting method for a microcomputer including a flash memory, characterized in that retained data is refreshed for each area based on the block. 2. In a microcomputer in which a flash memory in which data is electrically rewritable and a memory cell area is divided into a plurality of blocks and a storage device in which data can be written and read are mixedly mounted, a preset refresh mode is designated. As a result, an instruction voltage for starting the refresh operation is applied to the mode register set in the flash memory, and the first step of starting the execution of the refresh mode and one block or several blocks performing the refresh operation are performed. Second step of generating a first start address and a first end address of the area, and setting the first start address in a counter, and reading the data held in the flash memory sequentially from the first start address. Data in the area of the storage device corresponding to A third step of performing data transfer to write data, and a step of updating the address value from the start address, transferring data from the flash memory to the storage device, and ending the data transfer when the end address is reached. 4th step, 5th step of erasing the data in the area of the flash memory to which the data is transferred, 2nd start address of the area whose data has been erased and 2nd
A sixth step of generating an end address and setting a second start address in a counter, reading data temporarily saved from the storage device, and performing data transfer of sequentially rewriting the data from the second start address A flash memory, comprising: a seventh step; and an eighth step of ending rewriting of data and completing a refresh operation of the data when the second end address is reached. Data rewriting method for microcomputer. 3. In the microcomputer, the preset refresh mode is designated by providing the microcomputer with an input terminal for starting a refresh operation and setting the potential of the input terminal to a predetermined level. To the mode register,
2. A data rewriting method for a microcomputer having a flash memory according to claim 1, wherein refreshing is started by setting a flag as an interrupt signal. 4. In the microcomputer, a matrix cell including at least 2 bits or more and 10 or more cells is provided outside the area of the memory cells divided into blocks, and a voltage applied to the memory cells at the time of reading data. 2. A higher voltage is applied to the drain of the cell of the matrix to monitor data retention, and if even one bit of data in the cell of the matrix is inverted, the refresh operation is started.
A data rewriting method for a microcomputer in which the flash memory described above is embedded. 5. In the microcomputer, a matrix cell including cells of at least 2 bits is provided in areas other than the area of the memory cells divided into blocks, and the voltage is higher than the voltage applied to the memory cells when reading data. 2. A voltage is applied to the gate of the cell of the matrix to monitor the data retention, and if the data of the cell of the matrix is inverted by one bit, the refresh operation is started. A data rewriting method for a microcomputer having a flash memory embedded therein. 6. In the microcomputer, a password is written to an arbitrary plurality of addresses in the area of the memory cell divided into blocks, the password is monitored during the operation of the microcomputer, and the password does not match. 2. A data rewriting method for a microcomputer having a flash memory according to claim 1, wherein the refresh operation is started.