JPH0950450A - Simulation method for arrangement and wiring, and semiconductor arrangement and wiring device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a timing error to be generated at the time of detailed simulation in a simulation before wiring by estimating the wiring length of the wiring passing through a wiring difficult area long. SOLUTION: After call arrangement is completed by a floor planner. a global box 1 where it is estimated that the wirings are to be congested, is found. It is highly possible that the wirings 2-4 passing through the global box 1 are not wired with a wiring length estimated by the floor planner in a layout tool. Then, for the wiring for which the wiring is difficult by wiring length information calculation after the cell arrangement in the floor planner, the wiring length is estimated long, and the wiring length information of the simulation before the wiring is used. Thus, the wiring length is estimated longer for the wirings for which the change of the wiring length is estimated in arrangement and the wiring by the layout tool and the timing error in the datailed simulation by the change of the wiring in the layout tool is found in the simulation before the wiring.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a gate array
The present invention relates to a layout evaluation method for a macrocell or block level layout operation (hereinafter, referred to as a floor plan) and a semiconductor layout and wiring apparatus (hereinafter, referred to as a layout tool) performed after a virtual simulation of a manufacturing process of a semiconductor element such as ECA / ASIC is there.

[0002]

2. Description of the Related Art In such a placement and routing simulation method, placement work at a macrocell or block level (hereinafter, floor plan) performed after virtual simulation is performed. (Hereinafter, this lattice is referred to as a global box), and the number of wirings in the lattice is evaluated. If the result of the simulation (hereinafter referred to as pre-wiring simulation) in which the evaluation is performed using the wiring length information obtained based on the layout information in the floorplan is good, the layout tool is based on the layout information made in the floorplan. Placement and wiring are performed using. At this time, if the difference between the wiring length of the temporary wiring used in the floor plan and the actual wiring length used in the detailed simulation after placement and routing is large, the timing error of the delay in the wiring also becomes large, and in the pre-wiring simulation there is no error timing. However, a timing error may occur in the detailed simulation.

In the past, in order to suppress the occurrence of such an error, the location of the wiring expected to be crowded was shown to the user at the stage of floorplanning to improve the layout.
Since there is a limit to the improvement of the layout and it is necessary to compromise to some extent, the pre-wiring simulation is performed while leaving the difficult wiring area.

If the result of the pre-wiring simulation is good, placement and routing is performed. However, wiring may be changed at locations where wiring is expected to be difficult in the floor plan, and the wiring length becomes longer than the floor plan execution device (hereinafter referred to as the floor planner) expected, so delays due to wiring may occur. appear. As a result, a timing error will occur in the detailed simulation after placement and routing.

FIG. 3 shows wiring paths 8 and 9 connecting the cell 10 and the cell 11. In the floor planner, since the Steiner route is used as the wiring evaluation route, the wiring route connecting the cell 10 and the cell 11 is either the route 8 or the route 9. In the layout tool, since the first wiring takes the Steiner path, the wiring path connecting the cell 10 and the cell 11 is either the path 8 or the path 9.
Change wiring when wiring is not possible.

Conventionally, both devices have cell 10 and cell 11
The same wiring route can be selected for the wiring for, but since information about the wiring route in the floor planner is not passed to the layout tool, different wiring routes may be selected. As a result, it is conceivable that the wiring difficult area in the floor planner and the wiring difficult area in the layout tool do not always match. This means that even if the floor planner considers the difficult wiring area, it cannot be used in the layout tool.

[0007]

A first aspect of the present invention is a placement and routing simulation method capable of causing a timing error occurring in a detailed simulation in a pre-wiring simulation and reducing a timing error in the detailed simulation. It's about to get.

A second aspect of the present invention is a wiring route in a floor plan execution device and a wiring route in a semiconductor placement and wiring device.
An object of the present invention is to obtain a semiconductor placement and routing device that can match the wiring length, the results of the pre-wiring simulation and the results of the detailed simulation.

A third aspect of the present invention is a wiring route in a floorplan execution device and a wiring route in a semiconductor placement and routing device.
An object of the present invention is to obtain a semiconductor placement and routing device that can match the wiring length, the results of the pre-wiring simulation and the results of the detailed simulation.

A fourth object of the present invention is to obtain a layout and wiring simulation method capable of improving the reliability of the layout evaluation of the floorplan execution device.

[0011]

Means for Solving the Problems In the first invention,
In the evaluation of the adequacy of the placement in the placement work performed after the virtual simulation, the chip is divided into small grids and the number of wires in the grid is evaluated, and the evaluation results are placed in the placement work. This is a method of estimating the wire length of a wire passing through a global box having a large number of wires in a simulation performed using the wire length information obtained from the information.

According to a second aspect of the present invention, in the semiconductor placement and routing apparatus that receives placement information for placement work performed after virtual simulation from a floorplan execution device having an interface function and performs placement and routing, cell placement information for the placement work is provided. And the wiring length when the wiring length is corrected in the arranging work via the floorplan execution device.

According to a third aspect of the present invention, in a semiconductor placement and routing apparatus that receives placement information for placement work performed after virtual simulation from a floor plan execution device having an interface function and performs placement and routing, a route provisionally routed in the placement work is performed. Information and the wiring length in the case where the wiring length is corrected in the arranging work through the floorplan execution device.

In the fourth aspect of the invention, in evaluating the adequacy of the wiring arrangement in the arrangement work performed after the virtual simulation, the timing information based on the timing verification result of each wiring is reflected as an evaluation element for the wiring dangerous area determination.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. 1 is a diagram showing a first embodiment of the present invention. 1 indicates a global box which is expected to be difficult to wire, and 2 to 7 indicate wires. First, after the cell layout is completed by the floor planner, the global box 1 that is expected to have a crowded wiring is found. It is highly possible that the discovered wirings 2 to 4 passing through the global box 1 are not routed with the wiring length expected by the floor planner in the layout tool. Therefore, the wiring length is estimated to be long for the wiring that is difficult to wire with the wiring length information calculated after the cell placement in the floor planner.

The estimation method is shown below. [Original wiring length + (Number of global boxes where wiring is difficult ×
α)] = estimated wiring length (where α is a positive real number and is a value determined by various conditions such as a layout tool and device for wiring).
This floor planner allows input of an arbitrary real number α. )

Thus, the wiring length is estimated to be long with respect to the wiring whose wiring length is expected to be changed by the layout tool, so that the timing error in the detailed simulation due to the wiring change in the layout tool can be corrected at the time of the pre-wiring simulation. You will be able to find it at. The result is shown in FIG. The flow is shown in FIG. The flowchart is shown in FIG.

As described above, in the first embodiment, it is possible to improve the reliability of the pre-wiring simulation by estimating the wiring length of the wiring which is expected to be changed by the layout tool. it can.

Embodiment 2. FIG. 3 is a diagram showing a second embodiment of the present invention. In FIG. 3, 8 and 9 are wiring paths and 10 and 11 are cells.

First, information on a wiring route when temporary wiring is performed in the floor planner is created for each wiring. Specifically, if the wiring route connecting the cell 10 and the cell 11 in FIG. 3 is the route 8, the floor planner outputs that this wiring route is the route 8.

If this information can be read by the layout tool, the wiring at the time of floorplanning and the wiring by the layout tool can be the same wiring unless the wiring is changed. The flow is as shown in FIG. If the floor planner outputs the wiring length corrected in the first embodiment and the layout tool can read the information, the wiring length can be lengthened when the wiring route is changed by the layout tool. It can be judged by the layout tool.

As described above, the floor planner capable of outputting the wiring route information and the layout tool of the third embodiment which can read the information can determine the wiring route at the time of floor plan and the wiring length at the time of changing the wiring route. It becomes possible to place and route by reflecting with the layout tool. Also,
The same result as the result of the pre-wiring simulation can be obtained by the detailed simulation.

Embodiment 3. FIG. 3 also shows a third embodiment of the present invention. First, the wiring route information of the temporary wiring output from the floor planner shown in the second embodiment is read, and the wiring route of each wiring is wired in the same way as the wiring route at the time of floorplanning. Specifically, the cell 10 of FIG.
If the wiring connecting the cell 11 and the cell 11 is the wiring route of the route 8 at the time of floorplanning, this layout tool performs the wiring along the wiring route 8.

As a result, unless the wiring is changed, the wiring path can be the same as the temporary wiring path at the time of floorplanning. The flow is as shown in FIG. 4 as in the second embodiment. Further, when the floor planner outputs the wiring length corrected in the first embodiment and the layout tool reads the information and corrects the wiring route, it can be determined how long the wiring can be.

As described above, with the floor planner of the second embodiment capable of outputting wiring route information and wiring length information and this layout tool capable of reading the information, the wiring route at the time of floor plan is reflected in the layout tool. Placement and wiring can be performed. Further, the same result as the result of the pre-wiring simulation can be obtained by the detailed simulation.

Embodiment 4 A fourth embodiment of the present invention will be described with reference to FIG. First, after the cells are arranged by the floor planner as shown in FIG. 1, the floor planner reads the timing information of the net created by the timing verification and uses it for the evaluation of the arrangement. The wiring with no timing margin cannot change the wiring length because it causes a timing error due to the increase of the delay time due to the change of the wiring length.
Using this, all global boxes through which wiring with a small timing margin passes are evaluated as areas where wiring is difficult.

By this, the user refers to the evaluation result in which the two wiring areas, the area having a large number of wirings and the area where the wiring length cannot be changed, are set as the wiring dangerous area in the floor plan.
The validity of the arrangement can be improved. Figure 7 shows the flow
Shown in The flowchart is shown in FIG.

As described above, in the fourth embodiment, by adding the timing information to the evaluation element, it is useful for the user to find the wiring dangerous area when performing the floor plan.

[0029]

According to the first aspect of the present invention, since the wiring length of the wiring passing through the wiring difficult area is largely estimated, the timing error generated during the detailed simulation can be generated during the pre-wiring simulation.
It is effective in reducing the timing error of detailed simulation.

According to the second aspect of the invention, since the wiring route information is output in the floor planner, the wiring route in the floor planner and the wiring route / wiring length in the layout tool, and the results of the pre-wiring simulation and the detailed simulation match. It is effective in making it happen.

In the third aspect of the invention, since the layout tool can input the wiring route information output by the floor planner, the wiring route in the floor planner, the wiring route / wiring length in the layout tool, the pre-wiring simulation and the detailed simulation. It is effective in matching the results of.

According to the fourth aspect of the invention, since the floor planner is configured to add the timing information to the evaluation items, it is effective in improving the reliability of the floor planner placement evaluation.

[Brief description of drawings]

FIG. 1 is a partially enlarged view when a floor planner is executed.

FIG. 2 is a cell layout diagram (partial) at the time of floorplanning in the first embodiment.

FIG. 3 is a diagram showing an example of a wiring route in the second and third embodiments.

FIG. 4 is an execution flow chart of the second and third embodiments.

FIG. 5 is an execution flow diagram of the first embodiment.

FIG. 6 is a diagram showing a flowchart of the first embodiment.

FIG. 7 is an execution flow diagram of the fourth embodiment.

FIG. 8 is a diagram showing a flowchart of the fourth embodiment.

[Explanation of symbols]

1 Global box, 2-7 expected to be difficult to wire
Wiring, 8 · 9 wiring path, 10 · 11 cells.

Claims (4)

[Claims] 1. In the evaluation of the appropriateness of the layout in the layout work performed after the virtual simulation, the chip is divided into small grids, and the number of wirings in the grid is evaluated. A simulation method for placement and routing, which comprises estimating a wiring length of a wiring passing through a global box having a large number of wirings in a simulation performed using wiring length information obtained based on the placement information in the placement work. 2. A semiconductor placement and routing apparatus that receives placement information for placement work performed after virtual simulation from a floorplan execution device having an interface function and performs placement and routing, and cell placement information for the placement work and the placement work. If there is a correction of the wiring length in
A semiconductor placement and routing device, characterized by being received via the floor plan implementation device. 3. In a semiconductor placement and routing apparatus that receives placement information for placement work performed after virtual simulation from a floorplan execution device having an interface function and performs placement and routing, information on a route tentatively wired in the placement work, and A semiconductor placement and routing apparatus, which receives the wiring length when the wiring length is corrected in the placement work via the floorplan execution device. 4. The placement and routing, wherein timing information based on a timing verification result of each wiring is reflected as an evaluation element for determining a wiring danger area in the evaluation of the validity of the wiring placement in the placement work performed after the virtual simulation. Simulation method.