JPH0950397A - Access control method for ic memory card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize an IC memory card by making access plural first memory individually by transferring an address signal, a data signal and a command signal via a shared signal. SOLUTION: When a code value to give a desired command is recognized by a card reader/writer, the card reader/writer designates a first the memory 1 as access target with a command input mode (1). Thereby, a chip select circuit 3 is operated, which sets designated memory 1 in an operable state. Then, the card reader/writer sets a signal level corresponding to a command input mode (2), and gives the command to selected memory 1 with the data signal in first and second cycles. Then, the card reader/writer is moved into an address input mode, and sets the signal level corresponding to the mode, and also, transfers the address signals A0-A20 to the memory of access target in first to third memory 1 by using signal lines D0-D7 in three cycles.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access control method for an IC memory card which is removable from a card reader / writer and which reads / writes data according to instructions from the card reader / writer.

[0002]

2. Description of the Related Art Conventionally, in this type of IC memory card, it was necessary to internally lay out an address signal for instructing a memory storage address and a signal line for transferring a data signal to be read / written.

[0003]

Therefore, miniaturization of the IC memory card is limited.

Therefore, the present invention can contribute to miniaturization.
An object of the present invention is to provide an access control method for a C memory card.

[0005]

In order to achieve such an object, the invention of claim 1 sends an address signal from a card reader / writer through an address signal line, and outputs a data signal to be read and written. In an access control method of an IC memory card for accessing a memory in an IC memory card by transferring it via a data signal line, an address signal, a data signal and a command signal are received via a shared signal line, and the command signal is received. Are provided in the IC memory card, and a plurality of first memories for executing the memory-related processing instructed by the IC memory card are provided in the IC memory card. When accessing the card,
The address signal line and the data signal line on the card reader / writer side are connected to the chip select circuit on the IC memory card side, the data signal line on the card reader / writer side is connected to the shared signal line, and the card reader is connected. After the writer uses the address signal and the data signal to instruct the chip select circuit which memory is to be operable, the card reader / writer connects the data signal line on the card reader / writer side and the data signal line. It is characterized in that the plurality of first memories are individually accessed by transferring the address signal, the data signal and the command signal through a shared signal line on the side of the connected IC memory card.

According to a second aspect of the invention, a second memory for transferring an address signal through an address signal line and a data signal through a data signal line is further provided in the IC card memory card, and the second memory is provided with the command. A code value corresponding to the content of the signal is stored in advance in the second memory, and the address signal line and the data signal of the card reader / writer side and the second memory are stored prior to the access to the first memory. The lines are connected to each other, and the card reader / writer side reads the code value of the command signal written in the second memory by an address signal.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a circuit configuration of an IC memory card according to an embodiment of the present invention. In FIG. 1, the card reader / writer (not shown) and the IC memory card have the same connection terminal configuration as the conventional one, and the following signals are transferred. That is, WE
The / -PGM signal is a signal for setting the memories 1 and 2 in a writable state. The -OE signal is a signal instructing the read timing of the memory 1. D0-D7 are data signals. A0-A7 are address signals. RDY
The / BSY signal is a signal that instructs the reset circuit 4 to reset. Reference numeral 1 is a memory, which uses a memory that receives an address signal and a data signal in a time division manner. Therefore, the data signal input terminals of the memory 1 are connected to the data signal lines D0-D7, that is, the shared signal lines according to the present invention, and the address signal terminals do not exist in the memory 1. The other characteristic of this memory is that the commands shown in FIG.
When it is received through the data signal line of D7, the process instructed by the command is executed. However, there has been a problem that the code assigned to this command differs depending on the manufacturer of the memory. Therefore, in this embodiment, a command system (code value assigned to each command type) corresponding to the manufacturer is stored in the memory 2.
The first feature is that the command system can be read prior to accessing the memory 1. Secondly, the chip select circuit 3 to be described later selects one of the plurality of memories 1, and the card reader / writer can instruct which memory 1 to select by using an address signal.

Other signals transferred via the connection terminals are transferred to the memories 1 and 2. For the memory 2, a memory of a type in which an address signal and a data signal are separately input, that is, an address signal line and a data signal line are input is used. In this memory 2, as shown in FIG.
The code value to be assigned for each command type is described. This code value is given by the data signals D0-D7.

The chip select circuit 3 receives the address signal A1.
8-A19 and the data signals D0-D1 are discriminated, and CLE signal, ALE signal, CE00-CE03 are discriminated according to the discrimination result.
The signal is output to the memory 1 and the memory 2. The CE00 signal sets the memory 2 in an operable state. CE01-C
The E03 signal sets the corresponding memory 1 to the operable state. The CLE signal is a signal indicating that a command is sent to the data signals D0 to D7 when this signal is active. The ALE signal is a signal indicating that the address information is sent to the data signals D0-D7 when this signal is active. The reset circuit 4 is the entire circuit RD
Reset according to the Y / BSY signal. The -CE1 signal is a signal for setting the chip select circuit 3 in an operable state.

The operation of the IC memory card having such a configuration will be described with reference to FIGS. FIG. 2 is a table showing the level states of the above signals assigned to each operation mode. In the figure, L indicates a low level, H indicates a high level, and HI indicates a high impedance state. Figure 3 shows three memories 1
7 is a table showing the relationship between the memory selected in the table and the data signals D0-D7. FIG. 4 shows the value of the data signal and the address signal A18 to be assigned corresponding to the type of command.
It is a table showing the level contents of A19. FIG. 5 is a table showing the contents of the address information assigned to the data signals D0-D7 and the transfer timing. FIG. 6 shows the memory 2
Shows the stored contents of.

When the IC memory card is mounted on the card reader / writer, the address signal lines and data signal lines of the IC memory card and the card reader / writer are connected. After the power is reset, the card reader / writer designates the memory 2 by the address signals A0-A16, and instructs the reading of the command system by the -OE signal and the address signals A0-A19. Thereby, the chip select circuit 3
Causes the memory 2 to operate, so the code value of the command is read from the specified address of the memory 2,
The data signals D0 to D7 are output to the card reader / writer via the signal lines.

In this way, when the card reader / writer knows the code value designating the desired command, the card reader / writer first designates the memory 1 to be accessed in the command input mode (1). More specifically, the levels of the -CE1 signal, -WE / -PGM signal, and -OE signal are set as shown in FIG. 2, and the data signals D0-D are set as shown in FIG.
7. Determine the level of address signals A0-A19. As a result, the chip select circuit 3 operates to set the designated memory 1 to the operable state. The card reader / writer then sets the signal level of FIG. 2 corresponding to the command input mode (2) and gives a command to the selected memory 1 by the data signal in the first and second cycles (see FIG. 4). Next, the card reader / writer shifts to the address input mode, sets the signal level of FIG. 2 corresponding to this mode, and sets the address signal A0- for the memory to be accessed in the first to third memories 1. A20 is transferred in 3 cycles using the signal lines D0 to D7 according to the table of FIG. In the case of reading, the card reader / writer sets the signal level of the data output mode of FIG. 2 and receives the read data from the memory 1 of the access destination through the signal lines D0 to D7. In the case of writing, the data input mode of FIG. 2 is set. Finally, the card reader / writer cancels the memory selection by the signal setting in the command input mode (1) of FIG. 2 and ends the processing.

Since the memory 1 is selected by the chip select circuit 3 in this embodiment as described above, the number of bits of the address signal can be reduced as compared with a single memory having the same capacity. The number of bits of the data signals D0-D7 in FIG. 1 can be reduced. Further, since the instruction of the selected memory and the command instruction to the chip select circuit 3 can be transmitted from the card reader / writer side by using the address signal line and the data signal line similar to the conventional one, no circuit change is required on the card reader / writer side. You don't have to. Further, even if the command system of the memory 1 used in the IC memory card is different for each IC memory card, different types of IC memory cards can be obtained by reading the code value indicating the command system from the memory 2 prior to access. Can access. Also, by checking the command system on the card reader / writer side, an unrelated IC
The memory card can be eliminated.

[0015]

As described above, according to the invention of claim 1, since the data signal and the address signal are transferred by the shared signal line, the address signal line becomes unnecessary. Furthermore, the number of bits of the shared signal line can be reduced by individually accessing the plurality of memories. This can contribute to miniaturization of the IC memory card.

According to the second aspect of the present invention, even if the IC memory card has a different command system, the card reader / writer can read the contents of the command system and access can be performed according to the contents.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a table showing a correspondence relationship between operation modes and signal level contents of an IC memory card.

FIG. 3 is an explanatory diagram showing the relationship between the selected memory 1 and the contents of signal levels.

FIG. 4 is an explanatory diagram showing types of commands and code values and signal levels for instructing the commands.

FIG. 5 is an explanatory diagram showing a timing of transferring an address signal to a shared signal line.

FIG. 6 is an explanatory diagram showing stored contents of a memory 2.

[Explanation of symbols]

 1 memory 2 memory 3 chip select circuit

Claims (2)

[Claims] 1. An IC memory for accessing a memory in an IC memory card by transmitting an address signal from a card reader / writer via an address signal line and transferring a data signal to be read / written via the data signal line. In a card access control method, an address signal, a data signal, and a command signal are received via a shared signal line, and a plurality of first memories that execute a memory-related process instructed by the command signal, and a plurality of the memories. A chip select circuit for selectively operating is provided in the IC memory card, and when the card reader / writer accesses the IC memory card, an address signal line and a data signal line on the card reader / writer side are provided. And a chip select circuit on the IC memory card side, The data signal line on the side is connected to the shared signal line, and the card reader / writer uses the address signal and the data signal to instruct the chip select circuit which memory is to be enabled, and then the card reader / writer. The writer transfers the address signal, the data signal and the command signal via a data signal line on the card reader / writer side and a common signal line on the IC memory card side connected to the data signal line to transfer the address signals, the data signals and the command signals. An access control method for an IC memory card, characterized in that the first memory is individually accessed. 2. A second memory for transferring an address signal through an address signal line and a data signal through a data signal line is provided in the IC card memory card, and the second memory has a code corresponding to the content of the command signal. A value is stored in advance in the second memory, and the address signal line and the data signal line of the card reader / writer side and the second memory are connected to each other before the access to the first memory, 2. The access control method for an IC memory card according to claim 1, wherein the card reader / writer side reads the code value of the command signal written in the second memory by an address signal.