JPH0945923A - Thin-film transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the ratio of ON current to OFF current by setting an active region to a thickness where a depletion layer spreads in the thickness direction when a specific negative voltage is applied to a gate electrode. SOLUTION: In a thin-film transistor, an n-type impurity is doped to a gate electrode 2 for selectively coating the surface of a glass substrate 1, an active region 4A located at the upper portion of the gate electrode 2 of island-shaped undoped amorphous silicon film which crosses via a gate insulation film 3, and an amorphous silicon film at both sides. Then, the transistor has a pair of n-type source and drain regions 5-1A and 2A, a pair of source and drain electrodes 6-1A and 2A connected to that region, and an organic insulation film 8 for covering the entire surface. Therefore, by setting the thickness of the active region to a value which is depleted in the entire region in the thickness direction by a specific gate voltage, the formation of a channel on an interface further away from the gate electrode of the active region can be suppressed, thus drastically improving the ratio of ON current to OFF current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor using amorphous silicon used as a switching element of a pixel of a liquid crystal display device and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 8 shows a conventional commonly used thin film transistor. Such a thin film transistor is described in, for example, Japanese Patent Laid-Open No. 63-158875, but a gate electrode 2 that selectively covers the surface of the glass substrate 1 and a gate insulating film 3 are interposed between the gate electrode 2 and the gate electrode 2. The active region 4 above the gate electrode 3 of the island-shaped undoped amorphous silicon film intersecting with each other, and a pair of undoped amorphous silicon films on both sides of the active region 4 doped with n-type impurities. n-type source / drain regions 5-1 and 5
-2 and a pair of source / drain electrodes 6-1 and 6-2 connected to the n-type source / drain regions 5-1 and 5-2.
And a protective film 7 made of SiN _x or SiO ₂ for covering the active region 4. This protective film 7 is used as a mask when the undoped amorphous silicon film is doped with n-type impurities.

[0003]

The characteristic of the drain current I _D vs. the gate electrode V _{G of} such a conventional thin film transistor is as shown by the curve I in FIG. However, the drain voltage is 10 V, the channel length is 6 μm, and the channel width is 33 μm. The curve I shows the anomaly in the region where the gate electrode V _G is about −2 V or less. Due to this anomaly, the off current of the thin film transistor (for example, I _D when V _G = −5V) does not become small, and there is a problem that the on current to off current ratio cannot be made large.

Further, the presence of this protective film causes a problem that the unevenness of the surface of the thin film transistor becomes large, and the liquid crystal alignment is liable to be disturbed when used in a liquid crystal display device, resulting in poor display image quality.

Therefore, a first object of the present invention is to provide a thin film transistor having an improved on-current to off-current ratio and a method for manufacturing the same. A second object of the present invention is to provide a thin film transistor with less unevenness and a method for manufacturing the same.

[0006]

A first thin film transistor according to the present invention comprises a gate electrode for selectively covering the surface of an insulating substrate, and an island-shaped undoped non-doped non-doped non-doped gate electrode which intersects with the gate electrode via a gate insulating film. An active region above the gate electrode of the crystalline silicon film, and a pair of n-type source / drain regions formed by doping the undoped amorphous silicon film on both sides of the active region with an n-type impurity, A pair of source / drain electrodes connected to the n-type source / drain regions and an organic insulating film covering the entire surface including the active region are provided, and the active region applies a predetermined negative voltage to the gate electrode. The thickness is set so that the depletion layer spreads in the thickness direction when applied.

Here, the organic insulating film is preferably a polyimide film.

A second thin film transistor of the present invention comprises a gate electrode which crosses the surface of an undoped amorphous silicon film selectively covering an insulating substrate with a gate insulating film interposed therebetween.
An active region formed of the undoped amorphous silicon film directly above the gate electrode, and a pair of n-type source / drain regions formed by doping the undoped amorphous silicon film on both sides of the active region with an n-type impurity. In the thin film transistor having, the active region is set to a thickness such that the depletion layer spreads in the thickness direction when a predetermined negative voltage is applied to the gate electrode.

The thickness of the active regions of the first and second thin film transistors is specifically at most 60 nm.

A first method of manufacturing a thin film transistor according to the present invention comprises a step of forming a gate electrode for selectively covering the surface of an insulating substrate, a step of depositing a gate insulating film on the entire surface,
An undoped amorphous silicon island shape intersecting with the gate electrode is formed by depositing and patterning an undoped amorphous silicon film having a thickness of at most 60 nm by a glow discharge plasma CVD method using a mixed gas of SiH ₄ gas and H ₂ gas. A step of forming a high-quality silicon film and a mask covering the island-shaped undoped amorphous silicon film immediately below the gate electrode are formed, and then n-type impurity ions are implanted into the undoped amorphous silicon film and annealed. Forming a pair of n-type source / drain regions, forming a pair of source / drain electrodes respectively connected to the pair of n-type source / drain regions, and forming an organic insulating film on the entire surface by a printing method. It has a process and. Here, the organic insulating film is preferably a polyimide film.

Since a negative gate voltage which gives off current depletes the entire active region, there is no abnormal current due to fixed charges in the organic insulating film.

[0012]

1 (a) is a plan view showing a first embodiment of a thin film transistor of the present invention, and FIG. 1 (b) is a sectional view taken along line XX of FIG. 1 (a). However, FIG.
For convenience, the organic insulating film is not shown.

In this thin film transistor, a gate electrode 2 made of a Cr film for selectively covering the surface of the glass substrate 1 and an island-shaped undoped amorphous silicon film intersecting the gate electrode 2 with a gate insulating film 3 interposed therebetween. 4A above the gate electrode 2, and a pair of n-type source / drain regions 5-1A formed by doping the above-mentioned undoped amorphous silicon film on both sides of the active region 4A with n-type impurities.
5-2A and n-type source / drain regions 5-1A, 5-
2A pair of source / drain electrodes 6-1 connected to 2A
A, 6-2A, and an organic insulating film 8 made of a polyimide film that covers the entire surface including the active region 4A.
Means that when a predetermined negative voltage is applied to the gate electrode 2, the depletion layer spreads in the thickness direction thereof.

Here, the undoped amorphous silicon film is S
It is formed by a glow discharge plasma CVD method using a mixed gas of iH ₄ gas and H ₂ gas. The term undoped means intentionally not introducing impurities.

In FIG. 1, the source / drain electrodes 6-1 are shown.
Although A and 6-2A do not overlap the gate electrode 2, they may partially overlap as shown in FIG.

Next, a manufacturing method according to the first embodiment of the present invention will be described.

First, as shown in FIG. 3A, a Cr film is deposited on a glass substrate 1 by a sputtering method and patterned by a lithography method to form a gate electrode 2. Next, a silicon nitride film is deposited as the gate insulating film 3 by the plasma CVD method. Next, an undoped amorphous silicon film 9 having a thickness of 60 nm or less, for example, 50 nm is deposited at a substrate temperature of 300 ° C. by a glow discharge plasma CVD method using a mixed gas of SiH ₄ gas and H ₂ gas, and a lithographic method is used. Pattern in an island shape (rectangular shape). next,
As shown in FIG. 3B, a resist film 10 is formed above the gate electrode 2. Next, with the resist film 10 remaining, phosphorus is implanted at a accelerating voltage of 20 kV and a dose of about 5 × 10 ¹⁵ / cm ² from the direction shown by the arrow. After the ion implantation, the resist film 10 is peeled off and annealed to remove the n-type source.
Drain regions 5-1A and 5-2A are formed. Immediately below the resist film 9, a non-doped amorphous silicon film remains as the active region 4A.

After that, a dilute hydrofluoric acid treatment is performed to remove the natural oxide film on the silicon surface, and then a Cr film is deposited by a sputtering method and patterned by a lithography method to form a source.
The drain electrodes 6-1A and 6-2A are formed, and then a polyimide film having a thickness of 50 nm is formed as the organic insulating film 8 by a printing method. The polyimide film protects the active region and can be used as an alignment film for a liquid crystal display device.

FIG. 4 is a graph showing the drain current I _D vs. gate voltage V _G characteristics of the thin film transistor according to the first embodiment of the present invention. Curve I shows the characteristic of the conventional example (the thickness of the active region is 180 nm), and curve II shows the characteristic of the first embodiment of the present invention. However, the channel length is 6μ in both cases.
m, the channel width is 33 μm, and the drain voltage is 10V. The curve II does not show the anomaly like the curve I, and the on-current (for example, I _D when V _G = 10 V) versus the off-current (for example, I _D when V _G = −5 V) is significantly improved. I know that

FIG. 5 is a band diagram for explaining the off current of the thin film transistor, FIG. 5 (a) shows a conventional example, and FIG. 5 (b) shows the first embodiment of the present invention.

First, FIG. 5A will be described. It is assumed that a negative voltage is applied to the gate electrode. A part of the non-doped amorphous silicon film 4 is depleted across the gate insulating film 3. At this time, the range where the curve showing the energy E _C of the conduction band and the energy E _V of the valence band of the non-doped amorphous silicon film 4 is distorted by the electric field from the gate electrode is from the gate insulating film to the depletion layer width W. Similar band bending may occur on the protective film 7 side.
That is, although there is no electrode on the protective film 7, since positive fixed charges Q due to ions or the like exist, negative electrons are induced in the protective film 7 and the non-doped amorphous silicon film 4. This phenomenon causes the thin film transistor I _D to V _G
The characteristic is that the gate voltage V _G is −1 as shown by the curve I in FIG.
An abnormal current increase is seen from 0V to around 0V.

On the other hand, consider a case where the thickness T2 of the non-doped amorphous silicon film is smaller than the depletion layer width W as shown in FIG. In this case, the energy E _C of the conduction band and the energy E _{V of the} valence band of non-doped amorphous silicon
The electric field generated by the gate electrode 2 extends to the surface of the non-doped amorphous silicon on the opposite side and is not easily affected by the positive fixed charges, so that electrons are not induced near the surface.

The width W of the depletion layer depends on the gate voltage V _G , the film quality of the non-doped amorphous silicon film and the fixed charge amount in the protective film. The off-current may theoretically be the drain current when the gate voltage V _G is sufficiently negative, but in practice it has a certain gate voltage, for example −5V.
The drain current _{ID at} that time is referred to as an off current. Therefore, the thickness may be such that V _G has a certain value in the range of 0 to −5 V and the active region is depleted in the thickness direction.

In the conventional example of FIG. 8, the protective film 7 is an n-type source.
Since it is used as a mask for ion implantation of phosphorus or the like to form the drain regions 5-1, 5-2, it is considered that a large amount of positive fixed charges exist. In the case of the present invention, as described above, the organic insulating film is provided after the n-type source / drain regions are formed, and it is not necessary to consider the increase in fixed charges due to ion implantation.

FIG. 6 is a graph showing an actual measurement example of the localized level density N (E) of the non-doped amorphous silicon film in the first embodiment of the present invention. The drain current I _D is I _D
= I ₀ exp (−ΔE / kT). Where I ₀ is a constant, ΔE is the activation energy, k is the Boltzmann constant, and T is the absolute temperature. The activation energy ΔE can be obtained by measuring the drain current at various temperatures from this equation, and the gate voltage dependence of ΔE is measured, the calculation method is often found in textbooks of semiconductor engineering, so it is omitted. However, the localized level density N (E) at each energy position (E _C −E) below the energy E _C of the conduction band can be obtained. The figure shows the results thus obtained. For example, the localized level density N is 0.2 eV below the conduction band energy E C.
(E) is about 10 ¹⁷ (eV · cm ³ ) ⁻¹ . In the non-doped amorphous silicon film, the localized level creates space charges, and thus N (E) affects the width W of the depletion layer. The abnormality described above to the gate voltage V _G characteristics is not observed were confirmed - drain current I _D within the thickness of non-doped amorphous silicon film is 30~60nm in the first embodiment of the present invention .

Since the unevenness based on the protective film 7 in the TFT of FIG. 8 does not exist in the first embodiment of the present invention, the disorder of the liquid crystal alignment when used in the liquid crystal display device can be reduced.

The organic protective film is not limited to the polyimide film, and any film used in the semiconductor field can be used.

FIG. 7 is a sectional view showing a second embodiment of the present invention.

Although this figure shows a forward stagger type thin film transistor, the active region 4 made of a non-doped amorphous silicon film is used.
The thickness 4B of B is 60 nm or less, for example 50 nm, so that the gate voltage V _G is depleted at a voltage of 0 to −5 V over the entire thickness direction.

Further, in this thin film transistor, the gate electrode 2A and the gate insulating film 3A are patterned into an island shape, and then phosphorus is doped by an ion implantation method to form a non-doped amorphous silicon film in the n-type source / drain region 6-1B.
6-2B is formed, but since the thickness of the non-doped amorphous silicon film is as thin as 60 nm or less, n-type is formed up to the vicinity of the interface in contact with the source / drain electrode, and the amorphous silicon film and the metal film (source / drain electrode) are formed. ) Gives good ohmic contact. Since the gate electrode 2A is deposited on the gate insulating film 3A at the time of ion implantation, the fixed charge due to phosphorus is smaller than that of the inverted stagger type.

The off current can be reduced as in the first embodiment.

[0032]

As described above, by setting the thickness of the active region of the amorphous silicon thin film transistor to be equal to or less than the value depleted in the entire thickness direction at a predetermined gate voltage,
Since it is possible to suppress the formation of a channel at the interface farther from the gate electrode in the active region, the on-current to off-current ratio can be greatly improved. Further, in the inverted staggered thin film transistor, the surface of the upper portion of the gate electrode in the active region is covered with SiN _x or Si.
By directly covering the entire surface with an organic insulating film such as a polyimide film without selectively covering with a protective film such as an O ₂ film, it is possible to reduce unevenness and contribute to the improvement of image quality when used in a liquid crystal display device. Since the organic insulating film also serves as the alignment film, the number of steps can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view (FIG. 1A) also showing a thin film transistor according to a first embodiment of the present invention and a cross-sectional view taken along line XX of FIG. 1A (FIG. 1B).

FIG. 2 is a cross-sectional view showing a modification of the thin film transistor according to the first embodiment.

3A to 3C are cross-sectional views in order of the processes, which are divided into (a) to (c) for describing the manufacturing method according to the first embodiment.

FIG. 4 is a graph showing a drain current _ID -gate voltage V _G characteristic of the thin film transistor of the first embodiment in comparison with a conventional example.

FIG. 5 is a band diagram for explaining a conventional example (FIG. 5A) and the thin film transistor of the first embodiment (FIG. 5B).

FIG. 6 is a graph showing an actual measurement example of a localized level density distribution of the non-doped amorphous silicon film according to the first embodiment.

FIG. 7 is a sectional view showing a thin film transistor according to a second embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a conventional thin film transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Glass substrate 2,2A Gate electrode 3,3A Gate insulating film 4,4A, 4B Active region 5-1,5-1A, 5-1B, 5-2,5-2A, 5-
2B n-type source / drain regions 6-1, 6-1A, 6-1B, 6-2, 6-2A, 6-
2B source / drain electrode 7 protective film 8 organic insulating film 9 non-doped amorphous silicon film 10 resist film

Claims (6)

[Claims] 1. A gate electrode that selectively covers the surface of an insulating substrate, and an island-shaped undoped amorphous silicon film above the gate electrode that intersects with the gate electrode via a gate insulating film. An active region, a pair of n-type source / drain regions formed by doping the undoped amorphous silicon film on both sides of the active region with an n-type impurity, and a pair connected to the n-type source / drain regions. Source / drain electrodes and an organic insulating film covering the entire surface including the active region, and a depletion layer expands in the thickness direction of the active region when a predetermined negative voltage is applied to the gate electrode. A thin film transistor characterized by being set to a thickness. 2. The thin film transistor according to claim 1, wherein the organic insulating film is a polyimide film. 3. A gate electrode that traverses the surface of an undoped amorphous silicon film that selectively covers an insulating substrate via a gate insulating film, and the undoped amorphous silicon film immediately below the gate electrode. In a thin film transistor having an active region and a pair of n-type source / drain regions formed by doping the undoped amorphous silicon film on both sides of the active region with an n-type impurity, the active region is the gate electrode. A thin film transistor having a thickness such that a depletion layer spreads in the thickness direction when a predetermined negative voltage is applied to the thin film transistor. 4. The thin film transistor according to claim 1, wherein the thickness of the active region is at most 60 nm. 5. A step of forming a gate electrode for selectively covering the surface of an insulating substrate, a step of depositing a gate insulating film on the entire surface, and a glow discharge using a mixed gas of SiH ₄ gas and H ₂ gas. Depositing an undoped amorphous silicon film having a thickness of at most 60 nm by plasma CVD and patterning it to form an island-shaped undoped amorphous silicon film that intersects with the gate electrode; and the island-shaped undoped amorphous film. After forming a mask covering just above the gate electrode of the crystalline silicon film, an n-type impurity ion is implanted into the undoped amorphous silicon film and annealed to form a pair of n-type source.
A step of forming a drain region, a step of forming a pair of source / drain electrodes respectively connected to the pair of n-type source / drain regions, and a step of forming an organic insulating film on the entire surface by a printing method. A method of manufacturing a thin film transistor having the characteristics. 6. The method of manufacturing a thin film transistor according to claim 5, wherein the organic insulating film is a polyimide film.