JPH0945856A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a field MOS transistor to serve as an input/output protective device by a method wherein a gate oxide film is composed of a first part as thick as a field oxide film and a second part which is locally set thin between a source and a drain. SOLUTION: Thick oxide films 15 and 15A as thick as 500nm or so are formed on a P-type silicon substrate 11 except on a part of the silicon substrate 11 under the wide lateral parts 13D and 13S of an SiN film 13. A thin oxide film 16 as thick as 300nm (thinner than field oxide film) is formed under the bridge 13G of the SiN film 13 by oxidation induced by oxygen fed from crosswise sides (Y direction). In a field MOS transistor, the oxide film 16 is thinner than the field oxide film 15, so that a threshold voltage is 8 to 9V lower under the thin oxide film 16 than under the oxide film 15A of the same thickness with the field oxide film 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having an input / output protection element and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, power supply voltage has been decreasing due to miniaturization and low power consumption of semiconductor devices. However, since semiconductor devices having conventional power supply voltages are still mainstream, semiconductor devices having different power supply voltages are mixed in the same system, board, and the like.

For example, even if the power supply voltage of a certain type of semiconductor device is lowered from 5V to 3.3V, the power supply voltage of many other types of semiconductor devices remains 5V, and both are used in combination. I have to do it.

For this reason, for example, a semiconductor device having a so-called 5V-3.3V interface in which a power supply voltage of an internal circuit is 3.3V and a 5V signal is input / output to / from its input / output portion is required. Become.

Since the internal circuit of such a semiconductor device has a low power supply voltage of 3.3 V, the gate oxide film of the insulated gate field effect transistor (hereinafter referred to as MOS transistor) constituting the internal circuit is 10 nm. The front and rear thin films are used to improve performance.

However, since a signal as high as 5 V is generated in the input / output section, the thickness of the gate oxide film of the MOS transistor as an input / output protection element connected to the input / output section is made thin like the MOS transistor in the internal circuit. I can't.

Therefore, a MOS transistor using a thick field oxide film as a gate oxide film is used as an input / output protection element (hereinafter, this MOS transistor will be referred to as
Field MOS transistor).

Field M as this input / output protection element
When noise charges such as positive ESD enter, the OS transistor receives a field MO between the signal line and GND.
The drain-gate voltage of the S-transistor rises to some extent, and a current begins to flow above the threshold voltage (VT) of this transistor, and when the drain-gate voltage rises to reach the snapback voltage, the snapback phenomenon causes a sudden drain current. Is increased to release the charge to GND and protect the MOS transistor forming the internal circuit.

An example of a conventional field MOS transistor will be described with reference to FIGS. 7 to 9 by its manufacturing method.

A SiO ₂ film (silicon oxide film) 22 having a thickness of about 50 nm is formed on the main surface of the P-type silicon substrate 21 by thermal oxidation.
(FIG. 7 (A)), a SiN film (silicon nitride film) 23 having a thickness of about 300 nm is grown thereon by a CVD method (FIG. 7 (B)), and a resist pattern 24 having an opening 24K is formed. It is formed by photolithography technology or the like (FIG. 7).
(C)).

A plan view of only the resist pattern 24 is shown in FIG. In the steps of FIGS. 8A and 8B,
Using the resist pattern 24 as a mask, the SiN film 23 and the SiO ₂ film 22 are selectively removed by dry etching, and the surface portion of the P-type silicon substrate 21 exposed by the etching is etched to form a recess 21T. Note that FIG. 8B is a cross-sectional view of a portion D-D in FIG. 8A.

Next, after removing the resist pattern 24,
Using the remaining SiN film 23 as a mask, heat treatment is performed at about 1000 ° C. in an oxidizing atmosphere to form a field oxide film 25 having a thickness of about 500 nm (FIG. 9A). This field oxide film 25 partitions the formation region of the firuled MOS transistor and constitutes the gate oxide film of this transistor, and also partitions the respective MOS transistor formation regions of the internal circuit. In FIG. 9, the field oxide film 2
5 shows a portion functioning as a gate oxide film. Then, the SiN film 23 used as a mask when forming the field oxide film and the SiO ₂ film 22 thereunder are removed to form a thin gate oxide film and a polysilicon gate electrode of the MOS transistor in the internal circuit, and N-type impurities are ion-implanted using the oxide film 25 as a mask, and an N-type diffusion layer is formed by activation heat treatment. FIG.
The pair of N-type diffusion layers 27 shown in FIG.
It becomes the source and drain of the transistor. Next, the interlayer insulating film 28 is formed, and the contactor holes 2 required there are formed.
After forming 8C, metal electrode wiring is formed. FIG.
(C) is a gate metal electrode 29 formed by this metal electrode wiring
The field MOS transistor 20 as a protective element having G, a source metal electrode 29S, and a drain metal electrode 29D is shown.

Referring to FIG. 10, a CMOS having a P-channel type MOS transistor 30 and an N-channel type MOS transistor 40 each having a thin gate oxide film in the internal circuit is formed.
Is connected between a low-voltage (+ 3.3V) power supply line and a ground line, and is provided between the input / output terminal (pad) 60 to which + 5V is applied and the gate of the CMOS, and the gate of the low-voltage protection part. An N-channel type MOS transistor 50, which is applied to the V.sub.3 and acts as a level shift from 5V to 3.3V, is inserted.

The protection section is provided with a pair of field MOS transistors 20 described in FIGS. 7 to 9 connected between a high voltage (+ 5V) power supply line and a ground line.

[0015]

As described above, in the recent semiconductor device, the MOS which constitutes the internal circuit is miniaturized with the miniaturization.
The junction breakdown voltage BVj of the transistor is, for example, 10
This value decreases to V, and this value becomes a threshold voltage VT ₂ of the field MOS transistor as an input / output protection element, for example, 16V.
Lower. For this reason, as shown in FIG. 11, when noise is applied to the input / output portion, a junction breakdown occurs in the internal circuit before the current starts flowing through the field MOS transistor and the protection action is performed, resulting in the field MO.
There is a problem that the S transistor cannot function as an input / output protection element.

Therefore, an object of the present invention is to reduce the junction breakdown voltage BVj due to the miniaturization of the internal circuit MOS.
Field MOS that can protect transistor
A semiconductor device using a transistor as an input / output protection element and a method for manufacturing the same.

[0017]

A feature of the present invention is to have an input / output terminal, an internal circuit, and a protective element provided between the input / output terminal and the internal circuit. ,
A pair of N-type diffusion layers surrounded by a field oxide film formed on a semiconductor substrate are used as a source and a drain, and oxidation formed on the substrate between the source and the drain is continuous with the field oxide film. In a semiconductor device having a structure of an insulated gate field effect transistor in which a film is a gate oxide film and a conductive film thereon is a gate electrode, the gate oxide film is a first film having the same film thickness as the field oxide film. And a second portion that is locally thinned between the source and the drain. Here, it is preferable that a plurality of the second portions are arranged in a direction perpendicular to the source-drain direction.

Another feature of the present invention is to selectively oxidize the semiconductor substrate by using the oxidation resistant film pattern provided on the semiconductor substrate as a mask, thereby forming a thick field oxide film and a thick first gate oxide film. A manufacturing method for manufacturing a semiconductor device in which a portion and a thin second portion are formed at the same time.

As described above, since the gate oxide film of the field MOS transistor as the protection element of the present invention is provided with a thin portion, its threshold voltage (VT) is lowered, and therefore noise lower than BVj of the MOSO transistor in the internal circuit is reduced. Since the current of the field MOS transistor starts to flow due to the voltage and a snapback phenomenon occurs, the MOSO transistor in the internal circuit can be protected. In addition, by arranging a plurality of these thin portions, the amount of current that can flow increases, and the ESD tolerance increases.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

1 to 4 are views showing manufacturing of a field MOS transistor in a semiconductor device according to an embodiment of the present invention.

First, in FIG. 1A, a SiO ₂ film (silicon oxide film) 12 having a film thickness of about 50 nm is formed on the main surface of a P-type silicon substrate 11 by, for example, a thermal oxidation method.

Next, referring to FIG. 1B, a SiN film (silicon nitride film) 13 having a thickness of about 300 nm is formed on the SiO ₂ film.
Are formed by, for example, the CVD method.

Next, in FIG. 1C, a resist pattern 14 having an opening 14K is formed on the SiN film 13 by a photolithography technique or the like.

As shown in FIG. 2A, the resist pattern 14 has a left side portion 14D, a right side portion 14S, and a plurality of (five in the figure) bridge portions 14G between the left and right portions 14D and 14S. ing. Each bridge portion 14G has a width (dimension in the Y direction) of about 0.4 μm and a length L.
(Dimension in the X direction that is the channel length) is 0.5
It has a rectangular planar shape of μm to 1.0 μm, and is arranged in the Y direction at regular intervals. The width W (dimension in the Y direction) of the left and right portions 14D and 14S is 100 μm.
２００200 μm.

In the steps of FIGS. 2A and 2B,
The SiN film 13 and the SiO ₂ film 12 are selectively removed by dry etching using the resist pattern 14 as a mask, and the surface portion of the P-type silicon substrate 11 exposed by the dry etching is etched to form a recess 11T. Note that FIG. 2B is a cross-sectional view taken along the line AA of FIG.

Next, in FIGS. 3A, 3B, and 3C, after the resist pattern 14 is removed, the remaining Si is left.
The pattern of the N film 13 is used as a mask in an oxidizing atmosphere for 10
Heat treatment at 00 ° C. is performed. The left and right portions 14D and 14S of the resist pattern 14 and the left and right portions 13D and 13S and the bridge portion 13G of the same planar shape as the bridge portion 14G are formed in the pattern of the SiN film 13.

By this heat treatment, a thick oxide film 1 having a thickness of about 500 nm is formed in the portion of the P-type silicon substrate 11 where the SiN film 13 is not formed, that is, in the recess 11T.
5, 15A are formed. Further, this thick oxide film is not formed at the portions of the P-type silicon substrate 11 below the wide left and right portions 13D and 13S of the SiN film 13. But SiN
Below the bridge portion 13G of the film 13, the width direction (Y direction)
The film thickness is about 30 because it is oxidized only by oxygen from both sides of
A thin oxide film 16 of 0 nm (thinner than the field oxide film 15) is formed. That is, a thick silicon oxide film is formed as the field oxide film 15 so as to surround the wide left and right portions 13D and 13S of the SiN film 13, and the bridge portion 13 is formed between the wide left and right portions 13D and 13S of the SiN film 13.
A thick portion 15A of the gate oxide film having a thickness of about 500 nm, which is the same as the field oxide film 15, is formed in a portion where G does not exist, and a thickness of about 300 n is formed under the bridge portion 13G.
A thin portion 16 of m gate oxide is formed.

In FIG. 3, (B) is B- of (A).
It is sectional drawing of B part, (C) is sectional drawing of CC section of (A).

In the series of steps shown in FIGS. 1 to 3, the thick field oxide film 15 is formed so as to partition the MOS transistor formation region forming the internal circuit even in the internal circuit region of the same substrate.

Next, referring to FIG. 4A, the SiN film 13 is formed.
And the SiO ₂ film 12 is removed to form an internal circuit M
Ion implantation for controlling the threshold voltage of the OS transistor, formation of a gate oxide film having a film thickness of 10 nm, and formation of a polysilicon gate electrode are performed in the region of the internal circuit, and then the field oxide film 15, the thick gate oxide film 15A and the thin film are formed. N-type impurities are ion-implanted using the gate oxide film 16 as a mask, and a pair of N-type diffusion layers 17 and 17 serving as the source and drain of the field MOS transistor are formed on the left and right wide portions 13D of the SiN film 13 by activation heat treatment. , 1
It is formed on the substrate where 3S was present. In addition, by ion implantation of this N-type impurity and activation heat treatment, the source of the N-channel type MOS transistor forming the internal circuit,
A drain region is also formed.

Next, in FIG. 4B, the film thickness is about 1 μm.
m interlayer insulating film 18 is deposited by, for example, a CVD method, and contact holes 18C and 18C reaching the pair of N type diffusion layers 17 and 17, respectively, are formed therein, and the film thickness is about 500 nm.
A metal film such as an aluminum film is deposited by, for example, sputtering, and the metal film is patterned by a photolithography technique or the like to form the metal wiring 19. This metal wiring 1
9 is an N-type diffusion layer 17 through a contact hole 18C,
Source and drain electrode wirings 19 connected to 17 respectively
S, 19D and gate electrode wiring 19G.
As a result, the field MOS transistor 10 as a protection element is obtained. Further, in this series of steps, an interlayer insulating film, a contact hole and a metal wiring are simultaneously formed in the area of the internal circuit to form a circuit as shown in FIG.

FIG. 5 uses the protective element 20 of the present invention in place of the conventional protective element 20 of FIG.

In the field MOS transistor 10 according to this embodiment, the pair of N-type diffusion layers 17 and 17 are used as a source and a drain, and the oxide films 15A and 16 between them are used as a gate oxide film, and the gate electrode of the metal wiring thereon is formed. Wiring 17
G is used as a gate electrode, but since the oxide film 16 is thinner than the field oxide film 15, the field oxide film 15
The threshold voltage under the thin oxide film 16 is lower than that under the same oxide film 15A as, for example, 8 to 9V.

Therefore, the channel region of the field MOS transistor 10 is a portion set by the plurality of bridge portions 13G of the SiN film 13.

For example, when the MOS transistor forming the internal circuit is miniaturized, the junction breakdown voltage (Bvj) is about 10 V, and a general field oxide film, that is, the field oxide films 15 and 15A and the conventional field oxide film. Although the threshold voltage of the film 25 is about 16 V, it is not suitable for the protective action, but the threshold voltage VT of the channel region by the thin oxide film 16 having the stripe shape of the present invention is not suitable.
₁ becomes 8V-9V, and as shown in FIG.
It becomes lower than the junction withstand voltage BVj of the OS transistor, and a snapback phenomenon occurs at a voltage below this withstand voltage BVj, and a large amount of drain current starts to flow.
The MOS transistor in the internal circuit of FIG. 5 can be protected from junction breakdown.

Further, if the number of the plurality of thin oxide films 16 is increased, the effective width of the entire channel region of the field MOS transistor is increased, and the current that can be passed is increased, so that the ESD resistance is increased. Become.

That is, since the thin portion 16 of the gate oxide film is formed at the same time as the normal thick field oxide film 15, the width of each thin oxide film 16 has an appropriate film thickness (the film thickness for the normal thick field oxide film 15). ), That is, the conditions for obtaining an appropriate threshold voltage VT ₁ .
Therefore, it is necessary to set the number in order to obtain the expected required ESD tolerance.

[0039]

As described above, in the field MOS transistor as the input / output protection element of the semiconductor device of the present invention, the oxide film serving as the gate oxide film is locally thinned in the W direction (channel width direction). However, since the threshold voltage is lowered by the thinned portion, the voltage entering the snapback of this field MOS transistor is also lowered.

Therefore, the snapback voltage can be set lower than the junction breakdown voltage (Bvj) of the MOS transistor forming the internal circuit, and the input / output protection is performed before the MOS transistor forming the internal circuit is destroyed. The field MOS transistor of the device enters the snapback, and the noise charge such as EDM can be released, and the noise resistance is improved.

Further, in the structure in which the field oxide film is locally thinned in the W direction, the field oxide film can be formed simultaneously with the original formation of the field oxide film. Therefore, the number of manufacturing steps can be increased by adopting the structure of the present invention. There is no.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

2A and 2B are diagrams showing a process following that of FIG. 1, in which FIG. 2A is a plan view and FIG. 2B is a cross-sectional view taken along the line AA of FIG.

3A and 3B are diagrams showing a process following that of FIG. 2, in which FIG. 3A is a plan view, FIG. 3B is a cross-sectional view taken along the line BB in FIG. 3A, and FIG. It is sectional drawing of a part.

4A to 4C are cross-sectional views sequentially showing a step following the step of FIG.

FIG. 5 is a circuit diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a diagram showing IV characteristics of the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a method of manufacturing a semiconductor device of the related art in the order of steps.

8A and 8B are diagrams showing a process following that of FIG. 7, in which FIG. 8A is a plan view and FIG. 8B is a cross-sectional view taken along line DD of FIG.

FIG. 9 is a cross-sectional view showing a step subsequent to FIG. 8 in order;

FIG. 10 is a circuit diagram showing a conventional semiconductor device.

FIG. 11 is a diagram showing an IV characteristic of a conventional semiconductor device.

[Explanation of symbols]

11, 21 P-type silicon substrate 11T, 21T P-type silicon substrate recess 12, 22 SiO ₂ film 13, 23 SiN film 14, 24 Resist pattern 14K, 24K Resist pattern opening 15, 25 Thick field oxide film 15A Gate oxide Thick film portion (same thickness as the field oxide film) 16 Gate oxide film thin portion 17,27 N-type diffusion layer (source, drain) 18,28 Interlayer insulating film 18C, 28C Contact formed in the interlayer insulating film Hole 19G, 29G Metal gate electrode 19S, 29S Metal source electrode wiring 19D, 29S Metal drain electrode wiring

Claims (3)

[Claims] 1. An input / output terminal, an internal circuit, and a protection element provided between the input / output terminal and the internal circuit, wherein the protection element is a field formed on a semiconductor substrate. A pair of N-type diffusion layers surrounded by an oxide film are used as a source and a drain, and an oxide film formed on the substrate between the source and the drain in succession with the field oxide film is used as a gate oxide film, and above that. In a semiconductor device having a structure of an insulated gate field effect transistor using the conductive film of (1) as a gate electrode, the gate oxide film includes a first portion having the same film thickness as the field oxide film, the source and the drain. And a second portion that is locally thinned over the space. 2. The semiconductor device according to claim 1, wherein a plurality of the second portions are arranged in a direction perpendicular to the source-drain direction. 3. The field oxide film and the first and second portions of the gate oxide film are selectively oxidized by using the oxidation resistant film pattern provided on the semiconductor substrate as a mask. A method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed simultaneously.