JPH0945097A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a stable operation in a wide voltage range and at a high voltage by switching over a potential level of logical conversion in response to supply of a high voltage test signal being activated in correspondence to an excess over a set voltage value of a supply voltage. SOLUTION: A redundant memory selecting circuit comprises a redundant memory address setting circuit 2, a precharge circuit 3, an inverter 11, transistors Q5 and Q6, a contact MS and a burn-in test signal BT. The redundant memory address setting circuit 2 is activated in correspondence to an excess over a set value of a supply voltage Vcc. The precharge circuit 3 switches over an operation level of logical conversion of the potential of an inversion memory signal (ms) into the potential of a memory selection signal(msb), in response to supply of the burn-in test signal BT. By this constitution, a stable operation is obtained in a wide voltage range and at a high voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory having a redundant memory cell array.

[0002]

2. Description of the Related Art In recent years, semiconductor memories have been highly integrated,
It is common to have a redundant memory cell array for replacing defective cells due to manufacturing defects in order to improve yield.

As described in the LSI Handbook, edited by the Institute of Electronics and Communication Engineers, pp. 495-496 (Ohm Co., Ltd., 1984), this type of redundant configuration usually includes a row.
Alternatively, each column has a redundant memory cell array. This is because line defects often occur even with a single defect, and this is easier to handle on a circuit and a layout. There is also one that switches in block units of the cell array.

Taking a case where a redundant memory cell array is provided for each column as an example, a defect is to be provided in each line of the regular memory cell array (regular memory cell array), and the column should be switched to a column corresponding to the redundant memory cell array (redundant column). The fuse of the defective line including is cut off by cutting, and its address is programmed in the ROM provided on the chip. At the same time, the decoder of the redundant column is also programmed by using the fuse ROM or the like. During memory operation, the address is compared with the contents of the ROM, and if the address matches the address of the defective line, the redundant column is operated and at the same time access to the normal memory cell array is prohibited.

A diagram showing a circuit diagram of a conventional redundant memory cell of this type and a redundant memory selection circuit of a first semiconductor memory having a selection circuit for selecting a column selection line for selecting the redundant memory cell. Referring to FIG. 9 (A), the conventional first semiconductor memory includes a redundant memory address setting circuit 2 for setting address information of a redundant memory cell array to be selected in response to supply of an address signal, and a node M.
The precharge circuit 1 which is inserted between S and the power supply and which generates the inverted memory selection signal ms at the node MS by the connection state of the fuses F1 to F4 of the redundant memory address setting circuit 2 and the address signal, and the input terminal are An inverter I1 connected to the node MS for inverting the inverted memory selection signal ms and outputting the memory selection signal msb.

In the precharge circuit 1, the drain has a node M.
The source of S is connected to the power source Vcc and the inverted memory selection signal m
A transistor Q5 that outputs s is provided.

Redundant memory address setting circuit 2 has transistors Q1 to Q4 to which respective gates are respectively supplied with signals A1a, A1b, A2a and A2b which are true complements of respective bits of address signals A1 and A2, and one end of each of them. Is connected to the respective drains of the transistors Q1 to Q4, and the other end of each is commonly connected as a node MS to form a fuse F1.
To F4.

Next, the operation of the conventional semiconductor memory will be described with reference to FIG. 9A when the defective memory cell exists in the normal memory cell array (not shown) in the redundant memory address setting circuit 2. A predetermined fuse among the fuses F1 to F4 is cut according to the address of the defective memory cell. Address signal A1,
When A2 designates the address of a normal memory cell of the main memory cell array, the normal memory cell array is in the operating state and the redundant memory cell array (not shown) is in the non-operating state. On the contrary, when the address signals A1 and A2 specify the address of the defective memory cell, the normal memory cell array is set to the non-operating state and the redundant memory cell array is set to the operating state.

For example, when there is a defective memory cell at the address 01 corresponding to the address signals A1 and A2 of the normal memory cell array, the address signal A1b, whose value is "1",
The fuses F2 and F3 to which A2a is input may be cut off.

By thus cutting the fuses F1 to F4, the inverted memory selection signal ms is at the L level, that is, the memory selection signal msb is at the H level at the address of the normal memory cell, and conversely, the defective memory cell is defective. , The L level is set. In this way, when a defective memory cell exists in the normal memory cell array, the redundant memory cell array is selected in response to the supply of the memory selection signal msb.

At the H level voltage value of the inverted memory selection signal ms, the fuses F2 and F3 are cut and the address signal A1 is generated.
Since a and A2b are "0", the power supply is at Vcc level. However, the L-level voltage value Vl of the signal ms does not reach the GND level because the signal ms may be pulled out by a combination of only one fuse and transistor depending on the combination of the address signals A1 and A2. In this case, the L level voltage value, that is, the maximum L level voltage VL, is a series resistance composed of the on resistance Rp of the transistor Q5, the resistances Rf of one of the fuses F1 to F4 and the transistors Q1 to Q4, and the on resistance Rq of the transistor. Rf
+ Rq) and partial pressure VL = Vcc · (Rf + R
q) / (Rf + Rq + Rp). This highest L level voltage VL is judged by the next stage inverter I1 to be L level. Therefore, the size corresponding to the current capability of each of the transistors Q5, Q1 to Q4 is set so that the ratio of the on resistance Rp to the series resistance (Rf + Rq) is set so that the voltage VL is sufficiently lower than the threshold voltage of the inverter I1 and cut off. Set it to be optimal.

Referring to FIGS. 9 (B) and 9 (C) showing circuit diagrams of the precharge circuit 1A and the one-shot circuit 6 of the conventional second redundant memory selection circuit, the above-mentioned first precharge circuit 1A is referred to. Is different from the conventional circuit in that the gate of the transistor Q5A is not fixed to the L level and the one-shot circuit 6 supplies the precharge signal φ which is a one-shot signal synchronized with the change of the address signals A1 and A2. is there.

In the case of this circuit, when the precharge signal φ is at the H level for inactivation, the L level of the signal ms becomes the GND level, but in general, the fuse and the transistor are connected to the load resistance of the signal ms. Since the series resistance value (Rf + Rq) of Q1 to Q4 is large, the following delay occurs from the turning off of the transistor Q5A until the signal ms reaches the GND level. That is, when the memory selection signal msb is changed from the selected state to the non-selected state, the power supply level Vcc is changed to the intermediate level L level voltage Vl at the node MS.
Since the data is transmitted by the change to
The higher the voltage, the more the fuse F becomes conductive
As the number of sets of 1 to F4 and transistors Q1 to Q4 is smaller, it is delayed to cut off the threshold voltage of the inverter I1 below the threshold voltage, and as a result, the memory selection signal msb.
Reset will be delayed.

Therefore, the semiconductor memory circuit aiming at high speed access has a level V which is a voltage division of one of the transistor Q5A, the fuse and the transistors Q1 to Q4.
With L, the low level of MS must be judged.

In recent years, the voltage of semiconductor memories has been lowered with the high integration, and the lower limit of the guaranteed operation voltage is 2.5V.
It has fallen to the vicinity. On the other hand, in the burn-in test for early rejecting a defective memory cell having a deterioration factor, a high voltage (5 to 6 V) exceeding the recommended operation voltage is applied, and the operation test during the burn-in test, namely A monitor burn-in test is also being conducted. Therefore, the redundant memory cell selection circuit is 2.
It is necessary to stably operate in the voltage range of 5V to 6V.

The power supply voltage Vcc of the threshold value Vt of the inverter I1 for converting the inverted memory selection signal ms into the CMOS level memory selection signal msb and the maximum L level voltage VL.
Referring to FIG. 10 showing an example of the characteristic with respect to the change of
In the high voltage region, for example, 5 V or more, the voltage ML becomes higher than the threshold value Vt, and the L level cannot be correctly determined. In such a case, the precharge transistor Q
Subtle adjustments such as reduction of the current capacity of No. 5 or increase of the current capacity of the fuse driver transistors Q1 to Q4 are required.

[0017]

In the conventional semiconductor memory described above, the redundant memory selection circuit includes the on-resistance of the precharge transistor, the series resistance including the resistance of the pair of fuses and the on-resistance of the series-connected driver transistor thereof. Since the maximum L level voltage of the inverted memory selection signal determined by the voltage division is determined to be the L level by the next stage inverter and converted to the CMOS level, if the current capacity of the precharge transistor is too large, a burn-in test is performed. When the applied power supply voltage becomes high, the maximum L level voltage exceeds the threshold value of the inverter, and the L level cannot be correctly determined, which causes a malfunction.

On the other hand, if the current capacity of the precharge transistor is reduced so that correct determination can be made even at a high voltage, a delay occurs when the inverted memory selection signal changes from the L level to the H level. There is a drawback in that the size ratio with the driver transistor needs detailed examination and is complicated.

[0019]

In a semiconductor memory of the present invention, a redundant memory cell array for replacing defective cells in a predetermined array unit of columns or rows, and a predetermined one of the redundant memory cell arrays are selected. Redundant memory cell array selection line, a precharge circuit that generates a first potential corresponding to the first power supply voltage at a predetermined node when not selected, and the first power supply voltage and the second power supply voltage when selected. A redundant memory address setting circuit for generating an intermediate second potential at the node and a logic conversion circuit for converting each of the first and second potentials into a first and a second selection potential, respectively. Redundant memory selection for selecting the redundant memory cell array selection line by generating selection signals of the first and second selection potentials respectively in the non-selection and in the selection in response to signal supply. A redundant memory selection circuit is responsive to the supply of a high voltage test signal that is activated in response to an excess of a predetermined voltage value of the first power supply voltage. A logic conversion potential switching means for switching the operation level of the logic conversion of the potential to the second selection potential is provided.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Next, referring to FIG. 1, which is a circuit diagram of the first embodiment of the present invention, the components common to those in FIG. The redundant memory selection circuit of the semiconductor memory of the present embodiment shown in the figure has a redundant memory address setting circuit 2 common to the conventional one, an inverter I1, and a transistor Q instead of the precharge circuit 1.
In addition to 5, the precharge circuit 3 further includes a transistor Q6 having a drain connected to the node MS and turned on / off in response to the supply of the burn-in test mode signal BT.

Next, the operation of the present embodiment will be described with reference to FIG. 1. First, when the power supply voltage Vcc is within the recommended operation voltage, the burn-in test signal BT is "0" and the transistor Q6 is Since it is turned on, the node MS
Is a maximum L level voltage VLN of the parallel value RP = (Rp + R) of the on resistances Rp and Rb of the transistors Q5 and Q6.
q) / RpRb and the series resistance (Rq +) of any one of the fuses F1 to F4 and the transistors Q1 to F4.
Rf) and the voltage division, and the voltage VLN = Vcc. (Rf
+ Rq) / (Rf + Rq + Rp). Inverter I
1 determines that the voltage VLN is at the L level and sets the memory selection signal Msb = '1'. On the other hand, when the power supply voltage Vcc exceeds the recommended operation voltage to some extent or more, the signal BT is'
Since it becomes 1 ′, the transistor Q6 is cut off and the on-resistance of the precharge circuit 3 is only the on-resistance value Rp of the transistor Q5. Therefore, the maximum L level voltage VLB of the node MS is the same as the conventional voltage VL, that is, VLB = V
cc · (Rf + Rq) / (Rf + Rq + Rp),
It is set to a lower value than when the transistor Q6 is on.

As a result, the maximum L level voltage VL of the node MS and the power supply voltage Vcc of the threshold value Vt of the inverter I1.
The dependency characteristic is as shown in FIG. 2, and stable operation can be performed even when the voltage Vcc is high.

Further, the precharge transistors Q5, Q
Each size of 6 may be set corresponding to an optimum value between the minimum value of the recommended operation voltage with respect to the power supply voltage Vcc and the voltage at which the burn-in test signal BT is activated, that is, "1", up to the high voltage region. I do n’t need to care,
The size can be easily designed.

The burn-in test signal BT may be given from an external pin or may be automatically generated from the power supply voltage.

Referring to FIG. 3 showing an example of a burn-in test signal generating circuit for automatically generating a burn-in test signal BT according to a power supply voltage, this burn-in test signal generating circuit is connected in series between a power supply Vcc and a ground GND. Connected between the power supply Vcc and the node N2 and the diode-connected transistor Q.
7 and Q8, a transistor Q9 inserted between the node N2 and the ground GND, and two-stage inverters I2 and I3 connected between the node N2 and the output terminal.

To explain the operation, the resistors R1 and R2 are
The potential of the node N1 which is the connection point of V1 becomes the partial voltage of R1 and R2, that is, VccR2 / (R1 + R2). If R2 = 2
When R1 is set, the potential of the node N1 becomes 2/3 Vcc. The node N2 is held at the GND level by the transistor Q9 when the power supply Vcc is low, and the signal BT is also at the L level.

The power supply Vcc is VN1 + 2VTP (VN
1: potential of N1 = 2/3 Vcc, VTP: threshold voltage of transistors Q7 and Q8), the transistors Q7 and Q8 are turned on, and current flows into the node N2. Since the transistor Q9 is set to have a smaller current capacity than the transistors Q7 and Q8, the node N2 becomes high level and the output signal BT becomes "1". In this example, Vcc> 2 / 3Vcc + 2VTP: 1 / 6Vcc
When> VTP, BT = '1'.

Next, referring to FIG. 4, which is a circuit diagram in which components common to those of the second embodiment of the present invention are denoted by common characters, the same components as those of FIG. 1 are referred to. The difference between this embodiment and the first embodiment is that the precharge circuit 3
Instead of the precharge circuit 3 that operates in response to the supply of the precharge signal φ similar to that of the conventional second semiconductor memory.
A is provided.

The precharge circuit 3A includes a transistor Q
In addition to 5A and Q6, there is provided an OR gate G1 which takes the logical sum of the precharge signal φ and the burn-in test signal BT and supplies it to the gate of the transistor Q6.

With respect to the operation, except for the precharge signal φ, the operation and effect are the same as those in the above-described first embodiment, and therefore the description thereof will be omitted.

Next, referring to FIG. 5, which is a circuit diagram in which the same components as those of FIG. 1 according to the third embodiment of the present invention are designated by common characters, the present embodiment shown in FIG. The difference between this embodiment and the first embodiment is that the precharge circuit 3
Instead of, the gate of the transistor Q5B and the transistor Q6A receiving the burn-in test signal BT are connected in series to the source side of the transistor Q5 and the gate and Vcc are commonly connected, and the signal BT is inverted and the signal BTb is inverted to the gate of the transistor. It is to be provided with a precharge circuit 4 provided with an inverter I5 to be supplied.

The operation of the present embodiment will be described with reference to FIG. 4. In the precharge circuit 4, the transistor Q5B turns on only when the signal BT = '0' and the transistor Q6A outputs the signal BT = '1'. Only turn on. Therefore, when BT = '0', the maximum L level voltage VL
Is the on resistance value Rp of the transistor Q5B, the fuse resistance Rf, and the on resistance Rq of its driver transistor.
And the series resistance value (Rf + Rq) and the divided voltage value Vcc (Rf
+ Rq) / (Rf + Rq + Rp). On the other hand, BT
When = '1', the transistor Q5B is cut off, and the series resistance value (Rf + Rq) of the ON resistance Rb of the transistor Q6A, the fuse resistance Rf, and the ON resistance Rq of the driver transistor thereof causes Vcc-VTN (VT
N: threshold voltage of Q10) level V
L = Vcc-VTN (Rf + Rq) / (Rf + Rq + R
b) is the maximum L level voltage.

By using this embodiment, the maximum L
The voltage dependence characteristics of the level voltage VL and the threshold value Vt of the inverter I1 are similar to those in FIG. 2, and stable operation is possible even at a high voltage.

Next, referring to FIG. 6 which is a circuit diagram in which the components common to those of the fourth embodiment of the present invention are given the common characters, the components of the fourth embodiment of the present invention shown in FIG. The difference between this embodiment and the third embodiment is that the precharge circuit 4
Instead of the above, a precharge circuit 4A that operates in response to the supply of the precharge signal φ is provided.

The precharge circuit 4A includes a transistor Q
In addition to 5B and Q6A, there is provided an OR gate G1 which takes the logical sum of the precharge signal φ and the inverted burn-in test signal BTb and supplies it to the gate of the transistor Q6A.

With respect to the operation, except for the precharge signal φ, the function and effect are the same as those in the above-described third embodiment, and therefore the description thereof will be omitted.

Next, referring to FIG. 7, which is a circuit diagram in which the same components as those of FIG. 1 are designated by the common characters, the fifth embodiment of the present invention is described. The difference between the first embodiment and the first embodiment is that the precharge circuit 1 is the same as the conventional one, the input end is connected in parallel with the input end of the inverter I1, and the threshold Vt2 is the threshold V of the inverter I1.
Inverter I2 different from t (high in this example), and inverter I1, in response to the value of burn-in test signal BT.
And a selector S1 for selecting one of the outputs I2 as the memory selection signal msb.

The operation of the present embodiment will be described with reference to FIG. 7 and FIG. 8 showing the voltage dependence characteristics of the maximum L level voltage VL and the threshold values Vt and Vt2 of the inverters I1 and I2. Is low and the signal BT is'
When it is 0 ', the selector S1 selectively outputs the output of the inverter I1 as the signal msb. When the power supply voltage Vcc rises and the signal BT reaches the voltage VBT at which the signal BT transits to "1", the selector S1 selectively outputs the output of the inverter I2 as the signal msb. Therefore, stable operation is possible even when the power supply voltage Vcc is high.

It is obvious that the same effect can be obtained by applying the present embodiment when the precharge signal φ is used.

[0040]

As described above, in the semiconductor memory of the present invention, the redundant memory selection circuit responds to the supply of the high voltage test signal BT which is activated in response to the excess of the set voltage value of the power supply voltage. By providing the logic conversion potential switching means for switching the potential level of the logic conversion, the maximum L level voltage or the threshold value of the output inverter circuit is changed in accordance with the value of the signal BT, so that a wide voltage range can be obtained. The redundant memory selection circuit can be operated at high speed and stably.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor memory of the present invention.

FIG. 2 is a power supply voltage vs. maximum L level voltage and threshold voltage characteristic diagram showing an example of the operation in the semiconductor memory of the present embodiment.

FIG. 3 is a circuit diagram showing an example of a burn-in test signal generation circuit.

FIG. 4 is a circuit diagram showing a second embodiment of a semiconductor memory of the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of a semiconductor memory of the present invention.

FIG. 6 is a circuit diagram showing a fourth embodiment of a semiconductor memory of the present invention.

FIG. 7 is a circuit diagram showing a fourth embodiment of a semiconductor memory of the present invention.

FIG. 8 is a power supply voltage vs. maximum L level voltage and threshold voltage characteristic diagram showing an example of the operation in the semiconductor memory of the present embodiment.

FIG. 9 is a circuit diagram showing an example of conventional first and second semiconductor memories and a one-shot circuit.

FIG. 10 is a power supply voltage vs. maximum L level voltage and threshold voltage characteristic diagram showing an example of a potential in a conventional semiconductor memory.

[Explanation of symbols]

 1, 1A, 3, 3A, 4, 4A Precharge circuit 2 Redundant memory address setting circuit 5 Burn-in test signal generation circuit 6 One-shot circuit F1 to F4 Fuse G1 OR gate I1 to I4 Inverter Q1 to Q10 Transistor R1, R2 Resistance S1 selector

Claims (7)

[Claims] 1. A redundant memory cell array for replacing defective cells in a predetermined array unit of columns or rows, a redundant memory cell array selection line for selecting a predetermined one of the redundant memory cell arrays, and a non-selection line. A precharge circuit that sometimes generates a first potential corresponding to a first power supply voltage at a predetermined node and a second potential intermediate between the first power supply voltage and the second power supply voltage at the time of selection are used as the node. A redundant memory address setting circuit that is generated and a logic conversion circuit that converts each of the first and second potentials into first and second selection potentials, respectively. And a redundant memory selection circuit for selecting the redundant memory cell array selection line by generating selection signals of the first and second selection potentials, respectively. A redundant memory selection circuit changes the second potential to the second selection potential in response to the supply of a high voltage test signal that is activated in response to the predetermined voltage value of the first power supply voltage being exceeded. 2. A semiconductor memory, comprising: a logic conversion potential switching means for switching the potential level of the logic conversion. 2. A fuse ROM in which the memory address setting circuit includes a plurality of fuses corresponding to respective bits of the address signal, and a transistor inserted between the plurality of fuses and the second power supply. 2. The semiconductor memory according to claim 1, further comprising: a first inverter circuit having a predetermined first threshold value capable of responding to the second potential. 3. The high voltage test, wherein the logic conversion potential switching means is inserted between the first power supply and the node, and conducts independently of the supply of the high voltage test signal. A second that conducts in response to the supply of a signal
2. The semiconductor memory according to claim 1, further comprising the precharge circuit having the transistor of FIG. 4. The logic conversion potential switching means is the second
A first inverter circuit having a predetermined first threshold value capable of responding to the potential of the second inverter circuit, a second inverter circuit having a second threshold value larger than the first threshold value, and the high threshold value. 2. The semiconductor memory according to claim 1, further comprising: the logic conversion circuit including a selector circuit that selects one of the first and second inverter circuits in response to the supply of the voltage test signal. 5. The third transistor, wherein the precharge circuit is inserted between the first power supply and the node, and rendered conductive in response to supply of a predetermined precharge signal, and the high voltage test signal. 4. The semiconductor memory according to claim 3, further comprising: a fourth transistor which is rendered conductive in response to the supply of the logical sum value of the precharge signal. 6. The fifth transistor, which is inserted between the first power supply and the node and is conductive in response to the supply of the high-voltage test signal, is diode-connected to the first transistor and the first transistor is diode-connected. And a seventh transistor connected to the power source of the sixth transistor, and a seventh transistor which is connected to the source of the sixth transistor and the drain of the node and which conducts in response to the supply of the inverted signal of the high voltage test signal. 4. The semiconductor memory according to claim 3, wherein: 7. The eighth precharge circuit is inserted between the first power supply and the node and is turned on in response to supply of a logical sum value of the high-voltage test signal and the precharged signal. The diode is connected to the transistor of
And a source connected to the sixth transistor and a drain connected to the node to respond to the supply of the logical sum of the inverted signal of the high voltage test signal and the precharged signal. 4. The semiconductor memory according to claim 3, further comprising a ninth transistor that is turned on.