JPH0945075A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To expedite the latency by disposing no logic gate between a memory cell and a memory controller, thereby enabling one cycle transfer from the cell to the controller. SOLUTION: When an address switch controller 2 selects a memory card 7 connected with a memory address bus 33 and a memory data bus 29, it connects the buses 22, 4 via a semiconductor switch 5 by using a semiconductor switch control signal 10. Then, the controller 2 outputs the signal necessary for row and column addresses and a memory access signal to the bus 4, and the card 7 outputs data to the bus 19 after a predetermined cycle. The controller 2 connects the buses 18, 19 via the switch 17 by a semiconductor control signal 11 before one cycle when the card 7 outputs the data. Thus, the switches 5, 17 formed of MOS transfer gates are disposed between the card 7 and a memory controller 1 to make the logic gate unstable to transfer one cycle from the card 7 to the controller 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device and an information processing device using a storage element capable of continuously reading and writing data.

[0002]

2. Description of the Related Art In order to improve the performance of a computer system, a storage device is required to have a large capacity and high performance. The performance of a storage device is evaluated by a value called throughput, which is a value indicating the amount of data that can be transferred in a unit time, and a value called latency, which is a value indicating the waiting time from the generation of a memory access request to the transfer of data. Naturally, the storage device has higher throughput and lower latency,
Higher performance.

On the other hand, in order to increase the storage capacity, it is necessary to increase the number of storage elements as much as possible. However, since the number of LSI pins that can be used in the memory controller is limited and the number of memory elements that can be connected to one pin is also limited, the number of memory elements that can be connected to one memory controller is limited.

A memory device such as a DRAM has an operation mode called a page mode for continuously outputting data. However, the operating frequency when data is continuously output in this page mode is limited to about 20 megahertz [MHz].

For this reason, a plurality of sub-controllers composed of selectors that can be switched at high speed are arranged between the memory controller and the memory element, and a plurality of memory buses and one controller are connected. This makes it possible to increase the number of memory elements connected to one memory controller, and the memory controller activates multiple memories at the same time, and the data output by the memory elements on multiple memory buses is output. The sub-controller synchronizes with a high-speed clock of about 50 MHz to 100 MHz and switches the bus at high speed to realize high throughput. As an example of this, JP-A-6-34859
The memory system used in Japanese Patent Laid-Open No. 0 can be mentioned.

On the other hand, in recent years, memory devices have been developed which can operate in synchronization with a clock, which is represented by a synchronous DRAM (hereinafter referred to as SDRAM). This SDRAM can operate at a higher speed than the page mode of the conventional DRAM, and its operating frequency reaches about 100 MHz.

[0007]

As described above, in the conventional system, the high throughput is realized by using the sub-controller composed of the selectors that can be switched at high speed, and the memory connected to one memory controller is further realized. It is possible to increase the number of elements.

On the other hand, this sub-controller is generally
It is realized by a logic gate. The selector made of this logic gate requires two stages of NAND date, a receiver circuit, and a driver circuit. Therefore, it takes time for the data to pass through the inside, and this time is usually about a dozen nanoseconds [nS] (equivalent to a cycle time of several tens of MHz). Therefore, in order to operate the memory system at a high-speed frequency and realize high throughput, the latch provided in the sub-controller once receives the data from the DRAM, and then the latch of the sub-controller Was transferring data to. Therefore, one cycle from the DRAM to the sub controller and one cycle from the sub controller to the memory controller are required, and a transfer time of at least 2 cycles or more is required. Thus, in order to achieve high throughput, the memory system using the conventional method is
Since it is necessary to place an intermediate latch on the memory bus, the latency of the memory device must be at least 1 less than the latency of the memory device itself.
There is a problem that the cycle latency becomes slow. On the other hand, when a memory element that outputs data continuously in synchronization with a clock, which is represented by a newly developed SDRAM, is used, high throughput can be achieved without the sub memory controller that can be switched at high speed as described above. It can be realized. However, it is necessary to realize a large capacity even in a memory system using SDRAM.
Therefore, in order to increase the number of memory elements connected to one memory controller, it is necessary to use a sub controller as in the conventional method. Therefore, even if a memory element that outputs data continuously in synchronization with a clock is used, it is necessary to place an intermediate latch on the memory bus in order to achieve high throughput as in the conventional method. At least 1 less than the latency
There arises a problem that the cycle latency becomes high, and a problem that only the performance equivalent to that of the conventional system can be realized.

It is an object of the present invention to utilize a memory element that continuously inputs / outputs data in synchronization with a clock so that a large number of memory elements can be connected to a memory controller and a throughput equal to or higher than that of a conventional method can be realized. In addition, it is to lower the latency.

[0010]

Means for Solving the Problems A plurality of buses to which synchronous DRAMs that operate in synchronization with a plurality of clocks are connected,
A storage element control for connecting a bus selection device including a MOS transfer gate for selecting one bus from the plurality of buses and controlling a synchronous DRAM connected to the bus using the bus selected by the bus selection device In a storage device including a unit and a bus selection device control unit that gives an instruction to select a plurality of buses to the bus selection device including a MOS transfer gate, the bus selection device including the MOS transfer gate is controlled by the bus selection device control unit. By a drive means controlled by a signal, the bus connected from the synchronous DRAM and the bus connected from the storage element control unit are electrically connected or disconnected, and have a feature of being constituted by an element. The bus selection device control unit is a bus composed of a MOS transfer gate. When it is necessary for the bus selection device control unit to change the connection state of the bus selection device by determining whether or not the connection state of the selection device has changed, the bus selection device control unit performs control such that one or more cycles of use inhibition are provided on the bus When it is not necessary to change the connection state of the selection device, control is performed to continuously use the bus.

[0011]

[Operation] Between the memory device and the memory controller, MO
By arranging the bus selection device composed of the S transfer gate, since the logic gate is not required, one cycle transfer from the memory element to the memory controller becomes possible. Further, only when the switch needs to be switched, only the cycle makes the bus unused, and when the switch does not need to be switched, the bus can be continuously accessed.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a memory system utilizing a semiconductor switch composed of MOS transfer gates and a synchronous DRAM, which is a feature of the present invention.

The processor 14 or the input / output device 15 in FIG. 1 is connected to the main storage device 25 by the address bus 12 and the data bus 13. When it is necessary to read data from the main storage device 25 as a result of the processing performed by the processor 14 or the input / output device 15, a main memory read request is sent to the main storage device 25 by using the memory request signal 26. Then, the read address of the main memory is sent using the address bus 12. The main memory device 25 sends the read address to the address / switch control unit 2 in the memory controller 1 inside the main memory device 25.

The address switch controller 2 selects one memory card from all the memory cards 7 based on the value of the address bus 12. Here, for example, it is assumed that the memory card 7 to which the memory address bus 22 and the memory data bus 19 are connected is selected. In this case, the semiconductor switch control signal 10 is used to connect to the memory address bus 22 and the memory address bus 4 to which the memory card 7 to be accessed is connected. Next, the address / switch control unit outputs a signal necessary for a row address, a column address, and other necessary memory access control signals to the memory address bus 4. After a certain cycle, the memory card
The data is output to the memory data bus 19. address·
The switch control unit outputs the data from the memory card 1
Before the cycle, the semiconductor switch control signal 11 is used to connect the memory data bus 18 and the memory data bus 19.

The address / switch controller 2 stores the state of the currently selected semiconductor switch 5, 17 and determines whether the semiconductor switch 5, 17 needs to be switched in response to the next memory access request. It has a function to judge. Furthermore, when it is determined that the semiconductor switches 5 and 17 need not be switched, one cycle earlier than when it is determined that the semiconductor switches 5 and 17 need to be switched,
It is equipped with 7 memory card activations.

FIG. 2 shows the inside of the address / switch control unit 2.

The address / switch control unit 2 includes a memory element control circuit 112 and a bus selection device control unit 13.
Consists of zero. The bus selection device control unit 130 includes registers 100, 101, 102, comparators 104, 105,
106, 116, a switch control circuit 113, a switch state buffer 109, and a timing control unit 114.

The main memory read address sent by the address bus 12 is transmitted to the memory element control circuit 112, and at the same time, the register 1 is read by the comparators 104, 105 and 106.
00, 101, 102.

The values indicated by the registers 100, 101, 102 indicate addresses, and the boundary between the memory address bus 6 and the memory address bus 22, the boundary between the memory address bus 22 and the memory address bus 23, the memory address bus 23 and the memory, respectively. The boundaries of the address bus 24 are shown. FIG. 3 illustrates the memory space indicated by the registers 100, 101 and 102.

The operations of the memory element control circuit 112, the switch control circuit 113, and the switch state buffer 109 operate according to the timing generated by the timing control unit 114.

The memory element control circuit 112 uses the address bus 12 and the values of the registers 100, 101 and 102 to
Wiring 1 of the timing control unit 114 after performing a certain calculation
A row address and a column address for accessing the memory card 7 according to the start timing transmitted in 19;
It is a sequencer that generates a control signal such as a chip select signal.

The switch control circuit 113 switches the semiconductor switch 5 from the comparison results of the comparators 104, 105 and 106 according to the control timing transmitted from the timing control unit 114 via the wiring 117, and the timing control unit 114.
This is a logic circuit that sets the semiconductor switch 17 to the state of the semiconductor switch 5 changed at the timing of the wiring 117 in accordance with the control timing transmitted by the wiring 118 of FIG.

The semiconductor switch 17 is switched according to the comparison result of the comparators 104, 105 and 106.

The switch state buffer 109 holds the comparison result of the comparators 104, 105, 106 according to the control timing transmitted by the wiring 117 of the timing control unit 114.

The comparator 116 has a switch state buffer 1
09 and the comparison results of the comparators 104, 105, 106 are compared, and if they do not match, 1 is output to the wiring 120.

The basic operation of the timing control section 114 is to control the memory element control circuit 112, the switch control circuit 113, and the switch state buffer 109. Only the logic of the function of reading data from the memory of the timing control unit 114 is shown in FIG.

When a memory read request arrives from the memory request signal 26, the arbitration circuit 30
At 9, the necessary arbitration is performed, and 1 is set in the flip-flop 305. This flip-flop 305
The cycle in which 1 is set is this flip-flop 3
By using the AND gate 300, 05 can be set to only one cycle. The memory controller outputs one cycle pulse of the flip-flop 305.
Processor 14 as memory request acceptance signal 27
Or to the request source of the input / output device 15. The processor 14 and the input / output device 15, which are the memory request request source, lower the memory request signal 26 when receiving the memory request acceptance signal 27.

While the memory request signal 26 is being output, the wiring 120, which is the output of the comparator 116, indicates that the newly requested memory request is the semiconductor switch 5,
It indicates whether the current status of 17 matches or does not match, and 1 is set when they do not match. When the output of the flip-flop 305 becomes 1 for one cycle while the output of the logic gate 301 is 1, the control timing signal for switching the semiconductor switch 5 to immediately switch the memory address bus and the state of the semiconductor switch change. This means that 1 cycle 1 is output to the wiring 119 as a signal for storing the new state in the switch state buffer 109. Since a memory device such as SDRAM outputs data several cycles after being activated, a memory read switch switching sequencer 308 that counts switch switching timing is activated, and this sequencer 30 is activated.
8 outputs 1 to the wiring 118 for one cycle at the timing of switching the memory data bus after a fixed cycle. Further, in order to activate the memory card 7, the output of the logic gate 302 is delayed by one cycle via the flip-flop 307 and the wiring 117 is set to 1 at a timing.
Is output. As a result, when the semiconductor switches 5 and 17 are switched, the semiconductor switch 5 for the memory address bus is switched immediately and the memory card is activated in the next cycle.

On the other hand, when the newly requested memory request matches the current state of the semiconductor switches 5 and 17, the output of the logic gate 304 becomes 1 and the signal 117 is sent to the wiring 117 at the same time as the memory request acceptance signal 27. 1 is output. In this case, since the states of the semiconductor switches 5 and 17 do not change, nothing is output to the wirings 118 and 119.

FIG. 5 is a timing chart showing the operation of the logic of FIG. 4 and the operations of the memory address bus and the memory data bus.

Although FIG. 4 shows only the logic for reading data from the memory card, the logic for writing data to the memory card is similar.

FIG. 6 shows one-to-four semiconductor switches 5 and 17.
It is an example of. 229, 230, 231, 23 in the figure
2, 233, 234, 235 and 236 are MOS transfer transistors. Also 237, 238, 23
9,240 are inverters.

Of the terminals 220, 221, 222, 223, for example, when a high level is input to the terminal 221, and a low level is input to the terminals 220, 222, 223,
MOS transfer transistors 230 and 233,2
35 and 236 are turned on and the other MOS transfer transistors are turned off. As a result, the terminal 22
8 and the terminal 226 become the same level, and the terminals 224, 2
25 and 227 become Vcc, and a 1 to 4 selector can be easily realized. LVTTL, T among the semiconductor input / output circuit system
Represented by TL. In the push-pull type input / output circuit type, the receiving circuit must always be fixed at a high level or a low level for circuit protection, but it can be easily realized by the circuit shown in FIG. As another circuit system, it is possible to realize a 1-to-n selector by connecting the 1-to-2 selector, which is a degenerate version of FIG. 6, in multiple stages.

Among the semiconductor input / output circuit systems, there is an input / output circuit system using a terminating resistor. Typical circuit methods using a terminating resistor include HSTL, ST-bus, GTL, and CT.
It can be given as T. When these circuit systems are used, the positional relationship between the semiconductor switch and the terminating resistor becomes a problem. FIG. 7 shows a layout in which the terminals are always terminated at both ends of the memory bus and the point from the memory controller 1 to point A in the figure is regarded as tap-off. In this case, the memory controller 1
The longer the distance from to point A, the longer the time the waveform is disturbed. This is because the waveform reflected at the connection point with the memory controller 1 is again reflected at the point A in the figure, and the reflected wave repeatedly travels between the memory controller 1 and the point A. Therefore, it is necessary to wait until the reflected wave has no influence, but the influence of the reflected wave depends on the number of reflections.

On the other hand, as shown in FIG. 8, a terminating resistor 4 is provided between the memory controller 1 and the semiconductor switch 5 or 17.
By arranging 01, the waveform once reflected by the memory controller 1 is matched by the terminating resistor 401. Therefore, the phenomenon in which the reflected wave reciprocates many times does not occur. Therefore, the time when the waveform is disturbed by the influence of this reflected wave is shown in FIG.
It will be much shorter than.

[0037]

Since no logic gate is arranged between the memory element and the memory controller, one cycle transfer from the memory element to the memory controller becomes possible.
The latency is faster than the memory system using the conventional method. Further, by using a storage element capable of continuously inputting / outputting data such as a synchronous DRAM, the frequency of switching the switches is reduced. Further, the bus is prohibited only when the switch needs to be switched, and when the switch is not required, the bus is continuously accessed, so that the latency and the throughput are improved and the performance of the entire system is improved.

Further, when the push-pull type input / output circuit type is used, the circuit protection of the receiving circuit can be easily implemented by setting a constant bias voltage to the memory controller and the unconnected memory bus.

Further, in the case of the input / output circuit system using the terminating resistance among the semiconductor input / output circuit systems, by disposing the terminating resistor between the memory controller and the semiconductor switch, the waveform is disturbed by the influence of the reflected wave. The time spent can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor switch including a MOS transfer transistor to which the present invention is applied.

FIG. 2 is a block diagram showing an address switch controller of the present invention.

FIG. 3 is an explanatory diagram showing a relationship between an address indicated by a register used in the present invention and an address space of a memory bus.

FIG. 4 is a block diagram showing the logic of memory read of the timing control unit of the present invention.

5 is a timing chart showing the operation of the logic block shown in FIG. 4;

FIG. 6 is an explanatory diagram showing a configuration of a semiconductor switch including a MOS transfer transistor used in the present invention.

FIG. 7 is a block diagram showing an unsuitable relationship between a semiconductor switch and a terminating resistor.

FIG. 8 is a block diagram showing a non-corresponding relationship between a semiconductor switch and a terminating resistor.

[Explanation of symbols]

1 ... Memory controller, 2 ... Address switch control section, 3 ... Data control section, 4,6,22,23,24 ... Memory address bus, 5,17 ... Semiconductor switch, 7 ... Memory card, 8,18,19 , 20, 21 ... Memory data bus, 9 ... Terminating resistor, 12 ... Address bus, 13 ... Data bus, 14 ... Processor, 15 ... Input / output device, 26
... memory request signal, 27 ... memory request acceptance signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Sataka Ishikawa 810 Shimoimaizumi, Ebina-shi, Kanagawa Hitachi Ltd. Office Systems Division

Claims (6)

[Claims] 1. A plurality of buses to which one or a plurality of storage elements are connected, a bus selection device connected to the plurality of buses and selecting one bus from the plurality of buses, and the bus selection circuit. A storage element control unit that is connected and that controls the storage element that is connected to the bus using the selected bus, and an instruction that is connected to the bus selection circuit and that selects the plurality of buses to the bus selection device. In the storage device comprising the given bus selection device control unit, the bus selection device is driven by a drive means controlled by a control signal comprising the bus selection device control unit.
A bus connected from the storage element and a bus connected from the storage element control unit are electrically connected or disconnected from each other. When it is necessary for the bus selection device control unit to change the connection state of the bus selection device by judging the presence or absence of a change, the bus selection device control unit performs control to provide one or more cycles of use prohibition to connect the bus selection device. A semiconductor memory device, wherein control is performed to continuously use the bus when there is no need to change the state. 2. A plurality of buses to which one or a plurality of storage elements are connected, a bus selection device which is connected to the plurality of buses and selects one bus from the plurality of buses, and the bus selection circuit. A storage element control unit that is connected and that controls the storage element that is connected to the bus using the selected bus, and an instruction that is connected to the bus selection circuit and that selects the plurality of buses to the bus selection device. In the storage device comprising the given bus selection device control unit, the bus selection device is driven by a drive means controlled by a control signal comprising the bus selection device control unit.
The bus selection device is characterized in that the bus connected from the storage element and the bus connected from the storage element control unit are electrically connected or disconnected. A semiconductor memory device having a function of applying a constant bias voltage to a bus from the storage element that is not electrically connected to the bus from the control unit. 3. A plurality of buses to which one or a plurality of storage elements are connected, a bus selection device connected to the plurality of buses and selecting one bus from the plurality of buses, and connected to the bus selection circuit. A storage element control unit that controls a storage element connected to the bus using the selected bus and a bus selection circuit that is connected to the bus selection circuit and gives an instruction to select the plurality of buses to the bus selection device. In the storage device including a bus selection device control unit, the bus selection device includes a bus connected from the storage device and a storage device control unit by a driving unit controlled by a control signal including the bus selection device control unit. Electrically connect the connected bus, or
A resistor is used to terminate the far end of the bus connected to the storage element from the bus selection device connection point, and a resistor is used to connect the storage element control unit. A semiconductor memory device, which uses a transmission method of performing a far end side of a connected bus from a connection point of the bus selection device. 4. The bus selection device control unit according to claim 1, wherein the bus selection device control unit has a register indicating a boundary address of a plurality of buses to which the storage elements are connected, and compares the address with an address for accessing the storage device. A semiconductor memory device that switches a bus selection device. 5. A plurality of buses to which one or a plurality of storage elements are connected, a bus selection device connected to the plurality of buses and selecting one bus from the plurality of buses, and connected to the bus selection circuit. A storage element control unit that controls a storage element connected to the bus using the selected bus and a bus selection circuit that is connected to the bus selection circuit and gives an instruction to select the plurality of buses to the bus selection device. In a storage device including a bus selection device control unit, the bus selection device is controlled by a control signal including a bus selection device control unit, and the bus connected from the storage element and the storage device according to an electric field driven. It is composed of a field effect type switch element that electrically connects or disconnects the bus connected from the element control unit, The unit determines whether or not there is a change in the connection state of the bus selection device, and when the bus selection device control unit needs to change the connection state of the bus selection device, one or more prohibited cycles are applied to the bus. A semiconductor memory device characterized by performing control to be provided and performing control to continuously use the bus when it is not necessary to change a connection state of a bus selection device. 6. A plurality of buses to which one or a plurality of storage elements are connected, a bus selection device connected to the plurality of buses and selecting one bus from the plurality of buses, and connected to the bus selection circuit. A storage element control unit that controls a storage element connected to the bus using the selected bus and a bus selection circuit that is connected to the bus selection circuit and gives an instruction to select the plurality of buses to the bus selection device. In a storage device including a bus selection device control unit, the bus selection device is controlled by a control signal including a bus selection device control unit, and the bus connected from the storage element and the storage device according to an electric field driven. It is characterized by a field effect switch element that electrically connects or disconnects the bus connected from the element control unit. The bus selection device for the bus connected to the storage element is terminated on the far end side from the bus selection device connection point, and a resistor is used to further connect the bus selection device for the bus connected to the storage device control unit. A semiconductor memory device characterized by using a transmission method of performing a far end side from a connection point.