CN117280298A

CN117280298A - Register array circuit and method for accessing register array

Info

Publication number: CN117280298A
Application number: CN202180097789.5A
Authority: CN
Inventors: 苗云杰; 颜丹丹; 钟世春; 魏侠
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-07-15
Filing date: 2021-07-15
Publication date: 2023-12-22
Also published as: WO2023283886A1

Abstract

A register array circuit and a method for accessing the register array relate to the technical field of chips and are used for solving the problem that useless turnover is generated when the register array circuit stores, and achieving the technical effects of reducing useless turnover in the register array circuit and reducing power consumption. When a register in the register array circuit is a rising edge trigger register, if a certain rising edge trigger register is not subjected to write access, a gating clock clamped to a high level is output to the rising edge trigger register through a gating clock circuit. When a register in the register array circuit is a falling edge trigger register, if a certain falling edge trigger register is not subjected to write access, the falling edge trigger register is output with a gating clock clamped to a low level through a gating clock circuit.

Description

Register array circuit and method for accessing register array

Technical Field

The embodiment of the application relates to the technical field of chips, in particular to a register array circuit and a method for accessing a register array.

Background

With the advancement of digital society, the demand for memory is increasing for circuit designs, such as implementing small-capacity memory based on register arrays or random access memory (random access memory, RAM). When implementing small capacity storage based on a register array, registers (registers) may be used to register instructions and data, etc.

For registers, information is generally stored in a data-clock mode, that is, a data input end (data end) corresponds to a data information bit, and a clock input end corresponds to a control signal, so that information is instantaneously written into the register under the action of the control signal. For the register array, registers of all addresses share a write data bus, when the write data bus has data transmission, the write data bus can generate overturn, and the overturn can be transmitted to the data ends of the registers of all addresses.

At present, on the basis of controlling the clock input end of the register by using the gating clock circuit, the data end of the register with the unselected address can be turned off by an AND gate or a NAND gate device (the data end of the register with the unselected address is turned off respectively or is turned off in groups according to the address), so that invalid turning of the internal circuit of the register with the unselected address can be avoided. However, this method causes an increase in the number of windings and circuit area, which results in difficulty in physical implementation, and an additional power consumption is introduced when the and gate or the nand gate is operated.

Disclosure of Invention

The embodiment of the application provides a register array circuit and a method for accessing a register array, which can reduce useless turnover in the register array circuit when the register array circuit stores, thereby reducing power consumption.

In order to achieve the above purpose, the embodiment of the application adopts the following technical scheme:

in a first aspect, an embodiment of the present application provides a register array circuit, where the register array circuit includes a plurality of registers and a plurality of gating clock circuits corresponding to the plurality of registers one to one, and the gating clock circuits are configured to output a gating clock to the registers. The plurality of registers includes a first register, the first register is a rising edge trigger register, and the first gating clock circuit corresponding to the first register is a gating clock circuit. The first gating clock circuit outputs a gating clock clamped to a high level to the first register when the first register is not being subjected to write access. Therefore, when the rising edge trigger register is not subjected to write access, the gating clock circuit corresponding to the rising edge trigger register outputs the gating clock clamped to be high level to the first register, namely, the clock input end of the rising edge trigger register is clamped to be high level, so that the low-pass circuits in the SI end selection circuit, the D end selection circuit and the low-pass high-latch lock circuit in the rising edge trigger register are not conducted, and therefore empty flip is not caused, and power consumption waste is avoided.

In one possible design, when the first register is subjected to write access, that is, when the address corresponding to the first register is selected, the first gating clock circuit is further configured to transition the gating clock output to the first register from a high level to a low level, that is, to transition the clock input end of the first register from a high level to a low level, clamp the gating clock to the first register from a low level to a high level, that is, to transition the clock input end of the first register from a low level to a high level. The first register is written with data when the gate clock output to the first register jumps from low level to high level, that is, when the clock input end of the first register jumps from low level to high level. Therefore, the SI and D end selection circuits in the rising edge trigger register and the low-pass circuit in the low-pass high-latch lock circuit are only conducted for a period of time when the write access is executed, and a circuit turning phenomenon exists, and when the rising edge trigger register is not executed after data is written into the high-pass low-latch lock circuit, namely after the data is written into the rising edge trigger register, the SI and D end selection circuits in the rising edge trigger register and the low-pass circuit in the low-pass high-latch lock circuit are not conducted, so that the waste of power consumption is avoided.

In one possible design, each of the plurality of gating clock circuits further includes a first input (i.e., a data input) coupled to the write address bus shared by each of the gating clock circuits and a second input (i.e., a clock input) for receiving the write clock signal shared with each of the gating clock circuits. Therefore, each address is provided with a corresponding gating clock circuit, the output of the gating clock circuit is related to address information indicated by the write address bus and a write clock signal, and the gating clock circuit can be controlled to output a gating clock clamped to a high level to a register of the address when the address is not selected, namely, the clock input end of the register of the address is clamped to the high level, so that the waste of power consumption is avoided.

In one possible design, the signal at the first input of the first gating clock circuit is used to indicate that the first address of the first register is not selected when the first register is not being subjected to a write access. Therefore, when the address is not selected, the gating clock circuit corresponding to the address does not jump, the register of the address is not subjected to write access, the gating clock circuit corresponding to the address can output the gating clock clamped to be high level to the register of the address, namely, the clock input end of the register of the address can be clamped to be high level, and therefore power consumption waste is avoided.

In a second aspect, embodiments of the present application provide a register array circuit including a plurality of registers and a plurality of gating clock circuits corresponding to the plurality of registers one-to-one, the gating clock circuits for outputting a gating clock to the registers. The plurality of registers includes a first register, the first register is a falling edge trigger register, and the first gating clock circuit corresponding to the first register is a gating clock circuit. The first gating clock circuit outputs a gating clock clamped to a low level to the first register when the first register is not being subjected to write access. Therefore, the gating clock circuit corresponding to the falling edge trigger register outputs the gating clock clamped to be at a low level to the first register, namely, when the falling edge trigger register is not subjected to write access, the clock input end of the falling edge trigger register is clamped to be at a low level, so that the high-pass circuits in the SI end selection circuit, the D end selection circuit and the high-pass low-latch lock circuit in the falling edge trigger register are not conducted, and therefore empty flip is not caused, and power consumption waste is avoided.

In one possible design, when the first register is subjected to write access, that is, when the address corresponding to the first register is selected, the first gating clock circuit is further configured to transition the gating clock output to the first register from low level to high level, that is, transition the clock input end of the first register from low level to high level, clamp the same to high level, and transition the gating clock output to the first register from high level to low level, that is, transition the clock input end of the first register from high level to low level. The first register is written with data when the gate clock output to the first register jumps from a high level to a low level, that is, when the clock input end of the first register jumps from a high level to a low level. Therefore, the high-pass circuits in the SI and D end selection circuits and the high-pass low-latch lock circuit in the falling edge trigger register are only conducted for a period of time when the write access is executed, and a circuit turning phenomenon exists, and when the data is written into the low-pass high-latch lock circuit, namely after the data is written into the falling edge trigger register, the high-pass circuits in the SI and D end selection circuits and the high-pass low-latch lock circuit in the falling edge trigger register are not conducted when the write access is not executed, so that the waste of power consumption is avoided.

In one possible design, each of the plurality of gating clock circuits further includes a first input (i.e., a data input) coupled to the write address bus shared by each of the gating clock circuits and a second input (i.e., a clock input) for receiving the write clock signal shared with each of the gating clock circuits. Therefore, each address is provided with a corresponding gating clock circuit, the output of the gating clock circuit is related to address information indicated by the write address bus and a write clock signal, and the gating clock circuit can be controlled to output a gating clock clamped to a low level to a register of the address when the address is not selected, namely, the clock input end of the register of the address is clamped to the low level, so that the waste of power consumption is avoided.

In one possible design, the signal at the first input of the first gating clock circuit is used to indicate that the first address of the first register is not selected when the first register is not being subjected to a write access. Therefore, when the address is not selected, the gating clock circuit corresponding to the address does not jump, the register of the address is not subjected to write access, the gating clock circuit corresponding to the address can output the gating clock clamped to be low level to the register of the address, namely, the clock input end of the register of the address can be clamped to be low level, and therefore power consumption waste is avoided.

In a third aspect, embodiments of the present application provide a method of accessing a register array, where the method is applied to a register array circuit, and the register array circuit includes a plurality of registers and a plurality of gating clock circuits corresponding to the plurality of registers one-to-one, and the gating clock circuits are configured to output a gating clock to the registers. The plurality of registers includes a first register, the first register is a rising edge trigger register, and the first gating clock circuit corresponding to the first register is a gating clock circuit. When it is determined that the first register is not being subjected to write access, a gate clock clamped to a high level, i.e., a clock input terminal of the first register is clamped to a high level, is output to the first register through the first gate clock circuit. The advantages achieved by the third aspect may be seen in the advantages of the first aspect.

In one possible design, when it is determined that the first register is subjected to write access, the gating clock output to the first register through the first gating clock circuit transitions from high to low, i.e., the clock input of the first register transitions from high to low, clamps to low, and transitions from low to high, i.e., transitions from low to high. When the clock input end of the first register jumps from the low level to the high level, data is written into the first register.

In one possible design, each of the plurality of gating clock circuits further includes a first input coupled to the write address bus shared with each of the gating clock circuits and a second input for receiving a write clock signal shared with each of the gating clock circuits.

In one possible design, the signal at the first input of the first gating clock circuit indicates that the first address of the first register is unselected when it is determined that the first register is not being subjected to a write access.

In a fourth aspect, embodiments of the present application provide a method for accessing a register array, where the method is applied to a register array circuit, and the register array circuit includes a plurality of registers and a plurality of gating clock circuits corresponding to the plurality of registers one-to-one, and the gating clock circuits are configured to output a gating clock to the registers. The plurality of registers includes a first register, the first register is a falling edge trigger register, and the first gating clock circuit corresponding to the first register is a gating clock circuit. When it is determined that the first register is not being subjected to write access, a gate clock clamped to a low level, i.e., a clock input terminal of the first register is clamped to a low level, is output to the first register through the first gate clock circuit. The advantages achieved by the fourth aspect may be seen in the advantages of the second aspect.

In one possible design, when it is determined that the first register is subjected to write access, the gating clock output to the first register through the first gating clock circuit transitions from low level to high level, i.e., the clock input terminal of the first register transitions from low level to high level, clamps to high level, and transitions from high level to low level, i.e., transitions from high level to low level. When the clock input end of the first register jumps from high level to low level, data is written into the first register.

In a fifth aspect, a computer readable storage medium comprises computer instructions which, when run on an electronic device, cause the electronic device to perform the method of any one of the above third aspect and any one of the possible designs of the third aspect.

A sixth aspect, a computer readable storage medium comprising computer instructions which, when run on an electronic device, cause the electronic device to perform the method of any one of the fourth aspect and the possible designs of the fourth aspect.

A seventh aspect is a computer program product for causing an electronic device to carry out the method of any one of the above third aspect and any one of the possible designs of the third aspect when the computer program product is run on a computer.

In an eighth aspect, a computer program product for causing an electronic device to carry out the method of any one of the above fourth aspect and any one of the possible designs of the fourth aspect when the computer program product is run on a computer.

The corresponding advantages of the other aspects mentioned above may be found in the description of the advantages of the method aspects, and are not repeated here.

Drawings

FIG. 1 is a schematic diagram of a register array circuit;

FIG. 2 is a timing diagram of a register array circuit;

FIG. 3 is a schematic diagram of another register array circuit;

FIG. 4A is a schematic diagram of a register array according to an embodiment of the present disclosure;

FIG. 4B is a schematic diagram of another register array according to an embodiment of the present disclosure;

fig. 5 is a schematic hardware structure of an electronic device according to an embodiment of the present application;

FIG. 6A is a schematic diagram of an internal circuit of a register;

FIG. 6B is a schematic diagram of another register internal circuit;

FIG. 7A is a schematic diagram of a register array according to an embodiment of the present disclosure;

fig. 7B is a schematic diagram of an internal structure of a gated clock circuit according to an embodiment of the present disclosure;

FIG. 7C is a timing diagram of a OR gate clock circuit according to an embodiment of the present disclosure;

FIG. 7D is a schematic diagram of another register array according to an embodiment of the present disclosure;

fig. 7E is a schematic diagram of an internal structure of a gating clock circuit according to an embodiment of the present disclosure;

fig. 7F is a timing diagram of a gating clock circuit according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a method for accessing a register array according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of another method for accessing a register array according to an embodiment of the present disclosure;

FIG. 10 is a schematic diagram of a register array according to an embodiment of the present disclosure;

FIG. 11 is a timing diagram of a register array circuit according to an embodiment of the present disclosure;

FIG. 12 is a schematic diagram of another register array according to an embodiment of the present disclosure;

FIG. 13 is a timing diagram of another register array circuit according to an embodiment of the present disclosure;

fig. 14 is a schematic hardware structure of an electronic device according to an embodiment of the present application.

Detailed Description

For ease of understanding, a description of some of the concepts related to the embodiments of the present application are given by way of example for reference. The following is shown:

clock (clock): each memory element in the circuit is controlled by a clock, the state of the memory element can be changed only when a clock signal arrives, so that the output of the time sequence circuit is changed, and the state of the memory element and the output state of the circuit can be changed once every clock signal. In this embodiment, when writing data into the register array, the clock signal is a write clock signal, and the write clock signal is periodically turned over, that is, makes a transition from a low level to a high level, or makes a transition from a 1-0 level to a low level.

Clock gating circuit (clock gating): by turning off the temporarily unavailable function on the chip and the clock corresponding to the function, the purpose of saving current consumption can be achieved. When the output end of the gating clock circuit does not jump, the register corresponding to the gating clock circuit is not written with data, and when the output end of the gating clock circuit jumps, the register corresponding to the gating clock circuit is written with data. In this embodiment of the present application, when the output end of the gating clock circuit hops, the register corresponding to the gating clock circuit is written with data.

Data bus (data bus): carrying data information, which may be data such as instructions, audio, video or pictures. In this embodiment, when data is written into the register array, the data bus may be a write data bus (write data bus), and when there is data transmission in the write data bus, the write data bus may perform 0-1 level jump, i.e. low level jump to high level, or 1-0 level jump, i.e. high level jump to low level. The level jumps of the write data bus can be understood as data flips.

Address bus (address bus): carrying address information, address buses can be divided into write address buses and read address buses. The write address bus indicates that data information on the data bus needs to be written into address information of a corresponding buffer (i.e., register), and the read address bus indicates that address information of the corresponding buffer needs to be read from the buffer.

Register): the clock trigger register is used for storing data information and is divided into a rising edge trigger register and a falling edge trigger register according to clock trigger edges. The rising edge trigger register performs data writing when the clock input end of the rising edge trigger register jumps from a low level to a high level, and the falling edge trigger register performs data writing when the clock input end of the falling edge trigger register jumps from the high level to the low level. For example, in the embodiment of the present application, taking a rising edge trigger register with a dual latch (latch) structure as an example, the internal circuits of the rising edge trigger register may include three circuits of a Scan Input (SI) and a data (data, D) terminal selection circuit, a low-pass high latch lock circuit, and a high-pass low latch lock circuit.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Wherein, in the description of the embodiments of the present application, "/" means or is meant unless otherwise indicated, for example, a/B may represent a or B; "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, in the description of the embodiments of the present application, "plurality" means two or more than two.

In the prior art, as shown in fig. 1, the register array circuit includes a register array (in the prior art, all of which are rising edge trigger registers) composed of a plurality of registers, AND a gating clock circuit (AND clock gating) corresponding to each register. The output of the AND gate clock circuit keeps low level when the output end does not jump, and data is not written into a register corresponding to the AND gate clock circuit. The register array includes, for example, a 0 address register, a 1 address register, a … address register, an n address register, etc. (n is an integer greater than 1) shown in fig. 1, which are all rising edge trigger registers, and represent a register of address 0, a register of address 1, a register of …, and a register of address n, respectively, that is, the addresses corresponding to each register are different. The clock input a of each register is coupled to the output b of the corresponding gating clock circuit, and the data input c of each register shares a write data bus. One input d is controlled by a write address bus (write address bus) shared by each of the gating clock circuits, and the other input e is used for receiving a write clock (write clock) signal shared by each of the gating clock circuits. The addresses of the write address bus may be different in different clock cycles, and the address information indicated by the write address bus may be 0, 1, …, n, which respectively represent selected addresses 0, 1, …, and n. When address information=0 indicated by the write address bus, that is, when the 0 address is selected to write data, the output end of the gating clock circuit corresponding to the 0 address register makes rising edge transitions (the output end of the gating clock circuit transitions from low level to high level), the output ends of the gating clock circuits corresponding to the remaining unselected address registers do not make transitions (the output end of the gating clock circuit maintains low level), and data information carried on the write data bus is written into the 0 address register when the output end of the gating clock circuit makes rising edge transitions.

FIG. 2 is a timing diagram of the register array circuit of FIG. 1. When the write clock signal is periodically flipped and address information indicated by the write address bus=0, the 0 address is selected, the 0 address register is subjected to write access, the output end of the gating clock circuit corresponding to the 0 address register is subjected to rising edge jumping, at this time, the 0 address register is written with data, and the data in the write data bus is written into the 0 address register. When address information=0 indicated by the write address bus, the registers corresponding to the other unselected addresses are not subjected to write access, and the output ends of the gating clock circuits corresponding to the registers not subjected to write access do not jump. Taking the output end of the gating clock circuit corresponding to the 1 address register as an example, when address information=0 indicated by the address bus is written, the output end of the gating clock circuit corresponding to the 1 address register keeps low level and does not jump, namely the 1 address register is not written with data. The jump position of the output terminal of the gating clock circuit corresponding to the register shown in fig. 2 may be adjusted according to an actual circuit, and the timing diagram is merely an example.

Since all address registers share the write data bus, the data terminals (e.g., input terminal c in fig. 1) of all address registers will flip whenever the write data bus is data flipped (i.e., there is a data transfer in the write data bus). When a certain address is selected, the output ends of the gate clock circuits corresponding to the other unselected addresses are kept at low level, and when the output ends of the gate clock circuits are output at low level, the inversion of the write data bus can cause the inversion of the low-pass circuits and the inverters in the register internal SI and D end selection circuits and the low-pass high-latch lock circuits of the unselected addresses. Because the output end of the gating clock circuit corresponding to the unselected address does not jump, the register of the unselected address is not written with data, so that the inside SI and D end selection circuits of the register, the low-pass circuit in the low-pass high-latch lock circuit and the turnover of the inverter are invalid, and can be understood as empty turnover, and the power consumption waste can be caused.

At present, in order to solve the problem of power consumption waste caused by invalid flip of the data end of the register with the unselected address, as shown in fig. 3, an AND gate (or a NAND gate (NAND)) is added on the basis of the register array circuit of fig. 1, the data end of the register with the unselected address is turned off, AND the data end of the register with the address where the write access is not performed is set to a low level (or a high level), that is, no jump is performed, so that invalid flip is reduced. The increased and gate (or nand gate) causes an increase in the number of windings and circuit area, making physical implementation difficult, and the and gate (or nand gate) also introduces additional power consumption when operating.

The present application thus proposes a register array circuit, which may be located in an electronic device, for example integrated in a chip. In view of the problem that in the prior art, a plurality of useless inversions can be generated in a register array circuit to cause the increase of power consumption, when the register array is a rising edge trigger register, when the data end of a register of an address which is not subjected to write access is overturned, a clock input end of the register of each address is controlled by using a OR clock circuit (OR clock gating), wherein the output end of the OR clock circuit outputs a high level, namely, the clock input end of the register which is not subjected to write access inputs a high level, and when the output end of the OR clock circuit is kept at the high level, an SI end selection circuit and a D end selection circuit in the register and a low-pass circuit in a low-pass high latch lock circuit are not conducted, so that the empty inversion of the internal circuit of the register can be reduced, the waste caused by power consumption is avoided, the number of windings and the circuit area can be reduced, and the physical implementation complexity is reduced. When the register array circuits are all falling edge trigger registers, when the data ends of the registers of addresses which are not subjected to write access are turned over, the clock input ends of the registers of each address are controlled by using the gating clock circuit, wherein the output end output of the gating clock circuit keeps low level, namely the clock input ends of the registers which are not subjected to write access are input and kept low level, when the output ends of the gating clock circuit keep low level, the SI and D end selection circuits and the high-pass circuits in the high-pass low latch lock circuits in the registers are not conducted, so that the empty turning of the internal circuits of the registers can be reduced, the power consumption waste is avoided, the winding quantity and the circuit area can be reduced, and the physical implementation complexity is reduced.

As shown in fig. 4A and 4B, the embodiment of the present application may be applied to a register array circuit. The register array circuit comprises a gating clock unit, a register array and other devices. As shown in fig. 4A, when the register in the register array is a rising edge trigger register, the gating clock unit is a gating clock circuit. As shown in fig. 4B, when the registers in the register array are falling edge triggered registers, the gating clock cell is a gating clock circuit. One of the two inputs of the gating clock unit receives a write clock signal and the other is coupled to the write address bus to receive address information indicated by the write address bus. The output end of the gating clock unit is used for controlling whether the register corresponding to the gating clock unit is written with data, and the output end of the gating clock unit and the output end of the write data bus are coupled to the register array. When the output end of the gating clock unit jumps, the data information carried by the write data bus is written into the register corresponding to the gating clock unit. Each gating clock unit is provided with a corresponding register, each register corresponds to a different address, and registers of all addresses are collectively called as a register array.

It should be noted that the embodiments of the present application may be applied to a register array formed by various types of registers, for example, the registers may be a rising edge trigger register with SI end, a falling edge trigger register with SI end, a rising edge trigger without SI end, a falling edge trigger without SI end, and the like, without limitation.

When the embodiment of the application is applied to an electronic device, as shown in fig. 5, a schematic hardware structure of the electronic device is shown, where the electronic device may include a chip in the embodiment of the application, and a chip illustrated as a chip 500 in fig. 5. Chip 500 may include a processor 501, memory 502, and bus 503, among others.

It should be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the chip 500. In other embodiments of the present application, chip 500 may include more or less components than illustrated, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

Wherein the processor 501 may comprise one or more processing units. For example: the processor 501 may include a graphics processor (graphics processing unit, GPU), a central processor (central processing unit, CPU), and/or a neural network processor (neural network processing unit, NPU), etc. Wherein the different processing units may be separate components or may be integrated in one or more processors. In some embodiments, the chip 500 may also include one or more processors 501.

Processor 501 may be understood as the neural and command center of chip 500. The operation control signal can be generated according to the instruction operation code and the time sequence signal to finish the control of instruction fetching and instruction execution.

Memory 502 may be a cache unit for storing instructions and data. In some embodiments, memory 502 includes a register array and a gated clock cell provided by embodiments of the present application.

In one possible implementation, the memory 502 may be separate from the processor 501. I.e. the memory 502 may be connected to the processor 501 via a bus 503 for storing data, instructions or program code. When the processor 501 invokes and executes instructions or program codes stored in the memory 502, it can be implemented by invoking the register array circuit provided in the embodiment of the present application.

With the application of the chip provided by the present application, in the register array circuit provided by the present application for the chip with reference to the accompanying drawings, for example, a scenario that the data end of the register of the unselected address of the chip is turned over, and the gating clock input to the register is low, so that the internal circuit of the register is turned over invalidity is caused, the register array circuit is described by using the gating clock circuit to control the level value of the gating clock input to the register corresponding to each address.

Before describing the register array circuit provided in the embodiments of the present application, the internal circuits of the register will be described generally, as shown in fig. 6A, where the register is taken as a rising edge trigger register. The ports of the register include a data input terminal (D terminal), a clock input terminal (CLK terminal), a scan input terminal (SI terminal), a scan enable signal input terminal (SE terminal), a signal output terminal (Q terminal), and the like. The terminal D is coupled with a write data bus outside the register and used for receiving data information, the terminal CLK is coupled with the output terminal of a gating clock unit outside the register and used for receiving a gating clock, the terminal SI is used for inputting a scanning signal when a register test is carried out, the terminal SE is used for controlling the working mode of the register, the working mode is the normal working mode of the register (namely data writing is carried out) when the SE inputs a low level, the scanning mode is the register (namely the register is tested) when the SE inputs a high level, and the terminal Q is used for transmitting an output signal. The internal circuits of the register comprise SI and D end selection circuits, a low-pass high-latch lock circuit, a high-pass low-latch lock circuit and the like. The CLK terminal is coupled to the SI and D terminal selection circuits, the low pass high latch lock circuit, and the high pass low latch lock circuit, and includes the CLK terminal and clk_bb terminal in fig. 6A (clk_bb terminal is opposite to the signal input by CLK terminal). The SE terminals, SI terminals, and D terminals are coupled to the inputs of the SI and D terminal select circuits, the outputs of which are coupled to the low pass circuits (i.e., CLK0 and CLK0_b partial circuits in FIG. 6A) in the low pass high latch lock circuit, the outputs of which are coupled to the high pass circuits (i.e., CLK2 and CLK2_b partial circuits in FIG. 6A) in the high pass low latch lock circuit, the outputs of which are coupled to the Q terminal through an output inverter circuit. The low-pass high-latch lock circuit can be understood as a circuit for temporarily storing data information transmitted by the output ends of the SI and D end selection circuits, and only when the data information is stored in the high-pass low-latch lock circuit, the data writing of the register is completed.

When the register is a rising edge trigger register, a low level is input at the SE end and is in a normal working mode, when the CLK end output is low level, CLK0 and CLK0_b in fig. 6A are conducted, at this time, if the D end is turned to be low level, the circuits D0, SE0 and CLK0 are conducted to transmit data information of the D end, and if the D end is turned to be high level, the circuits d0_b, SE0_b and CLK0_b are conducted to transmit data information of the D end. The low-pass circuit in the SI and D end selection circuits and the low-pass high-latch lock circuit is conducted, and the data information transmitted by the D end is output from the low-pass circuit in the low-pass high-latch lock circuit. However, when the CLK terminal is at the low level, CLK1, CLK1_b, CLK2 and CLK2_b in fig. 6A are not conductive, so that the data information outputted from the low-pass circuit in the low-pass high-latch circuit is outputted directly through the inverter 1, but cannot pass through the high-pass circuit of the high-pass low-latch circuit, which corresponds to the data being temporarily stored in the low-pass high-latch circuit. Because the data information is not stored in the high-pass and low-lock latch circuit, which is equivalent to that the register is not written with data, the jump generated by the SI and D end selection circuits, the low-pass circuit in the low-pass and high-lock latch circuit and the inverter 1 during data transmission is invalid, and the jump can be understood as that the internal circuit of the register is empty.

When the CLK terminal is outputted at the high level, CLK0 and CLK0_b in fig. 6A are not conductive, CLK1, CLK1_b, CLK2 and CLK2_b are conductive, and at the moment when the CLK terminal is turned from the low level to the high level, the data information outputted through the inverter 1 is locked into the high lock circuit (i.e., the CLK1 and CLK1_b part circuits in fig. 6A) in the low-pass high lock circuit through the feedback circuit, and is also stored into the high-pass low lock circuit through the high-pass circuit in the high-pass low lock circuit, which is equivalent to the data information stored in the low-pass high lock circuit, namely, the data writing into the register is completed. When the output of the CLK terminal is at a high level, CLK0 and CLK0_b are not conducted, which is equivalent to that the low-pass circuits in the SI and D terminal selection circuits and the low-pass high-latch lock circuits are not conducted, so that the idle turn of the low-pass circuits in the SI and D terminal selection circuits and the low-pass high-latch lock circuits and the inverter 1 does not exist, and the power consumption waste can not be caused.

Register is a falling edge triggered register the internal register circuitry is shown in fig. 6B, unlike the rising edge triggered register where the outputs of the SI and D terminal select circuits are coupled to the high pass circuitry in the high pass low latch lock circuit (i.e., CLK0 and CLK 0B portion of the circuit in fig. 6B) whose outputs are coupled to the low pass circuitry in the low pass high latch lock circuit (i.e., CLK2 and CLK 2B portion of the circuit in fig. 6B) whose outputs are coupled to the Q terminal through an output inverter circuit. The high-pass low-lock latch circuit is understood to be used for temporarily storing data information transmitted by the output ends of the SI and D end selection circuits, and the data writing of the register is only completed when the data information is stored in the low-pass high-lock latch circuit.

When the register is a falling edge trigger register, a low level is input at the SE end and is in a normal working mode, when the CLK output is high level, CLK0 and CLK0_b in fig. 6B are conducted, at this time, if the D end is turned to be low level, the circuits D0, SE0 and CLK0 are conducted to transmit the data information of the D end, and if the D end is turned to be high level, the circuits d0_b, SE0_b and CLK0_b are conducted to transmit the data information of the D end. The high-pass circuit in the SI and D end selection circuits and the high-pass low-lock latch circuit is conducted, and the data information transmitted by the D end is output from the high-pass circuit in the high-pass low-lock latch circuit. However, when the CLK terminal is at the high level, CLK1, CLK1_b, CLK2 and CLK2_b in fig. 6B are not conductive, so that the data information outputted from the high-pass circuit in the high-pass low-latch circuit is outputted directly through the inverter 1, but cannot pass through the low-pass circuit of the low-pass high-latch circuit, which corresponds to the data being temporarily stored in the high-pass low-latch circuit. Because the data information is not stored in the low-pass high-latch lock circuit, which is equivalent to that the register is not written with data, the jump generated by the SI and D end selection circuits, the high-pass circuit in the high-pass low-latch lock circuit and the inverter 1 during data transmission is invalid, and can be understood as that the internal circuit of the register is empty.

When the CLK terminal is outputted at the low level, CLK0 and CLK0_b in fig. 6B are not conductive, CLK1, CLK1_b, CLK2 and CLK2_b are conductive, and at the moment when the CLK terminal is turned from the high level to the low level, the data information outputted through the inverter 1 is locked into the low lock circuit (i.e., the CLK1 and CLK1_b part circuits in fig. 6B) in the high-pass low-lock circuit through the feedback circuit, and is also stored into the low-pass high-lock circuit through the low-pass circuit in the low-pass high-lock circuit, which is equivalent to the data information stored in the high-pass low-lock circuit, namely, the data writing into the register is completed. When the CLK end outputs to be low level, CLK0 and CLK0_b are not conducted, which is equivalent to that the SI and D end selection circuits and the high-pass circuits in the high-pass low-lock latch circuits are not conducted, so that the SI and D end selection circuits, the high-pass circuits in the high-pass low-lock latch circuits and the inverter 1 are not turned over, and power consumption waste is avoided.

As shown in fig. 7A, a schematic diagram of a register array circuit according to an embodiment of the present application is provided, where the register array circuit includes: a plurality of registers and a plurality of gating clock circuits corresponding to the plurality of registers one by one.

Wherein the gating clock circuit is used for outputting the gating clock to the register. Each register of the plurality of registers has a different corresponding address, each register comprises a data input end and a clock input end, the data input end of each register is coupled with a write data bus shared by each register, the clock input end of each register is coupled with the output end of a corresponding gating clock circuit, the plurality of registers comprises a first register, the first register is a rising edge trigger register, and the first gating clock circuit corresponding to the first register is a gating clock circuit.

Illustratively, as shown in fig. 7A, the plurality of registers may include a first register, a second register, an nth register, etc. (N is an integer greater than 1), all being rising edge trigger registers. Each register is respectively corresponding to a gating clock circuit, the gating clock circuit corresponding to the first register is a first gating clock circuit, the gating clock circuit corresponding to the second register is a second gating clock circuit, the gating clock circuit corresponding to the N-th register is an N-th gating clock circuit and the like, and each gating clock circuit is a gating clock circuit. The data input end of the first register is an input end f, and the input end f is coupled with the write data bus. The clock input of the first register is input g, which is coupled to the output h of the first gating clock circuit. It will be appreciated that toggling on the write data bus enables toggling of the internal portion of the first register via input g, and the output of the first gating clock circuit is used to output a gating clock to the first register to control whether the first register is being written with data.

In some embodiments, the first gating clock circuit is to output a gating clock clamped high to the first register when the first register is not being subjected to a write access.

The first gating clock circuit is a gating clock circuit, as shown in fig. 7B, and is an internal structure schematic diagram of the gating clock circuit, and is composed of a high-pass low-lock latch, an inverter and an or gate. The high-pass low-lock latch is locked with two input ends, namely an enabling end (E end) and a clock input end (CLK end), wherein the enabling end is used for receiving address information indicated by a write address bus, when the address information indicated by the write address bus is the address of a register corresponding to the OR gate clock circuit, the enabling end is input into a high level, which is equivalent to that the address corresponding to the OR gate clock circuit is selected, and the register corresponding to the OR gate clock circuit is subjected to write access. The clock input is for receiving a write clock signal shared by each of the gated clock circuits. The output end (Q end) of the high-pass low-lock latch is coupled with one input end of the OR gate through an inverter, the other input end of the OR gate is used for receiving a write clock signal shared by each OR gate clock circuit, and the signal output by the output end of the OR gate is the gate clock output by the OR gate clock circuits.

The timing diagram of the or gate clock circuit shown in fig. 7B is shown in fig. 7C, and the address corresponding to the or gate clock circuit shown in fig. 7B is taken as address 1 as an example. In fig. 7C, the write clock signal is periodically flipped, and when the address information indicated by the write address bus is not address 1, that is, the address corresponding to the or gate clock circuit is not selected, the high-pass low latch lock enable terminal in fig. 7B is input as a low level. After the low level and the write clock signal input by the enabling end pass through the high-pass low latch lock, the output end of the high-pass low latch lock is low level, after the low level output by the output end of the high-pass low latch lock passes through the inverter, the output end of the inverter outputs high level, and after the high level and the write clock signal output by the inverter pass through the OR gate, the OR gate outputs high level, namely the output end of the OR gate clock circuit outputs high level. It will be appreciated that when an address is not selected, i.e. when the register corresponding to the address is not being written to, the output of the register corresponding to or clock gating circuit outputs a high level.

For example, the fact that the first register is not subjected to write access may be understood that an address corresponding to the first register is not selected, and at this time, the first gating clock circuit outputs a gating clock clamped to a high level to the first register, and may be understood that the first gating clock circuit clamps a clock input terminal of the first register to a high level. When the clock input end of the rising edge trigger register keeps high level, the SI and D end selection circuits inside the rising edge trigger register and the low-pass circuit in the low-pass high-latch lock circuit are not conducted, so that the empty turning of the internal circuit of the rising edge trigger register can be reduced, and the power consumption waste is avoided.

In some embodiments, when the first register is subjected to write access, the first gating clock circuit is further configured to transition the gating clock output to the first register from a high level to a low level, clamp the gating clock to the low level, and transition the gating clock output to the first register from the low level to the high level.

Wherein the first register is written with data when the gate clock output to the first register transitions from a low level to a high level. As shown in fig. 7C, taking the address corresponding to the or gate clock circuit shown in fig. 7B as address 1 as an example, when the address information indicated by the write address bus is address 1, that is, when the address corresponding to the or gate clock circuit is selected, the high-pass low latch lock enable terminal in fig. 7B is input with a high level. After the high level and the write clock signal input by the enabling end pass through the high-pass low-lock latch, the output end of the high-pass low-lock latch is high level (the output high level is not necessarily aligned with the write clock signal period), after the high level output by the output end of the high-pass low-lock latch passes through the inverter, the output end of the inverter outputs low level, and after the low level output by the inverter and the write clock signal pass through the OR gate, the OR gate outputs low level, namely the output end of the OR gate clock circuit outputs low level. And the output end of the or gate clock circuit jumps from low level to high level after outputting low level for a period of time, and at the moment that the output end of the or gate clock circuit jumps from low level to high level, data is written into a register corresponding to the or gate clock circuit. It can be understood that when an address is selected, that is, when a register corresponding to the address is accessed by writing, the gating clock corresponding to the register or output by the output end of the clock gating circuit jumps from high level to low level, and continuously outputs the low level for a period of time, and then jumps from low level to high level, and writes data into the register at the moment of jumping from low level to high level. The jump position of the output terminal of the gating clock circuit corresponding to the register shown in fig. 7B may be adjusted according to an actual circuit, and the timing diagram is merely an example.

By way of example, when the first register is subjected to write access, it may be understood that an address corresponding to the first register is selected, at this time, the first gating clock circuit may first transition the gating clock output to the first register from a high level to a low level, that is, the first gating clock circuit transitions the clock input end of the first register from a high level to a low level and clamps the clock input end to the low level, which may be understood that a rising edge triggers that low-pass circuits in SI and D end selection circuits and low-pass high latch lock circuits inside the register are turned into, and data information transmitted by the D end is stored in the low-pass high latch lock circuit. The first gating clock circuit jumps the gating clock output to the first register from low level to high level, namely the first gating clock circuit jumps the clock input end of the first register from low level to high level. When the gate clock output to the first register transitions from low level to high level, that is, when the clock input terminal of the first register transitions from low level to high level, the first register is written with data, and it can be understood that the high-pass low-latch lock circuit in the rising edge trigger register is turned on at the moment when the clock input terminal of the first register transitions from low level to high level, at this time, the data information stored in the low-pass high-latch lock circuit is written into the high-pass low-latch lock circuit, which is equivalent to the first register being written with data.

In some embodiments, each of the plurality of gating clock circuits further includes a first input coupled to the write address bus shared by each of the gating clock circuits, the first input being understood as the enable in FIG. 7B, and a second input for receiving the write clock signal shared by each of the gating clock circuits, the second input being understood as the clock input in FIG. 7B.

Illustratively, as shown in FIG. 7A, the first gating clock circuit includes a first input i coupled to the write address bus and a second input j for receiving the write clock signal.

In some embodiments, the signal at the first input of the first gating clock circuit is used to indicate that the first address of the first register is not selected when the first register is not being subjected to a write access.

For example, the fact that the first register is not subjected to the write access may be understood that the address corresponding to the first register is not selected, and at this time, a signal at the first input end of the first gating clock circuit corresponding to the first register is used to indicate that the first address of the first register is not selected. For example, when the write address bus is the second address, the signal at the first input of the first gating clock circuit is used to indicate that the first address is not selected.

Therefore, in the register array circuit provided by the embodiment of the application, when the register array is a rising edge trigger register, the gating clock circuit outputs the gating clock clamped to the high level to the register which is not subjected to write access, namely, the clock input end of the register which is not subjected to write access is clamped to the high level, so that the low-pass circuits in the SI and D end selection circuits and the low-pass high latch lock circuit in the register are not conducted, and the SI and D end selection circuits, the low-pass circuits and the inverter in the low-pass high latch lock circuit are not turned over in a null manner, thereby avoiding the waste of power consumption, improving the power consumption utilization rate, reducing the number of windings and the circuit area, and being convenient for physical realization.

As shown in fig. 7D, another schematic diagram of a register array circuit according to an embodiment of the present application includes: a plurality of registers and a plurality of gating clock circuits corresponding to the plurality of registers one by one.

Wherein the gating clock circuit is used for outputting the gating clock to the register. Each register in the plurality of registers corresponds to different addresses, each register comprises a data input end and a clock input end, the data input end of each register is coupled with a write data bus shared by each register, the clock input end of each register is coupled with the output end of a corresponding gating clock circuit, the plurality of registers comprise a first register, the first register is a falling edge trigger register, and the first gating clock circuit corresponding to the first register is a gating clock circuit.

Illustratively, as shown in fig. 7D, the plurality of registers may include a first register, a second register, an nth register, etc. (N is an integer greater than 1), all being falling edge triggered registers. Each register is respectively corresponding to a gating clock circuit, the gating clock circuit corresponding to the first register is a first gating clock circuit, the gating clock circuit corresponding to the second register is a second gating clock circuit, the gating clock circuit corresponding to the N-th register is an N-th gating clock circuit and the like, and each gating clock circuit is a gating clock circuit. The data input end of the first register is an input end k, and the input end k is coupled with the write data bus. The clock input of the first register is input l, which is coupled to the output m of the first gating clock circuit. It will be appreciated that toggling on the write data bus enables toggling of the internal portion of the first register via input l, the output of the first gating clock circuit being used to output a gating clock to the first register to control whether the first register is being written with data.

In some embodiments, the first gating clock circuit is to output a gating clock clamped to a low level to the first register when the first register is not being subjected to a write access.

The first gating clock circuit is a gating clock circuit, as shown in fig. 7E, and is an internal structure schematic diagram of the gating clock circuit, and is composed of a low-pass high-lock latch, an inverter and an and gate. The low-pass high latch is locked with two input ends, namely an enabling end (E end) and a clock input end (CLK end), wherein the enabling end is used for receiving address information indicated by a write address bus, when the address information indicated by the write address bus is the address of a register corresponding to the gating clock circuit, the enabling end is input into a high level, and the address corresponding to the gating clock circuit is selected, and the register corresponding to the gating clock circuit is subjected to write access. The clock input is for receiving a write clock signal shared by each of the gated clock circuits. The output end (Q end) of the low-pass high-lock latch is coupled with one input end of the AND gate, the other input end of the AND gate is used for receiving the write clock signal shared by each AND gate clock circuit, and the signal output by the output end of the AND gate is the gate clock output by the AND gate clock circuits.

The timing diagram of the gating clock circuit shown in fig. 7E is shown in fig. 7F, and the address corresponding to the gating clock circuit shown in fig. 7E is taken as address 1 as an example. In fig. 7F, the write clock signal is periodically toggled, and when the address information indicated by the write address bus is not address 1, that is, the address corresponding to the gating clock circuit is not selected, the low-pass high-lock latch enable terminal in fig. 7E is input as a low level. The low level and the write clock signal input by the enabling end pass through the low-pass high-latch lock, the output end of the low-pass high-latch lock is low level, and the low level and the write clock signal output by the output end of the high-pass low-latch lock pass through the AND gate, and the AND gate outputs low level, namely the output end of the AND gate clock circuit outputs low level. It will be appreciated that when an address is not selected, i.e. when a register corresponding to the address is not being written to, the output of the register corresponding to the clock gating circuit outputs a low level.

For example, the fact that the first register is not subjected to write access may be understood that an address corresponding to the first register is not selected, and at this time, the first gating clock circuit outputs a gating clock clamped to a low level to the first register, which may be understood that the first gating clock circuit clamps a clock input terminal of the first register to a low level. When the clock input end of the falling edge trigger register keeps low level, the SI and D end selection circuits and the high-pass circuits in the high-pass low-latch lock circuit in the falling edge trigger register are not conducted, so that the empty flip of the internal circuits of the falling edge trigger register can be reduced, and the power consumption waste is avoided.

In some embodiments, when the first register is subjected to write access, the first gating clock circuit is further configured to transition the gating clock output to the first register from a low level to a high level, clamp the gating clock to the high level, and transition the gating clock output to the first register from the high level to the low level.

Wherein the first register is written with data when the gate clock output to the first register transitions from a high level to a low level. As shown in fig. 7F, taking the address corresponding to the gating clock circuit shown in fig. 7E as address 1 as an example, when the address information indicated by the write address bus is address 1, that is, when the address corresponding to the gating clock circuit is selected, the low-pass high-lock latch enable terminal in fig. 7E is input with a high level. After the high level and the write clock signal input by the enabling end pass through the low-pass high latch lock, the output end of the low-pass high latch lock is high level (the output high level is not necessarily aligned with the cycle of the write clock signal), and after the high level and the write clock signal output by the output end of the low-pass high latch lock pass through the AND gate, the AND gate outputs the high level, namely the output end of the AND gate clock circuit outputs the high level. And the output end of the AND gate clock circuit jumps from high level to low level after outputting high level for a period of time, and at the moment that the output end of the AND gate clock circuit jumps from high level to low level, data are written into a register corresponding to the AND gate clock circuit. It can be understood that when an address is selected, that is, when a register corresponding to the address is accessed by writing, the gating clock output by the output terminal of the clock gating circuit corresponding to the register jumps from low level to high level, and after a period of time when the high level is continuously output, the high level jumps from high level to low level, and data is written into the register at the moment when the high level jumps to low level. The jump position of the output terminal of the gating clock circuit corresponding to the register shown in fig. 7E may be adjusted according to an actual circuit, and the timing chart is merely an example.

By way of example, when the first register is subjected to write access, it may be understood that an address corresponding to the first register is selected, at this time, the first gating clock circuit may first transition the gating clock output to the first register from a low level to a high level, that is, the first gating clock circuit transitions the clock input end of the first register from a low level to a high level and clamps the clock input end to the high level, which may be understood that a falling edge triggers that the SI and D end selection circuits inside the register and the high-pass low-lock latch are turned into a conductive state when the high-pass circuit is not turned on, and data information transmitted by the D end is stored in the high-pass low-lock latch circuit. The first gating clock circuit jumps the gating clock output to the first register from high level to low level, namely the first gating clock circuit jumps the clock input end of the first register from high level to low level. When the gate clock output to the first register transitions from high level to low level, that is, when the clock input terminal of the first register transitions from high level to low level, the first register is written with data, and it can be understood that the low-pass high latch lock circuit inside the falling edge trigger register is turned on at the moment when the clock input terminal of the first register transitions from high level to low level, at this time, the data information stored in the high-pass low latch lock circuit is written into the low-pass high latch lock circuit, which is equivalent to the first register being written with data.

In some embodiments, each of the plurality of gating clock circuits further includes a first input coupled to the write address bus shared by each of the gating clock circuits, the first input being understood as the enable in FIG. 7E, and a second input for receiving the write clock signal shared by each of the gating clock circuits, the second input being understood as the clock input in FIG. 7E.

Illustratively, as shown in FIG. 7D, the first gating clock circuit includes a first input o coupled to the write address bus and a second input p for receiving the write clock signal.

Therefore, in the register array circuit provided by the embodiment of the application, when the register array is a falling edge trigger register, the gating clock circuit outputs the gating clock clamped to the low level to the register which is not subjected to the write access, namely, the clock input end of the register which is not subjected to the write access is clamped to the low level, so that the high-pass circuits in the SI and D end selection circuits and the high-pass low-lock latch of the register are not conducted, the SI and D end selection circuits, the high-pass circuits and the inverter in the high-pass low-lock latch are not turned over, the power consumption waste is avoided, the power consumption utilization rate is improved, the winding quantity and the circuit area are reduced, and the physical implementation is convenient.

As shown in fig. 8, an embodiment of the present application provides a flowchart of a method for accessing a register array, taking the register array circuit shown in fig. 7A as an example, where the register is a rising edge trigger register. That is, the gating clock unit of the or clock gating circuit in fig. 4A may be the first gating clock circuit in fig. 7A, the write address bus in fig. 4A is the write address bus in fig. 7A, the register array in fig. 4A includes the first register in fig. 7A, and so on. The method is applied to the register array circuit shown in fig. 7A, and the specific register array circuit structure can be seen from the description of fig. 7A. The method comprises the following steps:

Step 801, when it is determined that the first register is not being subjected to write access, indicates that the first address of the first register is not selected through a signal of the first input terminal of the first gating clock circuit.

For example, as shown in fig. 7A, when it is determined that the first register is not subjected to the write access, it may be understood that, when it is determined that the address corresponding to the first register is not selected, a signal of the first input terminal of the first gating clock circuit corresponding to the first register indicates that the first address of the first register is not selected.

Step 802, outputting a gating clock clamped to a high level to the first register through the first gating clock circuit when it is determined that the first register is not subjected to write access.

For example, as shown in fig. 7A, when it is determined that the first register is not subjected to the write access, it can be understood that when it is determined that the address corresponding to the first register is not selected, the gate clock clamped to the high level is output to the first register by the first gate clock circuit, that is, the clock input terminal of the first register is clamped to the high level by the first gate clock circuit. When the clock input end of the rising edge trigger register keeps high level, the SI and D end selection circuits inside the rising edge trigger register and the low-pass circuit in the low-pass high-latch lock circuit are not conducted, so that the empty turning of the internal circuit of the rising edge trigger register can be reduced, and the power consumption waste is avoided.

In some embodiments, when it is determined that the first register is subjected to write access, the gating clock output to the first register through the first gating clock circuit transitions from high to low, i.e., the clock input terminal of the first register transitions from high to low, clamps to low, and transitions from low to high, i.e., the clock input terminal of the first register transitions from low to high, and writes data to the first register when the clock input terminal of the first register transitions from low to high.

For example, when it is determined that the first register is subjected to write access, a specific control procedure of the first gating clock circuit to the clock input terminal of the first register and a procedure of writing data to the first register may be referred to the above description of fig. 7A.

Therefore, in the method for accessing the register array, when the register array is a rising edge trigger register, the gating clock circuit outputs the gating clock clamped to the high level to the first register, namely, the clock input end of the register which is not subjected to write access is clamped to the high level, so that the low-pass circuits in the internal SI and D end selection circuits and the low-pass high-latch lock circuit of the register are not conducted and are not turned over in idle mode, further, the power consumption waste is avoided, the power consumption utilization rate is improved, the winding quantity and the circuit area are reduced, and the physical implementation is convenient.

As shown in fig. 9, an embodiment of the present application provides a flowchart of a method for accessing a register array, taking the register array circuit shown in fig. 7D as an example, where the register is a falling edge trigger register. That is, the gating clock cell including the and clock gating circuit in fig. 4B may be the first gating clock circuit in fig. 7D, the write address bus in fig. 4B is the write address bus in fig. 7D, the register array in fig. 4B includes the first register in fig. 7D, and so on. The method is applied to the register array circuit shown in fig. 7D, and the specific register array circuit structure can be seen from the description of fig. 7D. The method comprises the following steps:

step 901, when it is determined that the first register is not being subjected to write access, indicating that the first address of the first register is not selected by a signal of the first input terminal of the first gating clock circuit.

For example, as shown in fig. 7D, when it is determined that the first register is not subjected to the write access, it may be understood that when it is determined that the address corresponding to the first register is not selected, a signal of the first input terminal of the first gating clock circuit corresponding to the first register indicates that the first address of the first register is not selected.

Step 902, outputting a gating clock clamped to a low level to the first register through a first gating clock circuit when it is determined that the first register is not subjected to write access.

For example, as shown in fig. 7D, when it is determined that the first register is not subjected to the write access, it can be understood that the gate clock clamped to the low level is output to the first register by the first gate clock circuit, that is, the clock input terminal of the first register is clamped to the low level by the first gate clock circuit, when it is determined that the address corresponding to the first register is not selected. When the clock input end of the falling edge trigger register keeps low level, the SI and D end selection circuits and the high-pass circuits in the high-pass low-latch lock circuit in the falling edge trigger register are not conducted, so that the empty flip of the internal circuits of the falling edge trigger register can be reduced, and the power consumption waste is avoided.

In some embodiments, when it is determined that the first register is subjected to write access, the gating clock output to the first register through the first gating clock circuit transitions from low to high, i.e., the clock input terminal of the first register transitions from low to high, clamps to high, and transitions from high to low, i.e., the clock input terminal of the first register transitions from high to low, and writes data to the first register when the clock input terminal of the first register transitions from high to low.

For example, when it is determined that the first register is subjected to write access, a specific control procedure of the first gating clock circuit to the clock input terminal of the first register and a procedure of writing data to the first register may be referred to the above description of fig. 7B.

Therefore, in the method for accessing the register array, when the register array is a falling edge trigger register, the gating clock circuit outputs the gating clock clamped to be low level to the first register, namely, the clock input end of the register which is not subjected to write access is clamped to be low level, so that the high-pass circuits in the internal SI and D end selection circuits of the register and the high-pass low-latch lock circuit are not conducted and are not turned over in idle mode, further, the power consumption waste is avoided, the power consumption utilization rate is improved, the winding quantity and the circuit area are reduced, and the physical implementation is convenient.

In the following, taking fig. 10 as an example, a register array circuit provided in the embodiment of the present application is described, where the register array is a rising edge trigger register.

The register array includes, for example, a 0 address register, a 1 address register, an n address register, and the like (n is an integer greater than 1) shown in fig. 10, and represents a register of address 0, a register of address 1, and a register of address n, respectively, that is, the addresses corresponding to each register are different. The clock input r of each register is coupled to the output s of a corresponding or gating clock circuit, and the data input q of each register shares a write data bus. One input terminal t is controlled by a write address bus shared by each of the or gate clock circuits, and the other input terminal u is used for receiving a write clock signal shared by each of the or gate clock circuits. When address information=0 indicated by the write address bus, that is, when the 0 address is selected to write data, the output end of the gating clock circuit corresponding to the 0 address register makes rising edge transitions (the output end of the gating clock circuit transitions from low level to high level), the output ends of the gating clock circuits corresponding to the other unselected address registers do not make transitions (the output end of the gating clock circuit maintains high level), and data information carried on the write data bus is written into the 0 address register when the output end of the gating clock circuit makes rising edge transitions. When address information=0 indicated by the write address bus, the rest addresses are not selected (for example, 1 address and n address are not selected), the registers corresponding to the unselected addresses (for example, 1 address register and n address register) are not subjected to write access, the output end of the or gate clock circuit corresponding to the registers not subjected to write access clamps the clock input end of the registers to be high level, so that the low-pass circuits in the internal SI and D end selection circuits and the low-pass high-lock latch of the registers are not conducted, and do not turn over, thereby avoiding power consumption waste, improving power consumption utilization rate, reducing the number of windings and circuit area, and being convenient for physical realization.

FIG. 11 is a timing diagram of the register array circuit of FIG. 10. When the write clock signal is periodically flipped and address information indicated by the write address bus=0, the 0 address is selected, the 0 address register is subjected to write access, the output end of the OR gate clock circuit corresponding to the 0 address register is subjected to rising edge jump, at this time, the 0 address register is written with data, and the data in the write data bus is written into the 0 address register. When address information=0 indicated by the write address bus, the registers corresponding to the other unselected addresses are not subjected to write access, and the output ends of the OR gate clock circuits corresponding to the registers not subjected to write access do not jump. Taking the output end of the gating clock circuit corresponding to the 1 address register as an example, when address information=0 indicated by the address bus is written, the output end of the gating clock circuit corresponding to the 1 address register keeps high level and does not jump, namely the 1 address register is not written with data. The jump position of the output terminal of the gating clock circuit corresponding to the register shown in fig. 11 may be adjusted according to an actual circuit, and the timing chart is merely an example.

Another register array circuit according to the embodiment of the present application will be described with reference to fig. 12, in which the register array is a falling edge trigger register.

The register array includes, for example, a 0 address register, a 1 address register, an n address register, and the like (n is an integer greater than 1) shown in fig. 12, and represents a register of address 0, a register of address 1, and a register of address n, respectively, that is, the addresses corresponding to each register are different. The clock input w of each register is coupled to the output x of the corresponding gating clock circuit, and the data input v of each register shares a write data bus. One input y of the two inputs of the gating clock circuits is controlled by a write address bus shared by each gating clock circuit, and the other input z is used for receiving a write clock signal shared by each gating clock circuit. When address information=0 indicated by the write address bus, that is, when the 0 address is selected to write data, the output end of the gating clock circuit corresponding to the 0 address register makes a falling edge transition (the output end of the gating clock circuit transitions from a high level to a low level), the output ends of the gating clock circuits corresponding to the remaining unselected address registers do not make transitions (the output end of the gating clock circuit maintains a low level), and data information carried on the write data bus is written into the 0 address register when the output end of the gating clock circuit makes a falling edge transition. When address information=0 indicated by the write address bus, the rest addresses are not selected (for example, 1 address and n address are not selected), the registers corresponding to the unselected addresses (for example, 1 address register and n address register) are not subjected to write access, the output end of the gating clock circuit corresponding to the registers not subjected to write access clamps the clock input end of the registers to be low level, so that the high-pass circuits in the internal SI and D end selection circuits and the high-pass low-lock latch of the registers are not conducted, and do not turn over, thereby avoiding power consumption waste, improving power consumption utilization rate, reducing the number of windings and circuit area, and being convenient for physical realization.

FIG. 13 is a timing diagram of the register array circuit of FIG. 12. When the write clock signal is periodically flipped and address information indicated by the write address bus=0, the 0 address is selected, the 0 address register is subjected to write access, the output end of the gating clock circuit corresponding to the 0 address register is subjected to falling edge hopping, at this time, the 0 address register is written with data, and the data in the write data bus is written into the 0 address register. When address information=0 indicated by the write address bus, the registers corresponding to the other unselected addresses are not subjected to write access, and the output ends of the gating clock circuits corresponding to the registers not subjected to write access do not jump. Taking the output end of the gating clock circuit corresponding to the 1 address register as an example, when address information=0 indicated by the address bus is written, the output end of the gating clock circuit corresponding to the 1 address register keeps low level and does not jump, namely the 1 address register is not written with data. The jump position of the output terminal of the gating clock circuit corresponding to the register shown in fig. 13 may be adjusted according to an actual circuit, and the timing chart is merely an example.

It will be appreciated that the electronic device, in order to implement the above-described functions, includes corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Those skilled in the art may implement the described functionality using different approaches for each particular application, but such implementation is not to be considered as beyond the scope of the embodiments of the present application.

The embodiment of the application may divide the functional modules of the electronic device according to the method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated modules may be implemented in hardware or in software functional modules. It should be noted that, in the embodiment of the present application, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation.

In the case of an integrated unit, as shown in fig. 14, an electronic device 1400 is disclosed in the embodiment of the present application, and the electronic device 1400 may be a chip in the above embodiment. The electronic device 1400 may include a processing module and a storage module. The processing module may be configured to determine address information indicated by the write address bus, send address information of a register to be accessed to the memory module through the write address bus, and send data to be written to the memory module through the write data bus. The memory module may be used to support the electronic device 1400 to store program codes and data, etc., and may also be used to support the electronic device 1400 to perform steps 801, 802, 901, and 902 described above.

Of course, the unit modules in the electronic device 1400 include, but are not limited to, the processing modules and the storage modules described above.

Wherein the processing module may be the processor 1401 (such as the processor 501 shown in fig. 5), and the storage module may be the memory 1402 (such as the memory 502 shown in fig. 5). The electronic device 1400 provided in the embodiments of the present application may be the chip 500 shown in fig. 5. Wherein the processor and the memory etc. may be coupled together, for example the processor is coupled to the memory via a write address bus and a write data bus.

Embodiments of the present application also provide an electronic device including one or more processors and one or more memories. The one or more memories are coupled to the one or more processors, the one or more memories being operable to store computer program code comprising computer instructions that, when executed by the one or more processors, cause the electronic device to perform the related method steps described above to implement the method of limiting power consumption in the above-described embodiments.

Embodiments of the present application also provide a computer readable storage medium having computer program code stored therein, which when executed by a processor, causes an electronic device to perform the method of accessing a register array in the above embodiments.

Embodiments of the present application also provide a computer program product which, when run on a computer, causes the computer to perform the above-described related steps to implement the method of accessing a register array performed by the electronic device in the above-described embodiments.

The electronic device, the computer storage medium, the computer program product, or the chip provided in this embodiment are used to execute the corresponding methods provided above, so that the advantages achieved by the electronic device, the computer storage medium, the computer program product, or the chip can refer to the advantages of the corresponding methods provided above, and are not described herein.

It will be appreciated by those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional modules is illustrated, and in practical application, the above-described functional allocation may be performed by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to perform all or part of the functions described above.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another apparatus, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and the parts displayed as units may be one physical unit or a plurality of physical units, may be located in one place, or may be distributed in a plurality of different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a readable storage medium. Based on such understanding, the technical solution of the embodiments of the present application may be essentially or a part contributing to the prior art or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, including several instructions for causing a device (may be a single-chip microcomputer, a chip or the like) or a processor (processor) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A register array circuit, wherein the register array circuit comprises a plurality of registers and a plurality of gating clock circuits corresponding to the registers one by one, and the gating clock circuits are used for outputting gating clocks to the registers; the plurality of registers includes a first register, the first register being a rising edge trigger register; the first gating clock circuit corresponding to the first register is a gating clock circuit;

the first gating clock circuit is configured to output a gating clock clamped to a high level to the first register when the first register is not being subjected to write access.
The register array circuit of claim 1, wherein the register array circuit comprises,

when the first register is accessed by writing, the first gating clock circuit is also used for jumping the gating clock output to the first register from high level to low level, clamping the gating clock to low level and then jumping the gating clock output to the first register from low level to high level;

Wherein the first register is written with data when a gate clock outputted to the first register transitions from a low level to a high level.
The register array circuit of claim 1 or 2, wherein each of the plurality of gating clock circuits further comprises a first input coupled to a write address bus shared with each gating clock circuit and a second input for receiving a write clock signal shared with said each gating clock circuit.
A register array circuit as claimed in claim 3, wherein the signal at the first input of the first gating clock circuit is used to indicate that the first address of the first register is not selected when the first register is not being subjected to a write access.
A register array circuit, wherein the register array circuit comprises a plurality of registers and a plurality of gating clock circuits corresponding to the registers one by one, and the gating clock circuits are used for outputting gating clocks to the registers; the plurality of registers includes a first register, which is a falling edge trigger register; the first gating clock circuit corresponding to the first register is a gating clock circuit;

The first gating clock circuit is configured to output a gating clock clamped to a low level to the first register when the first register is not being subjected to write access.
The register array circuit of claim 5, wherein the register memory is configured to store the data,

when the first register is accessed by writing, the first gating clock circuit is also used for jumping the gating clock output to the first register from low level to high level, clamping the gating clock to high level and then jumping the gating clock output to the first register from high level to low level;

wherein the first register is written with data when a gate clock outputted to the first register transitions from a high level to a low level.
The register array circuit of claim 5 or 6, wherein each of the plurality of gate clock circuits further comprises a first input coupled to a write address bus shared with each gate clock circuit and a second input for receiving a write clock signal shared with said each gate clock circuit.
The register array circuit of claim 7, wherein the signal at the first input of the first gating clock circuit is used to indicate that the first address of the first register is not selected when the first register is not being write-accessed.
A method of accessing a register array, the method being applied to a register array circuit, the register array circuit comprising a plurality of registers and a plurality of gating clock circuits in one-to-one correspondence with the plurality of registers, the gating clock circuits for outputting gating clocks to the registers; the plurality of registers includes a first register, the first register being a rising edge trigger register; the first gating clock circuit corresponding to the first register is a gating clock circuit;

when it is determined that the first register is not subjected to write access, a gating clock clamped to a high level is output to the first register through the first gating clock circuit.
The method according to claim 9, wherein the method further comprises:

when the first register is determined to be subjected to write access, the gating clock output to the first register through the first gating clock circuit jumps from high level to low level, clamps to low level, and jumps from low level to high level;

wherein data is written to the first register when a gating clock output to the first register transitions from a low level to a high level.
The method of claim 9 or 10, wherein each of the plurality of gating clock circuits further comprises a first input coupled to a write address bus shared with each gating clock circuit and a second input for receiving a write clock signal shared with said each gating clock circuit.
The method of claim 11, wherein the method further comprises: when it is determined that the first register is not being subjected to write access, a signal through a first input terminal of the first gating clock circuit indicates that a first address of the first register is not selected.
A method of accessing a register array, the method being applied to a register array circuit, the register array circuit comprising a plurality of registers and a plurality of gating clock circuits in one-to-one correspondence with the plurality of registers, the gating clock circuits for outputting gating clocks to the registers; the plurality of registers includes a first register, which is a falling edge trigger register; the first gating clock circuit corresponding to the first register is a gating clock circuit;

When it is determined that the first register is not subjected to write access, a gating clock clamped to a low level is output to the first register through the first gating clock circuit.
The method of claim 13, wherein the method further comprises:

when the first register is determined to be subjected to write access, the gating clock output to the first register through the first gating clock circuit jumps from low level to high level, clamps to high level, and jumps from high level to low level;

and when the gating clock output to the first register jumps from a high level to a low level, writing data into the first register.
The method of claim 13 or 14, wherein each of the plurality of gating clock circuits further comprises a first input coupled to a write address bus shared with each gating clock circuit and a second input for receiving a write clock signal shared with said each gating clock circuit.
The method of claim 15, wherein the method further comprises: when it is determined that the first register is not being subjected to write access, a signal through a first input terminal of the first gating clock circuit indicates that a first address of the first register is not selected.
A computer readable storage medium comprising computer instructions which, when run on an electronic device, cause the electronic device to perform the method of any of the preceding claims 9-12.
A computer readable storage medium comprising computer instructions which, when run on an electronic device, cause the electronic device to perform the method of any of the preceding claims 13-16.
A computer program product, characterized in that the computer program product, when run on a computer, causes an electronic device to perform the method of any of the preceding claims 9-12.
A computer program product, characterized in that the computer program product, when run on a computer, causes an electronic device to perform the method of any of the preceding claims 13-16.