JPH0944644A - Image processor and control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor by which an image memory is divided into plural areas and the access to the respective areas can be easily switched and to provide a control method therefor. SOLUTION: Plural load values showing an initial address value to be given to the address counter of an address controller 318 are set, and since the space of a memory 309 for storing image data is divided into plural areas by switching the load values corresponding to an enable signal or a designate signal from a CPU, a data controller 319 can easily access the respective areas.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and a control method thereof, and, for example, after image processing of input image information, the image information is temporarily stored in an image memory and the image information read from the image memory is stored. The present invention relates to an output image processing device and a control method thereof.

[0002]

2. Description of the Related Art There is a device that performs image processing on full-color image information read by an image input device, temporarily stores it in an image memory, and outputs the full-color image information read from the image memory to an output device. In this device, when using the automatic document feeder to copy multiple documents continuously,
If the original size is smaller than half the maximum size that can be stored, the image memory is divided into two areas, the Nth original image is stored in one memory area, and the other memory area is stored. It is conceivable to increase the copying speed by the so-called double buffer method in which the image information of the (N + 1) th sheet is stored and the image processing can be continuously performed. Also,
When double-sided copying is performed by the double buffer method, the copying speed can be similarly increased by storing the first side of the original document in one memory area and the second side in the other memory area.

[0003]

However, the above-mentioned technique has the following problems. That is, in order to store the image data in the image memory by the double buffer method, when the CPU controls the address given to the image memory, after storing the first image data in the image memory, the second image After the address control for data is performed, the automatic document feeder must start feeding the document. Therefore, a waiting time is generated in the meantime, and as a result, the copying speed is reduced. Further, at the time of jam processing in double-sided copying, it is necessary to determine whether the image is the first image or the second image and switch the address control.

The present invention is for solving the above-mentioned problem, and provides an image processing apparatus capable of dividing an image memory into a plurality of areas and easily switching access to each area, and a control method thereof. The purpose is to provide.

[0005]

The present invention has the following structure as one means for achieving the above object.

The image processing apparatus according to the present invention comprises a first generating means for generating an address signal representing a storage area of the storage means, and a second generating means for generating a control signal for storing image data in the storage means. Generating means, first controlling means for controlling the first and second generating means, and storing the input image data in the storing means based on the address signal and the control signal, and storing the image data. Second control means for reading out the image data stored in the means, the first control means sets a plurality of different address initial values in the first generating means, and based on a predetermined signal. Then, the set address initial value is switched.

Further, a reading means for reading the original image, a first generating means for generating an address signal representing a storage area of the storage means, and a second generation means for generating a control signal for storing the image data in the storage means. Generating means, first control means for controlling the first and second generating means, and image data output from the reading means stored in the storage means based on the address signal and the control signal. The first control means includes: second control means for reading the image data stored in the storage means; and forming means for forming an image based on the image data read from the storage means. Is characterized in that a plurality of different address initial values are set in the first generating means, and the set address initial values are switched based on a predetermined signal.

The control method of the image processing apparatus according to the present invention comprises a setting step of setting a plurality of different address initial values in the first generation means for generating an address signal representing the storage area of the storage means, A switching step of switching the address initial value set in the first generating means based on a predetermined signal, and a control for storing the image data in the storage means generated by the address signal and the second generating means. A storage step of storing the input image data in the storage means based on a signal; and a reading step of reading the image data stored in the storage means based on the address signal and the control signal. Is characterized by.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image processing apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings.

[0010]

First Embodiment [Outline of Apparatus] FIG. 1 is a schematic view showing a configuration example of an image processing apparatus according to an embodiment of the present invention.

In FIG. 1, reference numeral 1201 denotes a platen glass on which a document 1202 for reading an image is placed. The original 1202 is illuminated by the illumination 1203, and the reflected light from the original 1202 is reflected by the mirror 1204 to
After 1206, an image is formed on the sensor 1208 by the optical system 1207. The sensor 1208 is an RGB three-line CCD sensor. In addition, the motor 1209 mechanically causes the mirror 1204 and the illumination 12
Mirror unit 1210 including 03 is speed V, mirror 1205,12
The second mirror unit 1211 including 06 is driven at the speed V / 2, and the entire surface of the original 1202 is scanned.

An image processing unit 1212 is a unit for processing the read image as an electric signal and outputting it as a print signal.

Reference numerals 1213 to 1216 denote semiconductor lasers, which are driven by the print signals output from the image processing unit 1212. The laser light emitted from each semiconductor laser is
The electrostatic latent image is formed on the photosensitive drums 1225-1228 by being scanned by the polygon mirrors 1217-1220. 1221-1224 is K,
The developing devices for developing the latent images with the Y, C, and M toners respectively transfer the developed toners of the respective colors to the recording paper to obtain a full-color print output.

The recording paper supplied from any of the recording paper cassettes 1229 to 1231 or the manual feed tray 1232 is adsorbed on the transfer belt 1234 via the registration roller 1233 and conveyed. Photosensitive drum 1228 is synchronized with the paper feed timing.
To 1225 are developed with toner of each color, and the toner is transferred to the recording paper as the recording paper is conveyed.

The recording paper on which the toners of the respective colors have been transferred is separated and conveyed from the transfer belt 1234, the toner is fixed by the fixing device 1235, and the recording paper is discharged to the paper discharge tray 1236.

[Image Processing Unit] FIGS. 2A and 2B are block diagrams showing a configuration example of the image processing unit 1212.

In the figure, 101 is the CCD of the sensor 1208,
The input reflected light from the original 1201 is decomposed into three components of R, G, and B, and an electric signal corresponding to each color component is output.

Reference numeral 102 denotes an analog processing section, which is composed of an amplifier, a sample-and-hold, an A / D converter, a delay memory, etc., which amplifies the output of the CCD 101, performs sample-and-hold, and A / D-converts the signal R. And G are delayed by a delay memory for a predetermined time and the spatial shifts of the three CCDs are corrected and output as, for example, 8-bit digital image signals.

A shading correction unit 103 corrects the output of the analog processing unit 102 according to the shading characteristics of the image reading unit.

An input masking unit 104 masks the output of the shading correction unit 103 to generate a sensor 1208.
The color space signal depending on the filter characteristic of is converted into, for example, the NTSC standard color space signal.

A scaling unit 105 scales the image signal in the main scanning direction especially when the image is enlarged. The scaling in the sub-scanning direction is performed by controlling the driving speed of the mirror units 1210 and 1211.

A LOG converter 106 converts the RGB image signal input from the scaling processor 105 into a CMY image signal.

Reference numeral 107 denotes a color space conversion unit which converts the CMY image signal input from the LOG conversion unit 106 into a lightness signal L and chromaticity signals a and b.
Convert to Here, the Lab signal is a signal represented in the CIE Lab color space, and is calculated by the following equation. Where αij, Xo, Yo, Zo: Constant A ^ B: A to the Bth power

Further, X, Y and Z are signals obtained from the RGB signals by the following equation. Where βij: constant

Note that the LOG converter 106 and the color space converter 107 may be combined into a single unit to directly generate a Lab image signal from an RGB image signal.

Reference numeral 108 denotes an encoding unit that encodes the L signal, which is the lightness information input from the color space conversion unit 107, in block units of 4 × 4 pixels, and the code is, for example, L_co of 43 bits.
De is output, the a and b signals that are the chromaticity information are encoded in block units of 4 × 4 pixels, and the code, for example, 21-bit ab_code is output.

Reference numeral 109 is a feature extraction circuit, which is an input masking unit 1
From the RGB image signal input from 04, it is determined whether the pixel of interest is a black pixel, and by determining whether the block of 4 × 4 pixels is the black pixel area, the pixel of interest becomes a character area. It is determined whether or not it is included, and if it is included, the black determination signal K_code is set to "1", and if not, the K_code is set to "0".

Reference numeral 110 denotes a memory unit, which is a code L_cod of lightness information.
e, the chromaticity information code ab_code and the black extraction signal K_code of the feature extraction result are stored. FIG. 3 is a block diagram showing a configuration example of the memory unit 110, and writing and reading to and from the memory 309 are controlled by the address controller 318 and the data controller 319, details of which will be described later.

The encoded image signal stored in the memory unit 110 is read by the four image forming units 119c, 119m, 119y and 119k in synchronization with the output of the printer unit to form an MCYK image signal. . The four image forming units 119c, 119m,
Since 119y and 119k have the same configuration, the C image forming unit 119c will be described below, and the other description will be omitted.

A decoding unit 111 decodes the lightness information L by the L_code read from the memory unit 110, and decodes the chromaticity information a and b by the ab_code.

A color space conversion unit 112 converts the decoded image signal in the Lab color space into an image signal in the CMY color space.

Reference numeral 113 denotes a masking / UCR unit, which is a color space conversion unit 1
Black K is extracted from the CMY image signal input from 12 according to the equation (3), masking calculation is performed by the set coefficient, and the C component signal is output. The masking operation is as shown in formula (4) or (5). However, when K_code read from the memory unit 110 is "0", that is, when the pixel of interest is not a black pixel, each of C, M, Y, and K is calculated. Predetermined coefficients for signals ai1, ai2, ai3, ai4
(4) is multiplied by, and K_code is `1 ',
That is, when the pixel of interest is a black pixel, the sum-product operation of equation (5) for multiplying each signal of C, M, Y, K by predetermined coefficients bi1, bi2, bi3, bi4 is performed. K = min (M, C, Y)… (3) Output = ai1 ・ M + ai2 ・ C + ai3 ・ Y + ai4 ・ K… (4) Output = bi1 ・ M + bi2 ・ C + bi3 ・ Y + bi4・ K… (5)

Reference numeral 118 denotes a filter processing determination unit, which is an amplitude ratio again, bg of the chromaticity information which gives details input from the decoding unit 111.
The filtering process of the image block is determined according to ain and the image determination signal Lflg, and a signal indicating the determination result is output.

Reference numeral 114 denotes a filter processing unit, which masks U according to the determination signal input from the filter processing determination unit 118.
The C component signal input from the CR unit 113 is spatially filtered to correct the image.

Reference numeral 115 denotes a scaling processing section, which is four image forming sections 119.
CMYK image signals input from c, 119m, 119y, and 119k are subjected to scaling processing, especially processing at the time of image reduction. The scaling unit
105 and 115 may be a single circuit. In that case, a control unit (not shown) controls the tristate gates provided at the input and output of the scaling processing unit to switch the flow of the image signal according to the scaling mode. You can do it.

Reference numeral 116 denotes a gamma correction unit that performs gamma correction on the CMYK image signal input from the scaling processing unit 115 according to the characteristics of an output device such as a printer.

Reference numeral 117 denotes an edge emphasizing unit which performs smoothing filter or edge emphasizing filter processing on the image signal output from the gamma correction unit 116 and outputs the image signal. The image signal output from the edge enhancement unit 117 is sent to an output device such as a printer to form an image.

[Encoding Unit] Next, the outline of the encoding of image data will be described. It should be noted that the image data is coded, for example, in a total of 16 pixels of 4 × 4 pixels as one block.

Encoding of Lightness Information The concept of lightness information encoding will be described with reference to FIGS. 4 and 5. Figure 4
Lightness information Xij cut out in the 4 × 4 pixel block shown in (a)
When (i, j = 1 to 4) is subjected to the 4 × 4 Hadamard transform shown in Expression (6), Yij (i, j = 1 to 4) shown in FIG. 4 (b) is obtained. The Hadamard transform is a type of orthogonal transform that expands 4 × 4 data with a two-dimensional Walsh function, and a signal in the time domain or space domain is transformed into the frequency domain or space frequency domain by the Fourier transform. Equivalent to. That is, the matrix Yij (i, j = 1 to 4) after Hadamard transform becomes a signal corresponding to each component of the spatial frequency of the matrix Xij (i, j = 1 to 4) of the input signal. Where H: 4 × 4 Hadamard matrix H ^ T: Transpose of H

Here, as in the case of the two-dimensional Fourier transform, the Hadamard transform result Yij (i, j = 1 to 4) becomes higher in the sub-scanning direction as the value of i (that is, the row position) becomes larger. The spatial frequency components are located and the value of j (ie the column position)
The larger is, the higher the spatial frequency component is arranged in the main scanning direction. Especially when i = j = 1, Yij = (1/4) ΣXi
Then, a signal corresponding to the DC component of the input data Xij (i, j = 1 to 4), that is, the average value (strictly, a signal having a value obtained by multiplying the average value by four) is output.

It is generally known that an image read by an image scanner has few high spatial frequency components due to the resolution of a reading sensor such as a CCD and the transmission characteristics of an optical system. Furthermore, the visibility of the human eye is also high.Using the low sensitivity of spatial frequency components, the signal Yij (i, j = 1 to 4) after Hadamard transform is scalar-quantized, and the result is shown in Fig. 4 (c). Zij (i, j = 1 to 4) shown in is obtained.

FIG. 5 (a) shows the number of bits of each element of the lightness information Xij (i, j = 1 to 4), and FIG. 5 (b) shows the Amadal transformation result Yij (i, j = 1).
4c), the figure (c) shows the number of bits of each element of the scalar quantization result Zij (i, j = 1 to 4). The component is quantized with the largest number of bits (8 bits) to Z11, and the component with higher spatial frequency is quantized with the smaller number of bits. Further, as shown in FIG. 4 (d), 16 elements of zij (i, j = 1 to 4) are grouped into a DC component and four AC components. That is, as shown in Table 1, the DC component Z11 is assigned to the signal AVE, the main scanning AC components Z12, Z13, and Z14 are assigned to the signal L1, and the sub-scanning AC components Z21 and Z31 are assigned to the signal L2. Assign Z41,
The main scanning and sub-scanning middle-range AC components Z22, Z23, Z32, Z33 are assigned to the signal M, and the signal H is grouped main scanning and sub-scanning high-pass components Z24, Z34, Z42, Z43, Z44
Assign

[0043]

【table 1】 Further, it is possible to change the code length and code each group depending on whether or not the pixel block is an edge portion in the image. For example, in the case of the edge part, Fig. 5 (d)
In the non-edge portion, the code length is coded as an example and the code length is coded as an example in FIG. That is, since the information of the AC component is important in the edge portion, a large code length is assigned to the AC component signals L1, L2, M, and H.

Coding of Chromaticity Information Human visual characteristics are more sensitive to lightness information than to chromaticity information. In general, L, a, and b all have an independent relationship, but the image signal read by the CCD has a correlation between the lightness information and the chromaticity information due to the characteristics of the optical system of the reading device. Considering this, the chromaticity information a and b can be quantized fairly coarsely and efficiently coded.

FIG. 6 is a diagram showing the concept of encoding chromaticity information.

FIG. 7A shows lightness information Lij in a 4 × 4 pixel block, and FIG. 9B shows chromaticity information in a 4 × 4 pixel block.
aij. Now, at the cut point of j = 3, that is, A-A ',
Considering the case where the data of L and a are transiting as shown in the same figure (c) or (d), the difference between the maximum value and the minimum value of the four data corresponding to the four pixels is ΔL, Δa, It is assumed that the average values of the four data are Lmean and amean, respectively. At this time, if L and a have a linear relationship, the following equation holds. Δa / ΔL = (ai3-amean) / (Li2-Lmean) ai3 = Δa / ΔL ・ (Li3-Lmean) + amean… (7)

Applying this relationship to the other pixels in the 4 × 4 pixel block gives equation (8). Δa / ΔL = (aij-amean) / (Lij-Lmean) aij = Δa / ΔL ・ (Lij-Lmean) + amean = again ・ (Lij-Lmean) + amean… (8)

Therefore, for the chromaticity information a, if the average value amean of the 4 × 4 pixel block and the amplitude ratio Δa / ΔL (= again) of the lightness information and the chromaticity information are encoded, the data of each pixel Can be restored. The same applies to the chromaticity information b.

Based on the above, amean and again (and bm
ean and bgain), but in order to reduce the number of bits, it is performed with a code length that differs depending on the characteristics of the image block.

With respect to an image having a high spatial frequency, the quantization error of chromaticity change has a large effect on the image quality, and the error of the chromaticity average value has a small effect. On the contrary, the quantization error of the chromaticity average value has a great influence on an image having a low spatial frequency, that is, a continuous tone part. Further, since the lightness and the chromaticity have a correlation as described above, the pixel block having a large lightness difference ΔL (edge portion) and the pixel block having a small lightness difference ΔL (flat portion) are divided and quantized. Then, amean and bmean are encoded into am and bm by linear scalar quantization, and again and gain are encoded into ag and bg by nonlinear scalar quantization, respectively. Table 2 shows the number of bits of each element. Note that Lflg in Table 2 is an image determination signal that becomes “1” when the lightness difference ΔL exceeds the threshold value and becomes “0” otherwise.

[0051]

[Table 2] By the encoding described above, for example, each color component 8
Bit image signal 4 × 4 pixels 384 bits, L_code 43
Bit and 21 bits of ab_code (including 1 bit of Lflg),
In other words, it can be compressed to 1/6 in total of 64 bits.

[Decoding Unit] Next, the outline of decoding the code read from the memory unit 110 will be described.

Decoding Lightness Information The lightness information may be decoded by reversing the procedure described in FIG. That is, the read L_code is inverse vector quantized and inverse scalar quantized to restore each frequency component of the Hadamard space. Further, if the inverse Hadamard transform is performed, the brightness information
L is restored. The inverse Hadamard transform is an inverse transform of the Hadamard transform shown in equation (6) and is defined by equation (9). Where H: 4 × 4 Hadamard matrix H ^ T: Transpose of H

On the other hand, the Hadamard transform and the inverse Hadamard transform are linear operations, and when the Hadamard transform or the inverse Hadamard transform of the matrix X is expressed as H (X), the equation (10) is generally used.
Holds. H (X1 + X2 +… + Xn) = H (X1) + H (X2) +… + H (Xn)… (10)

Utilizing this property, the inverse Hadamard transform is decomposed into each frequency band defined by the coding of the brightness information, and is performed in parallel. Here, the data matrix decoded from the code L1 is YL1, the data matrix decoded from the code L2 is YL2, the data matrix decoded from the code M is YM, and the data matrix decoded from the code H is YH.
If, then equation (11) holds. H (YL1 + YL2 + YM + YH) = H (YL1) + H (YL2) + H (YM) + H (YH)… (11)

Therefore, the brightness information dLij of each pixel of the block
Can be obtained by the equation (12) when the component of each pixel of H (X) is represented by Hij (X). dLij = Lmean + Hij (YL1) + Hij (Yn) + Hij (YH)… (12)

Decoding of Chromaticity Information Decoding of chromaticity information is performed by the formula (8).
Perform based on. Lmean and dLi decoded by the above procedure
Substituting j, the average value amean of the 4 × 4 pixel block decoded from the codes am, ag, and Lflg and the amplitude ratio again into the equation (8),
The chromaticity information daij of each pixel is obtained. Similarly, chromaticity information db
You can also get ij.

[Device Timing Chart] FIG. 7 is an example of a device timing chart of this embodiment.

In the figure, the signal START is a signal indicating the start of the document reading operation. The signal WPE represents a section in which the image scanner reads the original image, performs the encoding process, and writes in the memory. The signal ITOP is a signal indicating the start of the printing operation, and the signals MPE, CPE, YPE, KPE drive the magenta semiconductor laser 1216, cyan semiconductor laser 1215, yellow semiconductor laser 1214, and black semiconductor laser 1213 shown in FIG. 1, respectively. It is a section signal.

As shown in the figure, the signals CPE, YPE and KPE are
The signal MPE is delayed by time t1, t2, t3, respectively, and this is controlled by the following relation with respect to the distances d1, d2, d3 shown in FIG. t1 = d1 / v, t2 = d2 / v, t3 = d3 / v… (13)

The signal HSYNC is a main scanning synchronizing signal, and the signal CLK is a pixel synchronizing signal. The signal XPHS is the count value of the 2-bit main scanning counter, and the signal YPHS is the count value of the 2-bit sub-scanning counter, which is generated by the circuit configured by the inverter 1001 and the 2-bit counters 1002 and 1003 shown in FIG. .

The signal BLK is a synchronization signal in units of 4 × 4 pixel blocks and is processed in units of 4 × 4 blocks at the timing indicated by BDATA.

[Structure of Memory Unit] The memory unit 110 is composed of a memory 309, an address controller 318 and a data controller 319, as shown in FIG.

FIG. 9 is a block diagram showing a configuration example of the address controller 318. The address controller 318 includes a main scanning address generation unit (XCOUNTER) 423, a sub-scanning address generation unit (YCOUNTER) 424, and an address selection unit (ADR-SEL). ) 425 and the memory control signal generator (RC-CON) 426.

In this embodiment, for example, DRA is used as the memory 309.
Use M. DRAM access is performed using two addresses, a row (ROW) address and a column (COLUMN) address, strobe signals (RAS, CAS), and enable signals (W
Controlled by E). In the present embodiment, for example, an image of maximum 297 mm in the main scanning direction and maximum 432 mm in the sub scanning direction is set to 400 dpi.
It is possible to store in the memory unit 110 at the resolution of.
Therefore, the XCOUNTER 423 and YCOUNTER 424 are 13-bit address counters so that the memory space of that size can be accessed.

The main scanning section signals WLE and RLE input from the section signal generator (not shown) via the buffer 407 are D-
It is delayed by 2 clocks by F / F413 and input to XCOUNTER423. Similarly, the sub-scanning section signals WPE, MPE, CPE, YPE input via the buffer 406 are delayed by 2 clocks by the DF / F 412 and input to the YCOUNTER 424.
These section signals represent an effective image section when the level is “H”.

ADDEC 418 is a signal ADR, DATA, XCS, RD, WR, RS input from a CPU (not shown) via buffers 400 to 405.
According to T, each built-in register is read and written, and the data held in each register is output as signals WR0 to WR7F. The signal RST is a reset signal and is input to the clear terminal CR or the reset terminal XRST of each block.

In addition to the section signals described above, the XCOUNTER 423 sends the XPHS signal and the YPHS signal indicating the phases of the main scanning and the sub scanning via the buffer 408 and the DF / F 414, and ADDEC4.
Signals WR0, WR4, which set counters from 18 registers
WR6, WR8, WRA, WRC are input. And XCOUNTER423
Outputs the main scan write address (XAW) of the DRAM and the main scan read address (XAR) of the DRAM.

The signal HS input from the CPU (not shown) via the buffer 410 is delayed by 1 clock each in the DF / Fs 416 and 421, and the signal delayed by 1 clock and the signal inverted by 2 clocks and inverted. Is ANDed at gate 422. The signal HS output from the gate 422 is input to the HS0 terminal of the XCOUNTER 423 and the HSY terminal of the YCOUNTER 424.

Signal CLK input via buffer 411
Is supplied to the CLK terminal of each block and inverted by the inverter 417 to become the signal XCLK, which is the XC of RC-CON426.
Supplied to the LK pin.

Main Scan Address Generation Unit (XCOUNTER) FIG. 10 is a diagram showing a circuit configuration example of the XCOUNTER 423.

The main scanning phase signal XPHS is DF / F1100, 1101
Delayed by 2 clocks by 1108 and 1109 respectively, 16-input 1-output selector (C
Input to ENB-SEL) 1102 and 1110. CENB-SEL1102 and 1110
Selects each bit of the signals WR4 and WRA using the main scanning phase signal XPHS as a select signal. Therefore, the bit of the signals WR4 and WRA corresponding to the phase to be enabled is set to "L" and the bit of the phase to be disabled is set to "H".

The outputs D of CENB-SEL1102 and 1110 are 1 respectively.
3-bit up / down counter (UDCT) 1107 and 1116 ENB
Input to terminal. When the level of the output D is'L ', it is in the enable state and the UDCTs 1107 and 1116 perform counting operation. Conversely, when the level of the output D is “H”, it is in the disable state, and the UDCTs 1107 and 1116 hold the output.

The signals WR0 and WR6 are signals that determine the load values of the UDCTs 1107 and 1116, and by changing the set value, access can be started from any address of the DRAM. The loading of the UDCTs 1107 and 1116 is controlled by the LD signal generated as follows.

The JK-F / F 1104 inputs the bit 0 of the main scanning section signal LE to its J terminal and outputs the signal to the terminal K by the gate 1103.
Input the signal obtained by NORing bit 0 of LE and bit 0 of signal WRC. Gate 1106 has output Q of JK-F / F1104 and its output Q.
Is delayed by 1 clock by DF / F1105
The NANDed signal is output, and this signal becomes the LD signal of the UDCT1107. Therefore, the UDCT 1107 loads the load value at the moment when the section signal LE is enabled. Of UDCT1116
LD signal is also gate 1111, JK-F / F1113, DF / F1114, gate 1
Similarly generated by 115. However, the LD signal of the UDCT 1116 is generated from bit 1 of the signal LE and bit 2 of the signal WRC instead of bit 0 of the signal LE and bit 0 of the signal WRC.

The counting operation of UDCT 1107 and 1116 is as follows.
When the bit 1 and bit 3 of the signal WRC input to the UP terminal are'H ', the count is up, and when they are'L', the count is down.

In this way, the output D of UDCT 1107 and 1116
Are determined and input to the ADR-SEL 425 as the main scan write address XAW and the main scan read address XAR, respectively.

Sub-scanning Address Generator (YCOUNTER) FIG. 11 is a diagram showing a circuit configuration example of the YCOUNTER 424, for writing (W).
No. Y counter 502 and four counters 503, 504, 505, 506 for reading (R) of M, C, Y, K respectively.

The selectors (CENB-SEL) 500 and 501 are 16-input 1-output selectors for counter enable control, which are the same as the CENB-SELs 1102 and 1110 shown in FIG. CENB-SEL
Each of 1102 and 1110 selects each bit of the signals WR12 and WR26 by using the sub-scanning phase signal YPHS as a select signal. Therefore, the signals WR12 and WR2 corresponding to the phase you want to enable are
Set the 6th bit to'L 'and the phase bit you want to disable to'H'. The selection output of CENB-SEL500 is input to the enable terminal EN of the Y counter 502 and
-Selection output of SEL501 is input to enable terminal EN of Y counters 502-506.

FIG. 12 is a diagram showing a circuit configuration example of each of the five Y counters 502-506.

The signal input to the terminal PE is a sub-scanning section signal input to each counter, which is delayed by one clock by the DF / F100 and then input to the CLK terminal of the DF / F103 and the D terminal of the DF / F104. Is entered. When the output of DF / F100 changes from'L 'to'H', the D terminal of DF / F103 receives a signal whose internal state is inverted from its inverted output. Also, DF / F103
The output Q is input as a select signal to the two-input one-output selector 105.

The terminal WR0 is connected to the A input and the terminal WR1 is connected to the B input of the selector 105, and the selected signal is sent to the 13-bit up / down counter (UDCT) 107 as a load value. The load signal is a signal obtained by NANDing the inverted output of the DF / F104 and the output of the DF / F100 by the gate 106. With this configuration, the UDCT 107 outputs the output of the selector 105 at the moment when the sub-scanning section signal PE is enabled. To load.

Since the enable signal obtained by ORing the signal input to the terminal HS by the inverter 102 and the signal input to the terminal EN at the gate 108 is input to the UDCT 107, the UDCT 107 In one main scanning section synchronized with the signal HS generated from the main scanning synchronization signal,
Performs count operation according to the signal input to the terminal EN.

The UDCT 107 switches up / down operation according to the signal input to the terminal WR3, and when the signal is'L ', it counts up, and when it is'H', it counts down.

In this way, the Y counter 502 outputs the sub-scanning write address YAW0, and the Y counters 503 to 506 output the sub-scanning read addresses YAR1 to YAR4, respectively. These address signals are input to the ADR-SEL425.

As described above, the Y counters 502 to 506 switch two load values and start accessing the DRAM from the load values, that is, use the load value as the initial address value. In this embodiment, when performing normal operation, set the same load value to the terminals WR0 and WR1,
DRAM access is always started from the same address. However, this embodiment has a memory capable of storing two images of A4 size, so an A4 size document is copied one-to-one by an automatic document feeder such as an RF feeder (one document To obtain one copy output), set different values to pins WR0 and WR1. If there is only one WR input when copying an A4 size document one-to-one with the RF feeder, the image of the Nth document is stored in memory and then the printout of that image ends. Up to, the image of the (N + 1) th original cannot be written to the memory. However, if it has two WR inputs, the memory can be divided into two and used.

More specifically, for the Nth original, the value of WR0 is loaded into the UDCT 107, and the image is written in the memory using the loaded value as the start address. When the writing of the image corresponding to the Nth sheet is completed, the value of WR1 is changed to UDCT107.
The image corresponding to the (N + 1) th sheet is written to the memory with the value of WR1 as the start address. Since the memory space for storing the image corresponding to the N + 1th sheet and the memory space for storing the image corresponding to the Nth sheet do not overlap, writing of the image corresponding to the N + 1th sheet and N It is possible to read out the image corresponding to the first sheet at substantially the same time. Therefore, this embodiment can process a one-to-one copy using an RF feeder or the like at high speed.

Also, when performing double-sided copy of A4 size or smaller, the image on the first side of the document is written in the address space set by WR0, and the image on the second side is written in the address space set by WR1. As a result, double-sided copying can be processed at high speed as in the case of using a document feeder or the like.

Address Select Unit (ADR-SEL) FIG. 13 is a diagram showing a circuit configuration example of the ADR-SEL 425.

The C-SELs 608 to 611 respectively select eight four-input one-output first selectors to which the sub-scanning read addresses YAR1, YAR2, YAR3, and YAR4 are input, and eight first selector outputs. It consists of a second selector with eight inputs and one output. The selection signal of each of the first selectors of the C-SEL608 is each 2 bits of the signal WR28.
The selection signal of each of the first selectors is 2 for each of the signals WR2A
The selection signal of each bit and the first selector of the C-SEL610 is each 2 bits of the signal WR2C, and the selection signal of each of the first selector of the C-SEL611 is each 2 bits of the signal WR2E. The selection signal of the second selector is the inverters 602 to 605.
The signal which inverted bit 1 of the main scanning phase signal XPHS by
Further, the sub scanning phase signal YPHS is delayed by one clock by the DF / F601, and the total of 3 bits of bits 0 and 1 is provided.
Therefore, the C-SELs 608 to 611 output four sub-scanning read addresses in a time division manner according to the signals XPHS and YPHS.

The main / sub counter switching circuit (XY-SEL) 612 switches between the input main scanning write address XAW and the sub scanning writing address YAW0 by using bit 0 of the signal WR31 as a switching signal and outputs it. In addition, XY-SEL613 to 616 use the bit 1 of WR31 as a switching signal to input the main scan read address XAR and the sub-scan write address selected by C-SEL608, X-SEL, respectively.
AR and C-Sub-scan write address selected by SEL609, XAR and C
-Sub-scan write address selected by SEL610, XAR and C-SEL6
The sub-scanning write address selected in 11 is switched and output. FIG. 13 shows the relationship between the input / output of XY-SEL 612 to 616 and the selection signal. In this way, by switching the main and sub addresses, the image stored in the memory can be rotated and output.

Regarding the outputs X and Y of the XY-SEL612, X is the LSB side and Y is the MS.
On the B side, it becomes one bus data and is input to the A terminal side of the read / write switching selectors 617-620. Similarly, X
The outputs X and Y of the Y-SEL 613 to 616 become one bus data with X being the LSB side and Y being the MSB side, and are input to the B terminal side of the read / write switching selectors 617 to 620. These selectors 617
The selection signals of ˜620 are 1 bit of the signal WR30 selected by the eight-input one-output selector 607. The selection signal of the selector 607 is the sum of bit 0 and 1 of the signal obtained by inverting the bit 1 of the main scanning phase signal XPHS by the inverter 606 and the signal obtained by delaying the sub scanning phase signal YPHS by 1 clock by the DF / F601. It is 3 bits, and the output of the selector 607 is switched according to the phase of main scanning / sub scanning. Then, when the output of the selector 607 is "0", the selectors 617 to 6
20 selects the A input side, that is, the write address, and when it is '1', the B input side, that is, the read address.

The outputs of the selectors 617 to 620 are input to the terminals A0 to A3 of the address converter (Z-TRNS) 621. Z-TRANS621
Converts the input count value into a ROW address and a COLUMN address so as to match the DRAM address section. As described above, the space handled by the image processing apparatus of this embodiment is, for example, 297 mm × 432 mm, and the recording density is, for example, 400 d.
When it is set to pi, it becomes 4,677 pixels x 6,803 pixels. 2M x 8
In order to map to the bit DRAM just enough,
The address may be output as follows.

FIG. 14 is a diagram showing an example of the circuit configuration of the Z-TRANS 621. The count values input to the terminals A0 to A3 are input to the address conversion unit 1401 and 13 bits on the MSB side thereof are converted address generation unit 1404. 13 bits on the LSB side are input to the Y terminal of the
Address and Z2 address. The conversion address selector 1405 selects either the Z1 address or the Z2 address based on the value of X10 output from the S terminal of the conversion address generation unit 1404. Then, the selector 14 with two inputs and one output
06 is a row according to bit 0 of the main scanning phase signal XPHS.
Switch the address and column (COLUMN). In this example,
For example, since 2K refresh type DRAM is used, ROW
The address and the COLUMN address are separated into 11 bits and 10 bits as shown in FIG.

The four address signals Z0 to Z3 output from the Z-TRANS621 are delayed by 3 clocks by the shift registers 622 to 625, respectively, and are delayed as A as address signals A0 to A3.
This address signal MAA, MAB, MA output from DR-SEL425
C and MAD are sent to the memory 309 via the output buffers 429 to 432 shown in FIG.

Memory Control Signal Generation Unit (RC-CON) FIG. 16 is a diagram showing an example of the circuit configuration of the RC-CON 426, in which the WE, RAS, and CAS signals necessary for accessing the DRAM and the I of the data controller 319 are shown. Generates the DIR signal that controls the / O port. The five RCSELs shown in the figure are blocks that generate signals that are the basis of control signals, and FIG. 17 is a diagram showing a detailed configuration of the RCSELA 1203.

In FIG. 17, the gate 1300 has a terminal LERC0.
Bit 0 of the main scan write section signal LE input to
The bit 0 of the sub-scanning write section signal PE input to ERC0 is set to N
AND Similarly, the gates 1301 to 1304 respectively NAND the bit 1 of the signal LE and any one of the bits 1 to 4 of the signal PE.
I do. The output of these gates 1301-1304 and the terminal WR
Signal E, which is the OR of the signal WR4B input to 1 at gate 1309
N generates RAS and CAS signals via terminal ENout
Input to enable terminal ENin of RCSELB1204-1207.
The signal EN is in the enable state in both the main scanning and sub-scanning enable areas, that is, in the effective image area. When the signal WR4B is '1', the signal EN is forcibly disabled.

The signal that is the basis of the RAS / CAS signal is bit 0 of the main scanning phase signal XPHS input to the terminal XP, and the signal is the D signal.
-Signal RCS delayed by one clock with F / F1308 (Signal RAS and CAS
Signal that is the source of the
Input to terminal RCSin of ~ 1307.

Further, the eight-input one-output selector 1306 selects each bit of the signal WR0 input to the terminals D0 to D7 by using the bit 1 and 2-bit signal YPHS of the signal XPHS as a selection signal. Therefore, by setting the value of signal WR0 arbitrarily,
It becomes possible to control the output WE of the selector 1306 in a time division manner. The signal WE (the signal that is the source of signals WE and DIR) is DRAM
As a signal to generate the write enable of
It is input to the terminal WEin of RCSELB1204-1207 via WEout.

Furthermore, this RCSELA 1203 is also configured to generate a signal for controlling the refresh cycle of DRAM and to realize CAS-before-RAS refresh. The signal YPHS and the signal LE input to the terminal YP are transferred through a four-input OR gate 1307 to a shift register (SHIFT-R) 130.
Input to D terminal of 7. Thus, the signals YPHS and LE
By taking the OR, the refresh cycle is executed once in every 4 sub-scanning lines in the disenable section.

Further, the gate 1310 ORs the delay output QA for 1 clock of the SHIFT-R 1307 and the delay output QG for 7 clocks.
The output signal RFC is output from the terminal RFCout, and the delayed output QB for 2 clocks and the delayed output QH for 8 clocks are output by the gate 1311.
After R, the signal RER which is ORed with the inverted output of DF / F1308 by the gate 1312 is output from the terminal RERout. These signals RFC (the signal that becomes the basis of the CAS signal at the time of refresh) and signal RFR (the signal that becomes the source of the RAS signal at the time of refresh) are used as the refresh cycle control signals at terminals RF of RCSELB1204 to 1207.
Input to Cin and RERin respectively. By delaying the signal RFR by one clock from the signal RFC, the CAS signal first becomes'L 'level during the refresh cycle and DF /
By taking the OR with the inverted output of F1308, the toggle operation is realized by the signal RFR synchronized with the phase signal, and the DRAM refresh operation is performed.

In FIG. 16, the main scanning phase signal XPHS and the sub scanning phase signal YPHS are converted into 8-bit phase signals by the decoders 1200 and 1201 and the inverter 1202, and RCSELB1.
Input to terminals PHSEL of 204 to 1207. This signal becomes "0" when the phase indicated by the bit is reached, and becomes "1" at other phases.

The original signal of each control signal output from RCSELA 1203 is converted into an actual control signal by RCSELB 1204-1207. Figure 18 shows an example of the RCSELB circuit configuration.
SEL and EN are signals WR0 to WR3 output from ADDEC418.
At the same time, it is input to the RAS / CAS selector (RCSEL0) 1000.

FIG. 19 is a diagram showing an example of the circuit configuration of RCSEL0 (1000). It has eight five-input one-output selectors 700-707 and three-input selectors.
It is composed of OR gates 708 to 715 and an eight-input NAND gate 716. Selectors 700-707 have bit 0 of signals WR0-3
~ 2 or bits 4 to 6 to select and output any of the bits of the signal EN input from the RCSELA1203. Since each of the gates 708 to 715 ORs one of the outputs of the selectors 700 to 707 and the bit 3 or 7 of the signal WR0, when the bit is "1", the output of the gates 708 to 715 is "H". 'Fixed to level. If this signal is fixed to'H 'level, the final output RAS / CAS signal does not change and access to DRAM can be forcibly stopped.

Further, the gates 708 to 715 have a signal PHSEL.
Any of the 8 bits of are input. Since each bit of the signal PHSEL goes to the'L 'level only in a certain phase, the signals output from the selectors 700 to 707 are utilized when the PHSEL signal has different phases. Then, the eight signals output from the respective gates 708 to 715 are integrated by the NAND gate 716 and output from the terminal D to control the DIR, WE, RAS / CAS signals of all phases.

In FIG. 18, the signal output from the terminal D of RCSEL0 (1000) is delayed by 5 clocks by the shift register (SHIFT-R) 1001, inverted by the inverter 1003, and then transferred to the terminal RCSin by the gate 1005. With the input signal RCS
ORed and input to DF / F1012. With this, SHIFT
-The signal delayed by 5 clocks by R1001 is NANDed with the signal RCS by the gate 1004. On the other hand, the signal WE input to the terminal WEin is delayed by 5 clocks by the shift register (SHIFT-R) 1002, ORed with the output of the gate 1004 by the gate 1006, and then input to the DF / F 1013, 1014. .

The DF / Fs 1012 to 1014 have a preset terminal PR and a reset terminal CR to which any of the signals obtained by inverting the bits 5 to 0 of the signal WR4 by the inverter 1009 is input. Therefore, the CPU controls the signal WR4
DF / F1012-1014 can be preset or reset arbitrarily.

Also, the gates 1007 and 1008 OR the output of the gate 1004 and the bits 6 and 7 of the signal WR4. Therefore, the CPU controls gate 1007 by controlling signal WR4.
And the output of 1008 can be fixed to'H 'level arbitrarily. The outputs of gates 1007 and 1008 are AND gates 1010 and 101.
By 1, the refresh signals RER and RFC are switched, and DF /
Sent to terminal D on F1015 and 1016 ,. The DF / F 1015 inputs the signal of the terminal D in synchronization with the clock XCLK (inverted signal of CLK) and sends it as a 2-bit signal RAS to the delay line (DELAY) 427 shown in FIG. Further, the DF / F 1016 inputs the signal of the terminal D in synchronization with the clock CLK and sends it as a 2-bit signal CAS to the delay line (DELAY) 428 shown in FIG.

Each signal of RAS, CAS, WE generated by RC-CON426 is sent to memory 309 shown in FIG. 3 as memory control signal MRS.MCS, WE via DELAY427,428 and output buffers 433-435. To be The DELAYs 427 and 428 adjust the timing so that the data can be properly accessed according to the characteristics of the memory to be controlled.
Further, the DIR signal is sent to the data controller 319 via the output buffer 436.

In this way, the address controller 31
Data controller according to addresses MAA, MAB, MAC, MAD and memory control signals MRS, MCS, WE, DIR output from 8
Image data is transferred between the 319 and the memory 309. The data controller 319 performs switching control of writing and reading of data, order control of data access for performing edit processing such as image data redundancy processing and image rotation necessary for decoding. And the data controller 31
The sign L_cod of the brightness information read from the memory 309 by 9
e, the code ab_code of the chromaticity information and the black determination signal K_code of the feature extraction result are sent to the decoding unit 111.

As described above, according to this embodiment, it is possible to set a plurality of load values to be given to the counter of the address controller, and the load value is switched by the enable signal or the designation from the CPU. Can be divided into a plurality of areas and accessed.

Therefore, according to this embodiment, for example, after the image data of the Nth original is stored in the image memory, the load value is switched to the address for the N + 1th original, so that N + 1
While storing the image data of the first document in the image memory,
Since the Nth image data stored in the image memory can be read, the copying speed can be improved when the automatic document feeder is used. Also, when performing double-sided copying, the image can be written in the address space set by WR0 on the first side and the image can be written in the address set by WR2 on the second side. The copying speed can be improved as in the case of using it.

[0113]

Second Embodiment An image processing apparatus according to the second embodiment of the present invention will be described below. Note that, in the second example, the configurations substantially the same as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

The present invention, like the first embodiment described above,
In addition to toggling the load value given to the counter of the address controller by an enable signal,
As in the second embodiment described below, the address space can be arbitrarily fixed by a signal from the CPU, and switching to the toggle operation can be performed.

FIG. 20 shows the address controller 3 of the second embodiment.
FIG. 21 is a diagram showing an example of a circuit configuration of 18, and FIG. 21 is a YCOUNTER4 of the second embodiment.
FIG. 22 is a diagram showing a circuit configuration example of 24, and FIG. 22 is a diagram showing a circuit configuration example of each of the five Y counters 502 to 506 of the second embodiment.

As shown in these drawings, the address controller 318 is different from that of the first embodiment shown in FIG. 9 in that the signal WR14 from the register is inputted to the YCOUNTER 424, and is different from that shown in FIG. It differs from the first embodiment in that a predetermined bit of the signal WR14 is input to the Y counters 502-506. Further, in the first embodiment, as shown in FIG. 12, the switching control of the load values input to the terminals WR1 and WR2 is controlled by the DF / F103 synchronized with the sub-scanning section signal PE. In the embodiment, as shown in FIG. 22, an F / F having preset PR and clear CR inputs is used for the DF / F 103. The operation due to this difference in configuration will be described below.

A signal input to the terminal WR2 (CPU (not shown)
Bit of signal WR14) set by
0 and bit 1 are NANDed by gate 1702, gate 1704
Is ANDed with the signal XRST, and then input to the PR terminal of the DF / F103. Also, bit 1 of the signal is the inverter 1701.
Is inverted by the gate 1703, and bits 0 and N
After being ANDed, it is input to the CR pin of DF / F103.

Therefore, when bit 0 of the signal is "0",
Regardless of bit 1, when the DF / F100 output changes from'L 'to'H', the inverted signal of the internal state is input to the D terminal of DF / F103. The operation is similar to that of the first embodiment. On the other hand, bit 0 of the signal is '1'
In case of, the Q output of DF / F103 becomes'L 'when bit 1 is' 0 ', and the Q output becomes'H' when it is '1'. This D-
The Q output of the F / F 103 is input to the select signal terminal of the selector 105, and the selector 105 selects the load value input to the terminal A of the selector 105 when the Q output is "0", and the value of "1" In this case, select the load value input to the B terminal.

As described above, according to the present embodiment, by controlling the signal WR14 from the CPU, the address space of the memory can be fixed to an arbitrary area, or can be switched to the toggle operation. Therefore, when a paper jam occurs during double-sided copying, two address spaces can be selected by controlling the signal WR14, so images can be read from either address space and stored in the memory. Efficient jam recovery can be provided without wasting the data once stored.

In each of the above-described embodiments, an example in which two load values (address initial values) are set has been described. However, the load value is not limited to two and may be three or more. It goes without saying that it is good.

[0121]

Other Embodiments Even when the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a printer, a reader, etc.), an apparatus including one device (for example, a copying machine). , Facsimile machines, etc.).

Further, the present invention is achieved by supplying a storage medium recording a software program for achieving the present invention to a system or apparatus, and reading out and executing the program stored in the storage medium by the system or apparatus. It goes without saying that it can be applied to cases where As a storage medium for supplying the program, for example, a floppy disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a non-volatile memory card, a ROM or the like can be used.

[0123]

As described above, according to the present invention,
It is possible to provide an image processing apparatus in which the image memory is divided into a plurality of areas and the access to each area can be easily switched, and a control method thereof.

[Brief description of drawings]

FIG. 1 is a schematic view showing a configuration example of an image processing apparatus according to an embodiment of the present invention,

2A is a block diagram showing a configuration example of an image processing unit shown in FIG.

2B is a block diagram showing a configuration example of the image processing unit shown in FIG.

FIG. 3 is a block diagram showing a configuration example of a memory unit shown in FIG. 2B.

FIG. 4 is a diagram for explaining the concept of brightness information encoding;

FIG. 5 is a diagram for explaining the concept of brightness information encoding;

FIG. 6 is a diagram showing a concept of encoding chromaticity information,

FIG. 7 is an example of a device timing chart of the present embodiment,

FIG. 8 is a diagram showing a circuit that generates phase signals XPHS and YPHS for main scanning and sub scanning.

9 is a block diagram showing a configuration example of the address controller shown in FIG.

10 is a diagram showing a circuit configuration example of the XCOUNTER shown in FIG. 9,

11 is a diagram showing a circuit configuration example of the YCOUNTER shown in FIG. 9,

12 is a diagram showing a circuit configuration example of each of the five Y counters shown in FIG.

13 is a diagram showing a circuit configuration example of the ADR-SEL shown in FIG. 9,

14 is a diagram showing a circuit configuration example of the Z-TRANS shown in FIG.

15 is a diagram showing a bit configuration example of an address signal generated by the Z-TRANS shown in FIG.

16 is a diagram showing a circuit configuration example of the RC-CON shown in FIG. 9,

FIG. 17 is a diagram showing a detailed configuration of RCSELA shown in FIG. 16;

FIG. 18 is a diagram showing a circuit configuration example of RCSELB shown in FIG. 16;

19 is a diagram showing a circuit configuration example of RCSEL0 shown in FIG.

FIG. 20 is a diagram showing a circuit configuration example of an address controller according to a second embodiment of the present invention;

FIG. 21 is a diagram showing a circuit configuration example of YCOUNTER shown in FIG. 20;

22 is a diagram showing a circuit configuration example of each of the five Y counters shown in FIG. 21. FIG.

[Explanation of symbols]

 101 Sensor 1208 CCD 102 Analog processing unit 103 Shading correction unit 104 Input masking unit 105 Magnification processing unit 106 LOG conversion unit 107 Color space conversion unit 108 Encoding unit 109 Feature extraction circuit 110 Memory unit 111 Decoding unit 112 Color space conversion unit 113 Masking / UCR unit 118 Filter processing determination unit 114 Filter processing unit 115 Magnification processing unit 116 Gamma correction unit 117 Edge enhancement unit 309 Memory 318 Address controller 319 Data controller

Claims (8)

[Claims] 1. A first generation means for generating an address signal representing a storage area of a storage means, a second generation means for generating a control signal for storing image data in the storage means, and the first generation means. And first control means for controlling the second generation means, and based on the address signal and the control signal, to store the input image data in the storage means, the image data stored in the storage means And a second control means for reading the set address initial value, the first control means sets a plurality of different address initial values in the first generating means, and sets the address initial value based on a predetermined signal. An image processing device characterized by switching between. 2. A reading means for reading a document image, a first generating means for generating an address signal representing a storage area of the storage means, and a second generating means for generating a control signal for storing image data in the storage means. Generating means, first control means for controlling the first and second generating means, and image data output from the reading means is stored in the storage means based on the address signal and the control signal. And a second control means for reading the image data stored in the storage means, and a forming means for forming an image based on the image data read from the storage means, the first control means An image processing apparatus, wherein a plurality of different address initial values are set in the first generating means, and the set address initial values are switched based on a predetermined signal. 3. The image processing apparatus according to claim 2, wherein the reading unit includes an automatic document feeding mechanism for continuously reading images from a plurality of originals. 4. The image processing apparatus according to claim 1, wherein the first control unit switches the address initial value based on a sub-scanning image area signal. . 5. The first control means, based on a sub-scanning image area signal or a signal input from the device control unit,
The initial value of the address is changed over.
The image processing device according to any one of claims 1 to 3. 6. The method according to claim 1, wherein the first control unit manages the storage unit by dividing the storage unit into a plurality of areas by switching the address initial value. The image processing device described in. 7. The apparatus further comprises an encoding means for encoding the image data stored in the storage means, and a decoding means for decoding the image data from the encoded data read from the storage means. The image processing device according to claim 1. 8. A setting step for setting a plurality of different initial address values in a first generating means for generating an address signal representing a storage area of the storage means, and an address initializing step set in the first generating means. A switching step of switching a value based on a predetermined signal, and input image data based on the address signal and a control signal generated by the second generating means for storing image data in the storage means. And a read step of reading the image data stored in the storage means on the basis of the address signal and the control signal. .