JPH11205582A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly and also accurately form a rear cover (closed) part with optimum width about an image processor which reads full color image information, performs image processing and outputs it. SOLUTION: A section signal generating part 230 produces plural valid image section signals based on a signal from a printer. Image memory 217 temporarily holds an image signal. An address controller 218 and a data controller 219 store the image signal in the memory 217 based on the valid image section signal and also control that the stored image signal is uncontinuously read in 1st and 2nd image sections which are mutually separated. The width of margin is optimally set in accordance the number of recording media that are used by a printer by optionally setting the length of uncontinuous image sections under the control of a CPU 240.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for reading full-color image information, performing image processing, and outputting the processed image.

[0002]

2. Description of the Related Art Conventionally, full-color image information is read from an image input device, image processing is performed on the full-color image information, temporarily stored in an image memory, and the stored full-color image information is read from this image memory and output to an output device. 2. Description of the Related Art An image processing device for outputting is known.

For example, an image which reads full-color image information from an image input device, performs image processing on the full-color image information, temporarily stores it in an image memory, reads out the stored full-color image information from this image memory, and outputs it to an output device. In the processing apparatus, an address controller for storing image data in an image memory stores a first image start address and a second image start address, two counter load value setting registers, and a main scan or sub scan section signal in a first signal. By processing so as to generate two valid sections, a valid section and a second valid section, the image stored in the image memory is output separately from the front and back sides, and the spine is automatically added to the output image. An image processing apparatus having a mode for forming a (closed) portion has been proposed.

[0004]

However, in the above-described conventional apparatus, in the spine (closed) mode, the width of the spine area is uniquely determined by the apparatus. The cover part may be small or large, and the spine section cannot be set so as to correspond to an arbitrary spine width specified by the operator.

Accordingly, the present invention has been made in view of the above points, and has as its object to provide an image processing apparatus capable of variably setting the spine width according to the recording paper to be used.

[0006]

In order to achieve the above object, in the apparatus according to the first aspect of the present invention, an image to be recorded is scanned and optically formed, and an image is formed according to the scanned image. Image signal generating means for generating an image signal, an image memory for temporarily holding the image signal, and a first image section storing the image signal in the image memory and separating the stored image signal from each other. And control means for controlling to read discontinuously in the second image section, image signal output means for performing predetermined signal processing on the read image signal having the discontinuous image section, and outputting to the output device, Section signal generating means for generating a plurality of effective image section signals based on a signal from the output device, wherein the control means stores and reads the image signal based on the effective image section signal. An image processing device that outputs an image signal having a margin between the first image section and the second image section to the output device, wherein the length of the discontinuous image section is arbitrary. And a margin setting unit that optimally sets the width of the margin in accordance with the amount of the recording medium used in the output device.

Here, in the apparatus according to the second aspect of the present invention, the margin setting means stores a value input by a user, and determines the length of the discontinuous image section in accordance with the input value. Can also be set.

In the apparatus according to the third aspect of the present invention, the margin setting means stores the number of recording media used by the user for the output device and stores the number of recording media according to the value of the recording medium. The length of a continuous image section can be automatically set.

In the apparatus according to the present invention, there is provided a storage means for storing in advance the width of the margin necessary for each type of recording medium in accordance with the thickness thereof, and Storing the number and type of recording medium used for the output device input by a user, and setting the number of the recording medium and the width of the margin of the type stored in the storage unit in the discontinuous image section. The length can also be set automatically.

Here, in the apparatus according to the present invention, the margin setting means controls a memory address in the scanning direction and a memory address in another direction substantially orthogonal to the scanning direction. A memory address control unit including a read address control unit and a read address assignment unit for assigning a read address according to the length of the set discontinuous image section to the plurality of read address control units may be provided.

Here, in the apparatus according to the present invention, the plurality of read address control means can control the read address in the scanning direction according to the width of the margin.

Here, in the apparatus of the present invention described in claim 7, the plurality of read address control means can control the read address in the other direction according to the width of the margin.

Here, in the apparatus according to the present invention, the image to be recorded can be scanned in two scans.

Here, in the apparatus according to the present invention, the image to be recorded can be scanned by one scan.

Here, in the apparatus according to the present invention, the image signal generating means converts the image signal to m × n.
The image signal output unit may include a unit that divides and encodes each pixel block (m and n are natural numbers), and the image signal output unit includes a unit that decodes the encoded block read from the image memory.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) [Outline of Image Processing Apparatus] FIG. 1 is an external view of a first embodiment of an image processing apparatus according to the present invention.

Reference numeral 101 denotes a document table glass on which a document 102 to be read is placed. The original 102 has the illumination 1
03, the reflected light is reflected by the mirrors 104 and 10.
After passing through steps 5 and 106, an image is formed on an image reading unit 108 having a CCD by an optical system 107. In addition, mirror 1
04, the mirror unit 110 including the illumination 103 is mechanically driven at a speed V by a motor 109,
The mirror unit 111 including 5, 106 also has a speed of 1
/ 2V, and the entire surface of the document 102 is scanned. Hereinafter, the direction in which both mirror units are driven is referred to as the sub-scanning direction (or line direction), and the direction substantially orthogonal to the driving direction is referred to as the main scanning direction (or pixel direction).

Reference numeral 112 denotes an image processing circuit which performs various kinds of processing on the image information read by the image reading unit 108 as an electric signal and outputs it as a print signal. 11
Reference numerals 3 to 116 denote semiconductor lasers for the respective colors (Bk, Y, C, M), which are driven by a print signal output from the image processing circuit unit 112.

The laser beams emitted by the respective semiconductor lasers are separated by a predetermined distance by polygon mirrors 117 to 120, respectively.
The respective latent images are formed on 25 to 128. 121,
122, 123 and 124 are black (B
k), yellow (Y), cyan (C), magenta (M)
Is a developing device for developing a latent image into a visible image by using the above toner, and the developed toner of each color is transferred to a sheet to print out a full-color image.

Sheets fed from one of the sheet cassettes 129 to 131 for feeding sheets of different sizes and the manual feed tray 132 are attracted onto the transfer belt 134 via the registration rollers 133, and are transferred onto a predetermined transport path. At a predetermined speed. The toner of each color is developed in advance on each of the photosensitive drums 125 to 128 in synchronization with the conveyance of the sheet, and the toner is transferred onto the sheet by the conveyance.

The paper on which the toner of each color is transferred is separated / separated.
After being conveyed and the toner is fixed on the sheet by the fixing device 135, the sheet is discharged to a sheet discharge tray 136.

[Configuration of Image Processing Unit] FIGS. 2 and 3 are block diagrams for explaining in detail the flow of image signals from the image reading unit 108 to the image processing unit 112 in FIG.

Reference numeral 200 denotes a CCD having red (R), green (G), and blue (B) color filters, respectively.
The output of each CCD is amplified by an analog amplifier in an A / D & S / H unit 201, and converted into a digital signal by an A / D converter. The R and G signals are each delayed by a delay memory, and are output after the spatial displacement of the three CCDs is corrected.

An output signal from the A / D & S / H unit 201 is subjected to shading correction by a shading correction unit 202, and further converted into an NTSC RGB signal by an input masking unit 203.

Reference numeral 204 denotes a scaling unit 1 for scaling an image signal in the main scanning direction, especially during enlarged copying. The magnification is changed in the sub-scanning direction by controlling the driving speed V of the mirror unit 110.

The image signal that has passed through the scaling unit 1 at 204 is
The LOG conversion unit 205 converts the primary color RGB signal into the complementary color C
It is converted to MY signal.

Reference numeral 206 denotes a color space conversion unit which converts a CMY signal into a lightness signal L and chromaticity signals a and b. Here, the L, a, and b signals are signals representing chromaticity components defined as L, a, and b spaces as international standards in the CIE, and the L, a, and b signals are calculated by the following equations.

[0029]

(Equation 1)

Here, α _ij , X0, Y0, and Z0 are constants.

Here, X, Y, and Z are signals generated by the R, G, and B signals, and are represented by the following equations.

[0032]

(Equation 2)

Here, β _ij is a constant.

An encoder 207 encodes an L signal as brightness information in units of 4 × 4 pixel blocks, and outputs the code L_code. Further, the a and b signals of the chromaticity information are encoded in units of 4 × 4 pixel blocks, and the code a
Output b_code.

On the other hand, a feature extraction unit 208 includes a black pixel detection circuit 208a and a character area detection circuit 208b, and outputs a black determination signal K_code to determine whether the pixel of interest is a black signal. That is, the black pixel detection circuit 20
8a, it is determined whether or not the inside of the 4 × 4 pixel block is a black pixel area.
b, it is determined whether or not the pixel area is a character area. If the pixel area is a character area, the K_code signal is set to “1”.
And "0" otherwise.

Reference numeral 217 denotes an image memory, which is an L_code signal which is a code of brightness information, and ab which is a code of chromaticity information
_Code signal and a K_code signal, which is the sign of the result of the determination output by the feature extraction unit 208, are stored. Writing and reading of these codes to and from the image memory 217 are performed by the address controller 218 and the data controller 219.
Is controlled by

A data processing unit 220 performs predetermined data processing on brightness information, chromaticity information, and a black determination signal from the data controller 219. This processing will be described later with reference to FIG.

Reference numeral 225 denotes a scaling unit 2, which scales the image signal in the main scanning direction, especially during reduction copying. Zooming in the sub-scanning direction is performed by controlling the driving speed V of the mirror unit 110. Magnification processing unit 1 of 204 and 225
And 2 may use the same circuit. In this case, a gate output by the CPU 240 in the variable power mode is controlled by using a tri-state gate circuit.

Reference numeral 226 denotes a gamma correction unit which corrects each color data of C, M, Y, and K according to the characteristics of the output device.
Then, a smoothing filter or an edge enhancement filter is applied to the C, M, Y, and K data by the edge enhancement unit 227, and the data is output to a printer device as output image data.

The section signal generator 230 generates the main scanning section signals WLE and RLE and the sub-scanning section signal WPE, and generates the sub-scanning section signal M transmitted from the printer.
Section signals MPE1, CPE1, YPE1, and KPE obtained by separating PE, CPE, YPE, and KPE into two image sections
1 and output. The output of each image processing unit shown in FIGS. 2 and 3 is controlled by these section signals.

FIG. 3 is a detailed block diagram of the data processing section 220.

211a (similarly, 211b, 211b)
c, 211d) is a decoder that decodes the lightness information L signal using the L_code signal read from the image memory 217, and decodes the chromaticity information a signal and b signal using ab_code.

212a (similarly, 212b, 212
c, 212d) denotes a color space conversion unit which converts the decoded L, a, b signals into magenta (M),
It is converted into cyan (C), yellow (Y), and black (Bk) components.

213a (similarly, 213b, 213
c, 213d) is a masking / UCR unit. UCR
In the part, by the black extraction circuit,

[0045]

Bk = mh (M, C, Y) The black signal Bk is generated based on the following equation (3). Further, in the masking section, when the black determination signal is "0", that is, when the pixel is not a black signal, each signal of C, M, Y, and Bk is multiplied by predetermined coefficients a1, a2, a3, and a4.
The calculation shown in equation (4) is performed.

[0046]

(Output C, M, YorBk) = a1M + a2C + a3Y + a4Bk (4) When the black determination signal is “1”, that is, when the pixel is a black signal, the signals C, M, Y, and Bk are output. The multiplication by different predetermined coefficients b1, b2, b3, and b4 is performed, and the calculation shown in equation (5) is performed.

[0047]

(Output C, M, YorBk) = b1M + b2C + b3Y + b4Bk (5) 214a (Similarly, 214b, 214c, 214d)
Is a filter processing determination unit, which turns on the filtering processing of the image block by the encoded image code.
/ OFF is determined, and an ON / OFF determination signal is sent to each filter processing unit described later.

215a (similarly, 215b, 215
c, 215d) is a filter processing unit,
With respect to the decoded L, a, and b signals, the determination result (ON / ON) of the filter processing determination unit 214 (214a to 214d)
The image is corrected by selectively applying a spatial filter according to the OFF determination signal). Note that each of the decoders 211a to 2112
d constitutes a decoding unit, and each filtering unit 215a
To 215d constitute a spatial filter unit.

[Apparatus Timing Chart] FIGS. 4 and 5 are timing charts in the present embodiment.

In FIG. 4, the START signal in FIG.
This signal indicates the start of a document reading operation according to the present embodiment. The (B) WPE signal is a signal indicating a section in which an image scanner having a CCD reads a document, performs an encoding process, and performs a memory write. The ITOP signal in (C) is a signal indicating the start of the printing operation, and the ITOP signal in (D)
The PE signal is a signal indicating a driving section of the magenta semiconductor laser 116 (see FIG. 1). The (C) signal of (E) is a signal indicating the driving section of the cyan semiconductor laser 115 (see FIG. 1), the (Y) signal of (F) is a signal indicating the driving section of the yellow semiconductor laser 114 (see FIG. 1),
The BPE signal of (G) is a signal indicating a driving section of the black semiconductor laser 113 (see FIG. 1).

As shown in FIG. 4, the CPE signal, the YPE signal, and the BPE signal correspond to t ₁ , t
₂ and t ₃ , which correspond to the distances d ₁ , d ₂ and d ₃ between the photosensitive drums 125 to 128 in FIG.
₁ = d ₁ / v, t ₂ = d ₂ / v, t ₃ = d ₃ / v (where v is the paper transport speed on the transport path in FIG. 1). Also, the HSYNC of (H)
The signal is a main scanning synchronization signal for synchronizing the main scanning.

FIG. 5 is a timing chart showing the main scanning section in this embodiment in detail by enlarging the time axis.

In FIG. 5, (A) and (C) correspond to FIG.
Are the same as the HSYNC signal of FIG. The clock signal (CLK) in (D) is a pixel synchronization signal for synchronizing the recording pixels. The YPHS signal in (B) is a count value of a 2-bit sub-scanning counter,
The XPHS signal in (E) is a count value of a 2-bit main scanning counter.

The WLE signal and the RLE signal are 1H, respectively.
This is a main scanning section signal representing an effective image section in which an image signal is input from the image scanner in the SYNC signal section.

The PHS signals shown in FIGS. 5B and 5E are supplied to the START signal (FIG. 4) by the circuit composed of the inverter 601 and the bit counters 602 and 603 shown in FIG.
(A)), the HSYNC signal and the CLK signal.

The BLK signal in FIG. 5F is a synchronization signal in units of 4 × 4 pixel blocks, and the output BDATA of the pixel block synchronized with the “H” section of the BLK signal (FIG. 5G).
Are output as valid data redundantly for four pixels.

[Configuration of Image Memory Unit] In FIG. 2, the image memory unit 210 includes an image memory 217, an address controller 218, and a data controller 219.

FIGS. 7 to 9 show the address controller 21.
FIG. 8 is a block diagram showing an internal configuration of FIG. The address controller 218 generally includes a main scanning address generator (X
COUNTER) 723 and a sub-scanning address generator (Y
COUNTER) 724 and an address select section (AD
R SEL) 725 and a memory control signal generator (RCC)
ON) 726.

The image memory 217 in the present embodiment
For example, a DRAM can be used. DR
AM access is performed by two addresses of a ROW address and a COLUMN address and a strobe signal (R
AS, CAS) and an enable signal (WE). The image processing apparatus according to the present embodiment
At a resolution of 00 dpi, an image having a maximum of 297 mm in the main scanning direction and a maximum of 432 mm in the sub-scanning direction can be stored in the image memory 217. Therefore, the address generators 723 and 724 in both scanning directions are 13-bit address counters (hereinafter also referred to as a main scanning counter and a sub-scanning counter) so as to access a memory space of that size.

In FIG. 7, the main scanning section signals WLE and RLE input from the section signal generating section 230 (FIG. 2) through the buffer 707 are delayed by one clock (CK) by the F / F 713. The delayed signal is input to the main scanning address generator 723 in FIG. Similarly, the sub-scanning section signals WPE and MP input from the buffer 706 are input.
Each signal of E, CPE, YPE is 1 by F / F712.
Delay by clock. The delayed signal is input to the sub-scanning address generator 724 in FIG. When each of these section signals LE and PE is “H”, it indicates that the section is an effective image section.

In FIG. 7, ADDEC 718 is a CPU.
From 240, the buffers 700, 701, 702, 703,
ADR, DATA, XCS, R via 704, 705
D, WR, and RST signals are received, and write / read to each register (not shown) is performed.

The buffer 70 shown in FIG.
XPHS signal, YPHS input through 8,709
The signal is output by one clock (C) by the F / Fs 714 and 715.
K) Delay by minutes. The delayed signal is input to each circuit of FIGS. Similarly, a later-described HS signal input through the buffer 710 is delayed for a predetermined time by the F / Fs 716 and 721, and is transmitted via the AND gate 722 to the main scanning address generator 723 and the sub-scanning address generator 72 shown in FIG.
4 is input. Further, the CLK signal input through the buffer 711 and the CLK signal
The XCLK signal inverted through 17 is input to each circuit of FIGS.

The main scanning address generator 723 has, in addition to the above-mentioned section signals LE), an XPH representing the phase of the main scanning.
WR0,2,4,6 for making various settings of S signal and counter
8, A and C are input. This main scanning address generator 7
23, the main scanning write address (XA
W) and main scanning read address (XAR) from DRAM
Is output.

FIG. 10 and FIG. 11 are detailed block diagrams of the inside of the sub-scanning counter 724.

The sub-scanning counter 724 is for writing (W)
Y counter 1002 for reading each of M, C, Y, and K (R0, R1, R2, R3)
3 to 1006. 1000,1
001 is based on the values set in the two registers WRY12 and WRY26.
02 to 1006 are enabled.

FIG. 12 is a block diagram showing in detail the structure of each of the read and write Y counters in the sub-scanning counter 724.

PE is a sub-scanning section signal input to each Y counter, delayed by 6 clocks by the F / F 1200, and connected to the CK terminal of the F / F 1203 and the F / F 120
4 is input to the D terminal. F / F1203 has F / F
When the output from 1200 transitions from “L” to “H”, the inversion of the internal state is input. A port signal PRESET from the CPU 240 is connected to a PR terminal of the F / F 1203.
Is input, and can be arbitrarily preset by the CPU 240. The output signal of the F / F 1203 is input to the select terminal of the 2TO1 selector 1205. The register WR0 is input to the A input terminal of the 2TO1 selector 1205, and the register WR1 is input to the B terminal input.
Is set, and one of them is selectively input to the load value WR of the 13-bit address counter 1207. In a normal copy operation, the same value is set for both WR0 and WR1, but when operating in a spine mode described later, different values are set for WR0 and WR1, respectively.

Inverted output of F / F 1204 and F / F 120
The output from 0 is input to the LD terminal of the address counter 1207 through the NAND gate 1206. With this configuration, the address counter 1207 is loaded at the moment when the section signal PE is enabled.

Also, a signal obtained by inverting the HS signal generated from the main scanning synchronization signal (HSYNC) by the inverter 1202 and the main scanning section signal EN are ORed by the OR gate 1208.
This signal is input to the enable terminal (ENB) of the address counter 1207. Address counter 1207
Performs a count operation for the number of times according to the EN signal in one main scanning section synchronized with the HS signal.

W input to address counter 1207
R3 is an up-count / down-count switching signal. When "L", the address counter 1207 counts up, and when "H", it counts down.

The five Y counters 10 in FIGS. 10 and 11
The output of each Y counter from 02 to 105 is YAW
0, YAR1, YAR2, YAR3, and YAR4 are input to the address selection unit 725 shown in FIG.

Then, the five Y counter outputs YAW0, YAR1, YAR2, YAR3, and YAR are output by the address selector 725 in accordance with the main scanning and sub-scanning phases.
4 switching control and four address signals A0 to A
3 is output to the external image memory 217 (FIG. 2) via the output buffers 729 to 732.

On the other hand, the RCCON 726 generates WE, RAS, and CAS strobe signals required for accessing the DRAM and a DIR signal for controlling the I / O port of the data controller 219.

RAS, C generated by RCCON 726
The AS and WE signals are supplied to delay lines 727 and 728, respectively.
2 via the output buffers 733 to 735. Delay lines 727, 7
28, RAS and C are provided so that data can be accessed properly according to the characteristics of the image memory to be controlled.
The timing of both AS signals is adjusted. The WE signal generated in the same manner passes through the output buffer 735 and
Is output to the image memory 217. The DIR signal generated in the same manner is output via an output buffer 736 as shown in FIG.
Is output to the data controller 219.

According to these address signals and memory control signals output from address controller 218,
Image data is exchanged between the data controller 219 and the image memory 217. Data controller 21
In 9, after switching between data write and data read, padding of image data necessary for decoding, and control of the order of data access when performing editing processing such as image rotation, etc., the image data is The data is passed to the above-described decoding unit in the processing unit 220.

[Operation in the spine mode] FIG. 13 is a flowchart in the spine mode in the present embodiment.

First, in step S10, an operator (user)
It is determined whether or not the spine mode is selected by an operation unit (not shown). If the spine mode has not been selected, the flow advances to step S90 to copy in the normal mode, and ends. On the other hand, if the spine mode is selected, the operator is requested to specify the document size and the recording paper size to be output in step S20, and the address is set.

That is, when the operator finishes the specification of the document size and the recording paper size, the CPU 240 sets the write address start values of the front and back sides to the registers WR0, WR0 of the Y counter 1002 for counting the write addresses inside the address controller 218. Set to WR1. In the case of the front side, since the image is stored from the head address of the image memory 217, the write start address is 0 and W
0000h is set in R0.

In the case of the spine mode, the bank is switched by dividing the image memory 217 into two. In the present embodiment,
Since input / output of image data to / from the image memory 217 is performed in units of 4 × 4 pixels, the address start value on the back side is 4
This value is set to [1/2] of 32 mm, that is, [1/4] of the number of pixels corresponding to 216 mm. Similarly,
Y counters 1003-1 for counting read addresses
006 registers WR0 and WR1 have a Y counter 10
02 is set to the same value as the registers WR0 and WR1.

When the address setting is completed, step S4
At 0, the operator is requested to set the spine width. CPU 24
0 stores a spine width specified by the operator, and generates a section signal having a blank section corresponding to the spine width when generating a section signal described later.

Next, in step S50, the front side of the original is read.
From the CPU 240 to the F / F 12 inside the controller.
03, a “L” PRESET signal is sent and F /
F1203 is preset. By this, F / F
The output of the address counter 1203 becomes "L" at the moment when the write sub-scanning section signal WPE becomes "H".
207 is loaded with the value of WR0 selected by the 2TO1 selector 1205, and the front side original is written into the memory from address 0. Next, step S
At 60, the original on the back side is read. When the writing sub-scanning section signal for reading the original becomes “H”, the F /
The output of F1203 is inverted to "H", and the value of WR1 selected by the 2TO1 selector 1205 is loaded into the address counter 1207. In this way, the back side document is written from the address of 1/4 of the number of pixels of 216 mm.

When reading of the original is completed, step S
By generating a spine section signal at 70, a lead section signal to be output to the printer is set. Each color sub-scanning section signal, which will be described later, sent from the printer is a signal that becomes “H” by the length of the paper size.
The section signal generating section 230 processes these sub-scanning section signals input from the printer into image section signals in which the front lead section and the rear lead section are discontinuous, and outputs the processed signal to each image processing section.

FIG. 14 is a timing chart showing each section signal generated by the section signal generating section 230 based on the sub-scanning section signal from the printer.

In FIG. 14, MPE, CPE,
YPE and KPE are transmitted from the printer to the section signal generator 230.
Is "H" for a time corresponding to the length of the paper size. MPE1, CP
E1, YPE1, and KPE1 are sub-scanning section signals output from the section signal generation unit 230. In the normal mode shown in FIG. 3B, the signal delays by the internal delay time ΔT, rises to “H”, and sets the length of the document size. The “H” state is maintained for a time corresponding to the above.

However, the signal output in the sub-scanning section in the spine mode shown in FIG. 7C temporarily drops to "L" after "H" continues for the length of the front printing section. Then, after maintaining the “L” state for a time (margin section) corresponding to the spine width specified by the operator, the state changes to “H” again.
Then, after outputting a time (H) corresponding to the length of the back side document size (back side printing section), it becomes "L". Accordingly, similarly to the case of reading a document, the F / F 120
When the image output is started after presetting No. 3, the value set in WR0 is loaded as the front address at the first rise to "H" indicating the sub-scanning section on the front side, and the second "" indicating the back side section is performed. H ”when rising
The value set in R1 is loaded as the back address.

FIG. 15 is a circuit diagram showing a part of the internal circuit of section signal generating section 230.

For example, the MPE signal generated by the printer is processed into an MPE1 signal separated into two image sections (a front section and a back section) by the section signal processing section 230a in FIG. 15, and the address controller 218 and the data in FIG. Output to the controller 219. The configuration shown in FIG. 15 is provided in plurality in accordance with each of the other signals CPE, YPE, and KPE, and the CLK terminal of each element in FIG.
Signal is input.

In the section signal processing section 230a, the MPE
The signals are first sent to DF / F 2301, 2302 and NAND
The gate 2304 processes the signal into a one-pulse signal that outputs “H” only at its rising edge, and the selector 2303
, The input terminal of the AND gate 2307, the clear terminal of the JKF / F 2310, and the load terminal LD of the 8-bit down counter 2311.

The input terminal of AND gate 2305 has D
The output of the F / F 2301 and the RC output of the counter 2311 are connected, and this RC output is “H” in an initial state.
When the MPE signal becomes “H”, the output of the AND gate 2305 also becomes “H”. The output of the AND gate 2305 is 1
Enable terminal EN of 3-bit down counter 2306
, Whereby the counter 2306 is enabled. At the same time, the output of the AND gate 2307 becomes “L”, the value of WR3 selected by the selector 2303 is loaded into the counter 2306, and the counting operation is started.

The set value of WR3 is the internal delay time ΔT of the section signal MPE1 in FIG. Therefore, by setting this value arbitrarily, the delay amount of the effective image section (“H” section) of each section signal can be changed. At this time, the value set in WR6 is loaded into the counter 2311. The output of the counter 2306 is directly input to the comparator 2309, and is compared with the value of WR5. Here, when the output of the counter matches WR5, “H” is output from the JKF / F2310. This signal is the MPE1 signal obtained by processing the MPE signal.
With the same configuration, the section signals CPE1, YPE1, and KPE1 are obtained by processing the CPE, YPE, and KPE signals.

Incidentally, the counter 2306 is sequentially down-counted, and when the value of the counter 2306 becomes 0, RC
"L" is output from the output. This allows AND gate 2
The output of the counter 307 becomes “L”, and the counter 2306 is in the load state. At this time, since the select signal of the selector 2303 is “H”, WR4
Is loaded. This set value of WR4 is a value for setting the spine width, and by setting a predetermined value based on the designation of the operator, the margin section can be varied.
An interval signal for arbitrarily changing the spine width can be generated.

On the other hand, the RC output of the counter 2306 is input to the enable terminal EN of the counter 2311 via the inverter 2308, so that the counter 2311 operates only when the RC output of the counter 2306 becomes "L". Has become. When the value of the counter 2311 becomes 0, "L" is output from the RC output, so that the enable signal to the counter 2306 also becomes "L". Thus, the counting operation of the counter 2306 stops.

In the back cover mode in the present embodiment,
WR6 is set to “2”, and the section signal for the front section and the back section is output as “H”.
While the operation is stopped, the section signal is held at "L".

When the setting of the section signal is completed, the process proceeds to step S80 in FIG. 13, where the CPU 240 informs the printing section that the printing is possible, executes printout on recording paper, and ends the processing.

By performing the control according to the present embodiment as described above, the image stored in the image memory 217 is separated into a front surface and a back surface, and printed out by two scans. Can be variably set in accordance with the number of sheets to be bound, so that the spine (closed) portion of the output image can be formed in an arbitrary width designated in advance by the operator.

(Second Embodiment) FIG. 16 is a flowchart of a spine mode according to the second embodiment.
Other configurations are the same as those of the first embodiment. In the first embodiment, the operator has to change the spine width setting every time depending on the number of recording sheets to be bound and the type of recording sheets. In the modified embodiment, the spine (closed) width is automatically set according to the number of recording sheets to be bound.

In FIG. 16, steps for performing the same processing as in FIG. 13 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

If the spine mode is selected, the operator is requested to specify the document size, the size and the number of recording sheets to be output in step S25, and the address is set.

That is, when the operator completes the specification of the document size, the recording paper size, and the number of recording papers, the CPU 24
0 is the write address start value for each of the front and back surfaces, and the registers WR0 and W of the Y counter 1002 for counting the write address in the address controller 218.
Automatically set to R1. In the case of the front, image memory 2
Since the image is stored from the start address of No. 17, the write start address is 0 and 0000h is set in WR0.

In the case of the spine mode, the bank is switched by dividing the image memory 217 into two. In the present embodiment,
Since input / output of image data to / from the image memory 217 is performed in units of 4 × 4 pixels, the address start value on the back side is 4
This value is set to [1/2] of 32 mm, that is, [1/4] of the number of pixels corresponding to 216 mm. Similarly,
Y counters 1003-1 for counting read addresses
006 registers WR0 and WR1 have a Y counter 10
02 is set to the same value as the registers WR0 and WR1.

Next, the front side of the original is read in step S50, but before reading, the address controller 218 is read.
From the CPU 240 to the F / F 12 inside the controller.
03, an “L” signal is sent, and the F / F 1203 is preset. As a result, the output of the F / F 1203 becomes “L”, and at the moment when the write sub-scanning section signal WPE becomes “H”, the address counter 1207 supplies W
The value of R0 is loaded, and the front side original is written into the memory from address 0. After reading the front side document, the back side document is read in step S60.
When the writing sub-scanning section signal for reading the original becomes “H”, the output of the F / F 1203 is inverted to “H”, and the address counter 1207 outputs WR 1
Is loaded. Thus, the back side document is 216 mm
It is written from the address of 1/4 of the number of pixels.

When reading of the original is completed, step S
At 70, a read section signal for output to the printer is set. The CPU 240 stores the spine width required for each recording sheet in advance by the CPU 240 itself.
Then, an optimum spine width is set based on this value and the number of recording sheets specified in step S25. In this way, the CPU 240 automatically sets the spine width according to the number of recording sheets to be bound, so that the operator can save time and effort and can quickly and efficiently output an image.

The sub-scanning section signal of each color sent from the printer is a signal which becomes "H" for the length of the paper size. The section signal generation section 230 processes the input sub-scanning section signal into a front section read section signal and a rear section read section signal as described above, and outputs the processed signal to each image processing section.

When the setting of the section signal is completed, step S8 is performed.
Then, the CPU 240 informs the print unit that the print unit is ready for printing, executes printout on recording paper, and ends the process.

As described above, by performing the control according to the present embodiment, the image stored in the image memory 217 is separated into a front surface and a back surface and printed out by two scans. Automatically and optimally set in accordance with the number of sheets to be bound, the spine (closed) portion of the output image can be automatically formed with an optimum width. Therefore, the trouble of having to change the setting each time depending on the number of recording sheets to be bound and the type of recording sheets can be eliminated, and the spine can be accurately formed.

(Third Embodiment) The present invention is not limited to the above embodiment. In the first and second embodiments, in the spine mode, the sub-scanning section signal is separated and processed so as to have two image sections by a blank section. The section signal may be processed so as to have two image sections separated by a blank section based on the set spine width. In this case, the configuration may be such that all the control of the sub-scanning address controller 218 described in the first and second embodiments is applied to the main scanning address control.

FIG. 17 is a timing chart showing each section signal generated by the section signal generation section 230.

As the sub-scanning section signal, the same section signal as MPE1 (CPE1, YPE1, KPE1) in the normal mode shown in FIG. 14B is used. Instead, as shown in FIG. 17, the main scanning section signal (FIG. 17B) is processed for each horizontal synchronization signal HSYNC (FIG. 17A), and the two image sections of the front side printing section and the back side printing section are processed. Main scanning section signal (see FIG. 17)
(D)).

In FIG. 17, EN in FIG. 17B is a main scanning section signal generated in the section signal generation circuit 230 as described later, and is “H” for a time corresponding to the length of the sheet size.
It has become. RLE is a main scanning section signal output from the section signal generating section 230. In the normal mode shown in FIG. 7C, the internal delay time is delayed by ΔT and then rises to “H”, and the “H” state is maintained for a time corresponding to the length of the document size.

However, in the case of the spine mode shown in (D), after "H" has continued for the length of the front printing section, it temporarily drops to "L". Then, after maintaining the “L” state for a time corresponding to the spine width specified by the operator or the CPU 240, the state changes to “H” again. Then, after outputting a time (H) corresponding to the length of the back side document size (back side printing section), it becomes "L". Therefore, when the image output is started, the first rising to “H” indicating the main scanning section of the front side and the second rising to “H” indicating the back side printing section correspond to the front side corresponding to each image. The address and the back address are loaded as start addresses.

FIG. 18 is a block diagram showing a part of the section signal generation circuit 230, and shows a block for generating a main scanning section signal EN. It should be noted that VCLK is input as a clock to all constituent elements in FIG.

Reference numeral 232 denotes a 13-bit counter for counting the horizontal synchronization signal HSYNC. 234 and 236
Is a comparator, the registers WR1 and WR2, each of which has an arbitrary value set by the CPU 240, and a counter 232.
Compare if the outputs of match. Both comparators 234 and 236 output “H” when the counter output and the register value are equal, and output “L” otherwise. 238 is a J / KFF, and the comparator 23
4 is input to the J terminal, and the output of the comparator 236 is input to the K terminal. The output of the J / KFF 238 becomes the main scanning section signal EN.

The main scanning section signal EN thus generated
Is output to the section signal processing unit 230b shown in FIG.

The section signal processing section 230b has exactly the same configuration as the circuit 230a of FIG. 15 of the first embodiment.
Although the same components are denoted by the same reference numerals, the clock input to each component is not HSYNC, but VCLK.
Is different.

Therefore, in FIG. 18, if a value corresponding to the start position of the section signal is input to WR1 and a value corresponding to the end position of the section signal is input to WR2, J / K is set at the start position.
The output of the FF 238 changes from “L” to “H” to start the effective section of the section signal, and from the “H” to “L” at the end position, the effective section of the section signal ends. That is, FIG.
An EN signal is generated at the timing shown in FIG.

By inputting the generated EN signal to the section signal processing section 230b, the main scanning section signal RLE1 is processed and generated as described with reference to FIG. FIG. 17C shows the normal mode, and FIG.
Represents RLE1 in the spine mode.

The printing operation is performed by the first and second operations.
This embodiment is the same as the first embodiment, and the present embodiment can also provide the same effects as the first and second embodiments.

(Fourth Embodiment) In each of the above embodiments, the operator arbitrarily sets the spine width according to the number of recording sheets, or the CPU 240 sets the spine width. In this example, the spine width is set in consideration of the thickness of the recording paper.

FIG. 20 is a flowchart of the fourth embodiment. The overall flow is the same as in the first or second embodiment.

However, in the case of the present embodiment, step S30
Requesting the operator to set the original size, the size of the recording paper to be output, the number of recording papers sandwiched between the front and back sides during bookbinding, and the type of paper classified according to the paper thickness. The CPU 240 stores in advance the spine width required for each recording sheet determined according to the thickness of the sheet by the CPU 240 itself. Then, based on this value and the number of recording sheets specified in step S30, the CPU 240 automatically sets an optimum spine width in step S40. Then, after reading the original on the front and back surfaces in steps S50 and S60, the process proceeds to step S70, where a section signal having two image sections separated by a blank section based on the set spine width is generated.

The printing operation is the first and second operations.
This embodiment is the same as the first embodiment, and the present embodiment can also provide the same effects as the first and second embodiments.

(Fifth Embodiment) The present invention is not limited to the above embodiments. In each of the above embodiments, the reading of the front image and the reading of the back image are performed separately. However, when one document is divided into two to form the front image and the back image, depending on the size of the document, The original may be read in one scan by setting the address start value on the back side to half the original size.

FIG. 21 is a flowchart according to the fifth embodiment.
An example in which scanning is performed will be described.

First, in step S10, it is determined whether or not the operator has selected the spine mode using an operation unit (not shown). If the backstrip mode is selected, the operator is requested in step S20 to specify the size of the document serving as the front surface of the cover and the size of the recording paper to be output. Next, the surface,
The write address start value of each back surface is set in registers WR0 and WR1 of Y counter 1002 for counting the write address in address controller 218. On the other hand, the registers WR0 and WR1 of the Y counters 1003 to 1006 for counting the read address have the first value.
In the case of the embodiment, 0000h is set to WR0, and the address start value on the back side is の of 432 mm, that is, 2
A value of 1/4 of the number of pixels corresponding to 16 mm was set.

However, in the present embodiment, since one document is divided into two at the address start value on the back surface to form images on the front surface and the back surface, the number of pixels corresponding to half the size of the document size Is set to 1/4. In the first embodiment, the reading operation is performed twice on the front surface and the back surface. In the present embodiment, however, the address start value on the back surface is set to one.
Since the original is divided into two and the front and back images are read, the original is read only once. Therefore, WR0, W
R1 is set to 0000h.

When the setting of the write address is completed, the spine width is set in step S40, and 1 is set in step S55.
The original is read by scanning. In the first embodiment, the scanning operation is performed twice to read the original on the front surface and the back surface, but in the present embodiment, the scanning operation is performed once.

After the scanning operation, that is, in step S5
The output operation to the printer after 5 is the same as that of the first embodiment. Of course, the original reading in other embodiments may be performed by one scan.

According to the above-described embodiment, the same effects as those of the first to fourth embodiments can be obtained. In addition, by reading the original in one scan, the spine (closed) portion can be more quickly obtained. Can be formed.

[0129]

As described above, according to the present invention, the bookbinding set in the spine mode in which the image signals stored in the image memory are discontinuously read out in the first image section and the second image section separated from each other. The user can arbitrarily or automatically set the margin width of the spine section based on the number of recording media and the type of recording paper, so that a spine (closed) portion having the optimum width can be formed quickly and accurately. become.

[Brief description of the drawings]

FIG. 1 is an external view of a first embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a block diagram for explaining in detail the flow of an image signal in an image processing unit.

FIG. 3 is a block diagram for describing in detail the flow of an image signal in an image processing unit.

FIG. 4 is a timing chart in the first embodiment.

FIG. 5 is a timing chart showing the main scanning section in the first embodiment in detail by expanding a time axis.

FIG. 6 is a circuit diagram showing a circuit for generating XPHS and YPHS signals.

FIG. 7 is an overall block diagram of an address counter according to the first embodiment.

FIG. 8 is an overall block diagram of an address counter according to the first embodiment.

FIG. 9 is an overall block diagram of an address counter according to the first embodiment.

FIG. 10 is a detailed block diagram of a sub-scanning counter according to the first embodiment.

FIG. 11 is a detailed block diagram of a sub-scanning counter according to the first embodiment.

FIG. 12 is a block diagram illustrating in detail the configuration of each Y counter in the sub-scanning counter according to the first embodiment.

FIG. 13 is a flowchart showing the operation of the present invention in the first embodiment.

FIG. 14 is a timing chart showing each section signal generated by the section signal generation section 230 based on the sub-scanning section signal from the printer in the first embodiment.

FIG. 15 is a circuit diagram showing a part of an internal circuit of a section signal generation unit 230.

FIG. 16 is a flowchart of a spine mode according to the second embodiment.

FIG. 17 is a section signal generation unit 2 according to the third embodiment.
3 is a timing chart showing each section signal generated by the section 30.

FIG. 18 is a block diagram showing a part of a section signal generation circuit 230 according to the second embodiment.

FIG. 19 is a block diagram illustrating a section signal processing unit according to the third embodiment.

FIG. 20 is a flowchart of the fourth embodiment.

FIG. 21 is a flowchart of the fifth embodiment.

[Explanation of symbols]

 200 CCD image sensor 201 A / D & S / H section 202 Shading correction section 203 Input masking section 204,225 Magnification processing section 206 Color space conversion section 207 Encoder 208 Feature extraction section 217 Image memory 218 Address controller 219 Data controller 220 Data Processing unit 226 Gamma correction unit 227 Edge enhancement unit 230 Section signal generation unit 240 CPU

Claims (10)

[Claims] An image signal generating unit configured to scan an image to be recorded to optically form an image and generate an image signal corresponding to the scanned image; and an image memory for temporarily storing the image signal. A control unit that stores the image signal in the image memory and controls the stored image signal to be read discontinuously in a first image section and a second image section that are separated from each other; Image signal output means for performing predetermined signal processing on an image signal having an image section and outputting the signal to an output device; and section signal generation means for generating a plurality of effective image section signals based on a signal from the output device. An image having a margin between the first image section and the second image section by the control means storing and reading the image signal based on the effective image section signal. An image processing apparatus for outputting a signal to the output device, the length of the discontinuous image period by setting arbitrarily,
An image processing apparatus comprising: a margin setting unit that optimally sets the width of the margin according to the amount of a recording medium used in the output device. 2. The image processing apparatus according to claim 1, wherein the margin setting unit stores a value input by a user and sets a length of the discontinuous image section according to the input value.
An image processing apparatus according to claim 1. 3. The margin setting means stores the number of recording media to be used for the output device input by a user, and automatically sets the length of the discontinuous image section according to the number of recording media. The image processing apparatus according to claim 1, wherein: 4. A recording medium for use in the output device, which is input by a user by the margin setting means, the storage means storing in advance the width of the margin necessary for each type of recording medium according to its thickness. And the length of the discontinuous image section is automatically set according to the number of sheets and the width of the margin of the kind stored in the storage unit. The image processing device according to claim 1. 5. The memory address control means including a plurality of read address control means, wherein the margin setting means controls a memory address in the scanning direction and a memory address in another direction substantially orthogonal to the scanning direction. The image according to any one of claims 2 to 4, further comprising: a read address assigning unit that assigns a read address according to the length of the set discontinuous image section to the plurality of read address control units. Processing equipment. 6. The image processing apparatus according to claim 5, wherein the plurality of read address control means controls a read address in the scanning direction according to a width of the margin. 7. The image processing apparatus according to claim 5, wherein the plurality of read address control means controls the read address in the other direction according to a width of the margin. 8. The image processing apparatus according to claim 1, wherein the image to be recorded is scanned by two scans. 9. The image processing apparatus according to claim 1, wherein scanning of the image to be recorded is performed by one scan. 10. The image signal generating unit includes a unit that divides the image signal into m × n (m and n are natural numbers) pixel blocks and encodes the divided image blocks. The image processing apparatus according to claim 1, further comprising a unit configured to decode an encoded block read from the memory.